DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-8 have been presented for an examination and pending in the application.
Allowable Subject Matter
Claims 4-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art of record does not teach the claimed connection details; therefore, allowable over the prior art of record.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Pihet (US 2017/0329388 A1).
Examiner relies on the entire teachings of the Pihet reference for this rejection; hence, the examiner advises the applicant to carefully consider the entire teachings of the Pihet reference to better understand the examiner’s position & the interpretations applied to the claimed invention. The examiner also notes that one of the cited reference Jain et al. (US 2018/0262527 A1) shows well-known and common practices in the art/industry of Controller Area Network (CAN) for using multiplexor(s) for inputting/outputting signals in the art/industry. See all the prior art of record for such well-known and/or common practice teachings in the art of CAN system.
The Pihet reference teaches functionally equivalent limitations of the claimed invention, when the examiner applies Broadest Reasonable Interpretation to the present claims 1-3, as follows:
CLAIMS 1-3
Pihet REF. TEACHINGS (emphasis underlined)
1. A microcontroller unit, comprising: a controller area network controller,
PAR 25, “circuit 10 that may be used to couple, for example, a microcontroller to a data lines of a CAN bus”
generating a transmission signal in digital form for a controller area network;
Par 25, “microcontroller may generate a binary input data signal, which is supplied to TxD pin of the CAN transceiver 10”
a digital signal remapping circuit, remapping the transmission signal into a first chip output signal and a second chip output signal;
Obvious from the teachings of the Par 27, “transmitter circuit 110 is configured to receive an input data signal Sin at pin TxD and to generate a corresponding first bus signal Vbus1, which output at the bus lines connected to pins CANH and CANL”
a first pin, configured to output the first chip output signal to drive a differential positive signal line of the controller area network; and a second pin, configured to output the second chip output signal to drive a differential negative signal line of the controller area network.
Par 27, “CAN bus, differential signaling is used…The common mode voltage pins CANH and CANL”
2. The microcontroller unit as claimed in claim 1, further comprising: a third pin, coupled to the differential positive signal line of the controller area network; a fourth pin, coupled to the differential negative signal line of the controller area network; and a comparator,
Obvious from figure 2 with accompanying description for the connection between CANH & CANL to the receiver circuit 120, see also par 30, “two inputs of the comparator circuit 121 are connected to the pins CANH and CANL”
receiving signals from the third pin and the fourth pin for comparison, to generate a received signal in digital form, which is coupled to the controller area network controller.
Par 31, “comparator 121 and configured to generate an output data signal Sout that is provided at the RxD pin”
3. The microcontroller unit as claimed in claim 1, wherein the digital signal remapping circuit comprises: a first multiplexer, outputting the first chip output signal as indicated by the transmission signal; and a second multiplexer, outputting the second chip output signal as indicated by the transmission signal.
Not expressly disclosed, but using one or more multiplexors for outputting signals are well-known and/or obvious in the art (see one of the claimed invention & well-known prior art teachings figure 5, column 59, “the CAN controller 512 is a digital logic device that operates the transceiver multiplexor 514 to use on or more of the transceivers 516A-516C to transmit data bits through the CAN bus”(examiner also notes it is well known & commonly practiced in the industry/art that multiplexors can easily be added when needed for proving the claimed propose of outputting a signal or more than one signals)
The examiner notes that the Pihet reference does not expressly disclose or identically used or labeled the term “remapping circuit”; however, the teachings of the “transmitter circuit 110” discloses/teaches the functionally equivalent claimed function of the above not expressly labeled/used (i.e., the claimed invention of the first and second “chip output signals” have no claimed functions) “remapping the transmission signal into” two signals recitations; furthermore, the claimed “transmission signal” or “remapping” function is not utilized by the claimed invention for performing any functions other than to merely output signals to CAN (i.e., the Pihet reference teaches the functionally equivalent outputting signals to CAN). Therefore, it would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to come up with the claimed invention from the teachings of the Pihet reference for the detailed teachings and reasons discussed above.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER B SHIN whose telephone number is (571)272-4159. The examiner can normally be reached 8:00-4:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, IDRISS N ALROBAYE can be reached at 571-270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER B SHIN/Primary Examiner, Art Unit 2181
Prosecution Insights