DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 recites “wherein an upper surface of the channel contact and an upper surface of the line pattern are coplanar with each other; the upper surface of the channel contact and a lower surface of the line pattern are coplanar with each other” is unclear and indefinite as to an upper surface of the line pattern can be both are coplanar an upper surface of the line pattern and with a lower surface of the line pattern as the same time.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9, 15-24 and 31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al. 20180261616.
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Regarding claim 1, figs. 3-6 of Cho disclose a semiconductor memory device comprising:
a source layer (100 and CSR) (fig. 4A);
a stack structure ST including a plurality of gate electrodes EL sequentially stacked apart from one another, on the source layer;
a channel structure VP/DS extending in a first direction D3 penetrating the gate electrodes and connected to the source layer;
a cutting pattern (142) extending in a second direction D1 that intersects the first direction, and cutting the stack structure;
a cell wiring structure (Bit lines BL1-Bln) on the stack structure;
a channel contact (portion of 172 in layer 160) connecting the channel structure and the cell wiring structure, between the stack structure and the cell wiring structure; and
a line pattern 166 extending in the second direction D1, between the stack structure ST and the cell wiring structure, and overlapping with the cutting pattern in the first direction,
the line pattern being 162 at a same level as the channel contact (same as 172 in layer 160).
Regarding claim 2, fig. 4A of Cho discloses further comprising: a contact pattern (portion of 172 at layer 170) connecting the channel contact and the cell wiring structure, wherein the line pattern is at a different level from the contact pattern.
Regarding claim 3, fig. 4A of Cho discloses wherein the line pattern 162 is spaced apart from the cell wiring structure (Bit lines BL1-Bln) in the first direction.
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Regarding claim 4, fig. 3 of Cho discloses wherein in a third direction D2 that intersects the first and second directions, a width of the line pattern 162 is greater than a width of the cutting pattern (see fig. 3 and compare the dimensions - (compare dotted line to non-dotted line).
Regarding claim 5, fig. 3 of Cho discloses wherein the cell wiring structure includes a conductive line BL1, which extends in a third direction D2 that intersects the first and second directions, and the channel contact connects the channel structure and the conductive line.
Regarding claim 6, par [0034] of Cho discloses wherein the source layer includes polysilicon (poly-Si) film doped with impurities (substrate can be polysilicon – par [0034] and CSR may have a second conductivity (e.g., n-type conductivity) - par [0039] form on polysilicon substrate).
Regarding claim 7, par [0090] of Cho discloses wherein the cutting pattern includes a silicon oxide film.
Regarding claim 8, fig. 4A of Cho discloses wherein the line pattern 162 is at a same level as the channel contact (portion of 172 in layer 160).
Regarding claim 9, fig. 4A of Cho discloses wherein the channel structure includes a semiconductor film VP and a data storage film DS, the semiconductor film extending in the first direction to intersect the gate electrodes, and the data storage film between the semiconductor film and the gate electrodes, and an end of the semiconductor film contacts the source layer.
Regarding claim 15, fig. 3 and par [0023] of Cho discloses further comprising: a peripheral circuit structure including a peripheral circuit substrate (portion of 100 under peripheral circuit region) and a peripheral circuit element (peripheral circuit region may include row decoder regions ROW DCR, a page buffer region PBR, a column decoder region COL DCR, and a control circuit region) on the peripheral circuit substrate, wherein the stack structure is between the source layer and the peripheral circuit structure.
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Regarding claim 16, fig. 3-4 and 16-17 (for clarity of layout) of Cho discloses semiconductor memory device comprising:
a peripheral circuit structure including a peripheral circuit substrate and a peripheral circuit element on the peripheral circuit substrate (par [0023]);
and
a memory cell structure stacked (figs. 16-17 showing peripheral on the outside of memory cell structure) on the peripheral circuit structure, the memory cell structure includes a source layer CSR including a first surface (right surface) facing the peripheral circuit structure and a second surface (left surface) that is opposite to the first surface;
a stack structure including a plurality of gate electrodes EL sequentially stacked apart from one another, on the source layer;
a channel structure VP/DS (fig. 4A) extending in a first direction D3 penetrating the gate electrodes and connected to the source layer;
a cutting pattern 142 extending in a second direction D1 that intersects the first direction, and cutting the stack structure;
a conductive line (all line on top of 170 in fig. 4B) extending in a third direction D2 that intersects the first and second directions, and being between the stack structure and the peripheral circuit structure (see fig. 16);
a channel contact (portion of 172 in layer 160) connecting the channel structure and the conductive line, and being between the stack structure and the conductive line; and
a line pattern (all line pattern on 160 inlcuding162) extending in the second direction, being between the stack structure and the conductive line, and overlapping with the cutting pattern in the first direction.
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Regarding claim 17, fig. 4A of Cho discloses wherein an upper surface of the channel contact and an upper surface of the line pattern are coplanar (top surface of 160 is the coplanar) with each other; the upper surface of the channel contact and a lower surface of the line pattern are coplanar with each other.
Regarding claim 18, fig. 4A of Cho discloses wherein the line pattern is spaced apart from the conductive line in the first direction.
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Regarding claim 19, fig. 4A of Cho discloses wherein in the third direction, a width of the line pattern is greater than a width of the cutting pattern (compare dotted line to non-dotted line).
Regarding claim 20 (see rejection of claim 9 above) Cho discloses wherein the channel structure includes a semiconductor film and a data storage film, the semiconductor film extending in the first direction to intersect the gate electrodes, and the data storage film between the semiconductor film and the gate electrodes, and an end of the semiconductor film contacts the source layer.
Regarding claim 21, fig. 4A of Cho discloses further comprising: a gate pattern EL between the stack structure and the conductive line and between the cutting pattern and the conductive line, wherein the channel structure extends in the first direction to penetrate the gate pattern.
Regarding claim 22, fig. 4B of Cho discloses wherein the line pattern contacts the gate pattern.
Regarding claim 23, fig. 4A of Cho discloses wherein the gate pattern includes a first portion and a second portion, the first portion penetrated by the channel structure, and the second portion between the cutting pattern and the line pattern, and the first and second portions are spaced apart from each other by an isolation pattern (pattern of 140) extending in the second direction.
Regarding claim 24, fig. 3 of Cho discloses wherein in the third direction D2, a width of the second portion is greater than a width of the line pattern (compare dimensions between 142 to that of between VP).
Regarding claim 31 (see rejection of claim 16), figs. 3-4 of Cho discloses an electronic system comprising:
a main substrate 100; a semiconductor memory device including a peripheral circuit structure (par [0023]) and a memory cell structure (figs. 3-4) sequentially stacked, on the main substrate; and
a controller (an external device (e.g., a memory controller) – par [0027]) electrically connected to the semiconductor memory device, on the main substrate (there is electrical connect to the memory device on the main substrate), the memory cell structure including:
a source layer including a first surface facing the peripheral circuit structure and a second surface that is opposite to the first surface;
a stack structure including a plurality of gate electrodes sequentially stacked apart from one another, on the source layer;
a channel structure extending in a first direction, penetrating the gate electrodes and connected to the source layer;
a cutting pattern extending in a second direction that intersects the first direction, cutting the stack structure;
a conductive line extending in a third direction that intersects the first and second directions, between the stack structure and the peripheral circuit structure;
a channel contact connecting the channel structure and the conductive line, between the stack structure and the conductive line; and
a line pattern extending in the second direction, between the stack structure and the conductive line, and overlapping with the cutting pattern in the first direction.
Conclusion
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/VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893
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