Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 18/807222, filed on 01/13/2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 9, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kanno (US Pub. US 2022/0237114) in view of Schauer et al. (US Pub. 2021/0042050).
Regarding independent claim 1, Kanno discloses a storage device (Fig.5: memory system 3A) configured to communicate with a first host (Fig.5: Information processing device D0), a second host (Fig.5: Information processing device D1), and a supervisor ([0076]: At least one of the information processing devices D.sub.0 to D.sub.M may be a virtual machine), the storage device (Fig.5: memory system 3A) comprising:
a nonvolatile memory device (Fig.5: Nonvolatile memory 5) comprising a first namespace (Fig.5: Namespace NS0) allocated for the first host (Fig.5: Information processing device D0), and a second namespace (Fig.5: Namespace NS1) allocated for the second host (Fig.5: Information processing device D1) ([0078]: the information processing devices D0 and D1 have access rights to their corresponding namespaces NS0 and NS1); and
a storage controller (Fig.5: Controller 4A) configured to, based on the plurality of address mapping tables (Fig.5 and Fig.6: Translation table 20):
access the first namespace (Fig.5: Namespace NS0) based on an input/output request (i.e., first command) from the first host (Fig.5: Information processing device D0); and access the second namespace (Fig.5: Namespace NS1) based on an input/output request (i.e., second command) from the second host (Fig.5: Information processing device D1) ([0108]-[0112]: the read unit 21 reads the read data 9R from the position indicated by PBA corresponding to the namespace NS.sub.M indicated by NSID 6R via the buffer memory F.sub.M corresponding to the namespace NS.sub.M indicated by NSID 6R, and sends the read data 9R to the information processing devices D.sub.M issuing the read command C3 via the interface unit 19. In the present embodiment described above, the nonvolatile memory 5 is divided into a plurality of the namespaces NS.sub.0 to NS.sub.M. The information processing devices D.sub.0 to D.sub.M can access the namespaces whose access rights are granted thereto. Consequently, data security can be improved).
wherein the storage controller (Fig.5: Controller 4A) comprises a first dedicated caching area (Fig.6: first dedicated caching area for Namespace NS0) partitioned to cache address mapping tables having a first table type (Fig.6: a group of NS0) corresponding to the first namespace (Fig.5: Namespace NS0) among the plurality of address mapping tables (Fig.5 and Fig.6: Translation table 20) (Fig.5 and Fig.6: As shown in Fig.6 entries corresponding to namespace NS0 (e.g., LBA200->PBA300, LBA201->PBA301) are grouped together as a table associated with first namespace, while entries corresponding to another namespace (e.g., NS1, NS2 … NSm) are maintained separately).
However, Kanno does not specifically teach a nonvolatile memory device comprising a plurality of address mapping tables because the address mapping tables of Kanno are stored outside of Kanno’s nonvolatile memory device.
Schauer teaches a nonvolatile memory device comprising a plurality of address mapping tables ([0018]: a copy of each of the system lookup table (SLT) and global mapping table (GMT) is maintained in the non-volatile storage array and updated periodically in case of a power failure of the SSD).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate storing mapping tables in a non-volatile storage array, as taught by Schauer into the memory system of Kanno.
Such a modification would have been a predictable design choice because storing the mapping tables within the nonvolatile memory allows the mapping data to be retained in the event of a power failure, thereby improving reliability by preventing data loss in case of a power failure of the memory system (Schauer - [0018]).
Regarding independent claim 19, Kanno discloses a storage device (Fig.5: memory system 3A) configured to communicate with a first host (Fig.5: Information processing device D0) and a second host (Fig.5: Information processing device D1), the storage device (Fig.5: memory system 3A) comprising:
a global address mapping table (Fig.5: translation table 20) stored in a storage controller (Fig.5: controller 4A) comprising a first plurality of address mapping tables and a second plurality of address mapping tables (Fig.5 and Fig.6: As shown in Fig.6 entries corresponding to namespace NS0 (e.g., LBA200->PBA300, LBA201->PBA301) are grouped together as first tables associated with first namespace, while entries corresponding to second namespace (e.g., NS1, NS2 … NSm) are maintained as second tables separately) respectively corresponding to the first host and the second host ([0108]-[0112]: the nonvolatile memory 5 is divided into a plurality of the namespaces NS.sub.0 to NS.sub.M. The information processing devices D.sub.0 to D.sub.M can access the namespaces whose access rights are granted thereto. Consequently, data security can be improved); and
the storage controller comprising: a map data memory device configured to cache at least one of the first plurality of address mapping tables or the second plurality of address mapping tables (Fig.5 and Fig.6: As shown in Fig.6 entries corresponding to namespace NS0 (e.g., LBA200->PBA300, LBA201->PBA301) are grouped together as a table associated with first namespace, while entries corresponding to another namespace (e.g., NS1, NS2 … NSm) are maintained separately); and
a caching manager configured to manage a first occupation guarantee ratio of the first plurality of address mapping tables for the map data memory device (Fig.5 & Fig.6 and [0108]-[0112]: Translation table 20) (Fig.5 and Fig.6: As shown in Fig.6 entries corresponding to namespace NS0 (e.g., LBA200->PBA300, LBA201->PBA301) are grouped together as a table associated with first namespace, while entries corresponding to another namespace (e.g., NS1, NS2 … NSm) are maintained separately. Thus, the controller of Kanno maintains separate mapping-table space for each namespace by grouping of entries per namespace shown in Fig.6. Kanno requires maintaining non-overlapping, namespace-specific portions of the translation table for NS0, NS1, NS2 …).
However, Kanno does not specifically teach a nonvolatile memory device configured to store a global address mapping table.
Schauer teaches a nonvolatile memory device configured to store a global address mapping table ([0018]: a copy of each of the system lookup table (SLT) and global mapping table (GMT) is maintained in the non-volatile storage array and updated periodically in case of a power failure of the SSD).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate storing mapping tables in a non-volatile storage array, as taught by Schauer into the memory system of Kanno.
Such a modification would have been a predictable design choice because storing the mapping tables within the nonvolatile memory allows the mapping data to be retained in the event of a power failure, thereby improving reliability by preventing data loss in case of a power failure of the memory system (Schauer - [0018]).
Regarding claim 2, Kanno teaches wherein the storage controller further comprises a shared caching area partitioned to cache a one or more address mapping tables having different table type from each other, from among the plurality of address mapping tables [0111] In step S803, the read unit 21 reads the read data 9R from the position indicated by PBA corresponding to the namespace NS.sub.M indicated by NSID 6R via the buffer memory F.sub.M corresponding to the namespace NS.sub.M indicated by NSID 6R, and sends the read data 9R to the information processing devices D.sub.M issuing the read command C3 via the interface unit 19).
Regarding claim 3, Kanno teaches wherein a capacity of the first dedicated caching area is determined based on a first allocation ratio configuration request provided by the supervisor (Fig.5 & Fig.6 and [0108]-[0112]: Translation table 20) (Fig.5 and Fig.6: As shown in Fig.6 entries corresponding to namespace NS0 (e.g., LBA200->PBA300, LBA201->PBA301) are grouped together as a table associated with first namespace, while entries corresponding to another namespace (e.g., NS1, NS2 … NSm) are maintained separately. Thus, the controller of Kanno maintains separate mapping-table space for each namespace by grouping of entries per namespace shown in Fig.6. Kanno requires maintaining non-overlapping, namespace-specific portions of the translation table for NS0, NS1, NS2 …).
Regarding claim 4. Kanno teaches wherein a capacity of the shared caching area is determined based on the capacity of the first dedicated caching area (Fig.5 and Fig.6: As shown in Fig.6 entries corresponding to namespace NS0 (e.g., LBA200->PBA300, LBA201->PBA301) are grouped together as a table associated with first namespace, while entries corresponding to another namespace (e.g., NS1, NS2 … NSm) are maintained separately).
Regarding claim 5, Kanno teaches wherein the storage controller is further configured to: perform a first input/output operation for the nonvolatile memory device based on a first address mapping entry for a first logical address, which is cached in the first dedicated caching area or the shared caching area, based on a first input/output request being provided from the first host and comprising the first logical address (Fig.5: Information processing device D1) ([0108]-[0112]: the read unit 21 reads the read data 9R from the position indicated by PBA corresponding to the namespace NS.sub.M indicated by NSID 6R via the buffer memory F.sub.M corresponding to the namespace NS.sub.M indicated by NSID 6R, and sends the read data 9R to the information processing devices D.sub.M issuing the read command C3 via the interface unit 19. In the present embodiment described above, the nonvolatile memory 5 is divided into a plurality of the namespaces NS.sub.0 to NS.sub.M. The information processing devices D.sub.0 to D.sub.M can access the namespaces whose access rights are granted thereto).
Regarding claim 6, Kanno teaches wherein the storage controller is further configured to: read a first address mapping table comprising the first address mapping entry from the nonvolatile memory device, and store the first address mapping table in the storage controller, based on the first address mapping entry not being in the first dedicated caching area and the shared caching area (Fig.5: Information processing device D1) ([0108]-[0112]: the read unit 21 reads the read data 9R from the position indicated by PBA corresponding to the namespace NS.sub.M indicated by NSID 6R via the buffer memory F.sub.M corresponding to the namespace NS.sub.M indicated by NSID 6R, and sends the read data 9R to the information processing devices D.sub.M issuing the read command C3 via the interface unit 19. In the present embodiment described above, the nonvolatile memory 5 is divided into a plurality of the namespaces NS.sub.0 to NS.sub.M. The information processing devices D.sub.0 to D.sub.M can access the namespaces whose access rights are granted thereto).
Regarding claim 9, Kanno teaches wherein a capacity of each of the plurality of address mapping tables is same as a capacity of a unit page of the nonvolatile memory device (Fig.5 and Fig.6).
Regarding claim 20, Kanno teaches wherein: the map data memory device comprises a first dedicated caching area corresponding to the first occupation guarantee ratio, and the first dedicated caching area is configured to exclusively cache the first plurality of address mapping tables among the first plurality of address mapping tables and the second plurality of address mapping tables (Fig.5 & Fig.6 and [0108]-[0112]: Translation table 20) (Fig.5 and Fig.6: As shown in Fig.6 entries corresponding to namespace NS0 (e.g., LBA200->PBA300, LBA201->PBA301) are grouped together as a table associated with first namespace, while entries corresponding to another namespace (e.g., NS1, NS2 … NSm) are maintained separately. Thus, the controller of Kanno maintains separate mapping-table space for each namespace by grouping of entries per namespace shown in Fig.6. Kanno requires maintaining non-overlapping, namespace-specific portions of the translation table for NS0, NS1, NS2 …).
Claims 10-13, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kanno (US Pub. US 2022/0237114) in view of Muthiah et al. (Pub. No.: US 2023/0418490).
Regarding independent claim 10, Kanno teaches a storage controller (Fig.1: Controller 4) configured to control a nonvolatile memory device (Fig.1: Nonvolatile memory 5) comprising a first namespace (Fig.1: namespace NS0) and a second namespace (Fig.1: namespace NSm), ([0025]: a plurality of namespaces NS.sub.0 to NS.sub.M (M is an integer which is 1 or more) are each space which can be obtained from dividing a plurality of blocks B.sub.0 to B.sub.N (N is an integer which is M or more) included in the nonvolatile memory 5) the storage controller (Fig.1: Controller 4) comprising:
a map data memory device (Fig.1: Memory unit 10) comprising: a first dedicated caching area storing a first plurality of address mapping tables (Fig.1: Address translation table L0) for the first namespace (Fig.1: namespace NS0); and a second dedicated caching area storing a second plurality of address mapping tables (Fig.1: Address translation table Lm) for the second namespace (Fig.1: namespace NSm) ([0025]-[0038]: The memory unit 10 stores address translation tables T.sub.0 to T.sub.M corresponding to their respective namespaces NS.sub.0 to NS.sub.M and each of address translation tables T.sub.0 to T.sub.M is data associating LBA with PBA based on the data write with respect to namespaces NS.sub.0 to NS.sub.M, and may be LUT).
However, Kanno does not specifically teach a caching manager configured to manage a capacity of each of the first dedicated caching area and the second dedicated caching area.
Muthiah teaches a caching manager configured to manage a capacity of each of the first dedicated caching area and the second dedicated caching area ([0065]: The peer rate leveller 322 may use available capacity in striping logic 322.4 and/or to manage the total capacity of the storage array for host LBA mapping table 322.1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate managing capacity of namspaces, as taught by Muthiah into the memory system of Kanno in order to provide aggregate capacity to the host system (Muthiah - [0065]).
Regarding claim 11, Kanno teaches wherein: a first address mapping table among the first plurality of address mapping tables comprises a first plurality of address mapping entries that map physical addresses and logical addresses for a first plurality of pages in the first namespace; and a second address mapping table among the second plurality of address mapping tables comprises a second plurality of address mapping entries that map physical addresses and logical addresses for a second plurality of pages in the second namespace (Fig.5 & Fig.6 and [0108]-[0112]: Translation table 20) (Fig.5 and Fig.6: As shown in Fig.6 entries corresponding to namespace NS0 (e.g., LBA200->PBA300, LBA201->PBA301) are grouped together as a table associated with first namespace, while entries corresponding to another namespace (e.g., NS1, NS2 … NSm) are maintained separately. Thus, the controller of Kanno maintains separate mapping-table space for each namespace by grouping of entries per namespace shown in Fig.6. Kanno requires maintaining non-overlapping, namespace-specific portions of the translation table for NS0, NS1, NS2 …).
Regarding claim 12, Kanno teaches wherein the map data memory device further comprises: a shared caching area configured to store a third plurality of address mapping tables for the first namespace and a fourth plurality of address mapping tables for the second namespace (see Fig.5 and Fig.6).
Regarding claim 13, Kanno teaches wherein: a third address mapping table of the third plurality of address mapping tables comprises a third plurality of address mapping entries that map physical addresses and logical addresses for a third plurality of pages in the first namespace; and a fourth address mapping table among the fourth plurality of address mapping tables comprises a fourth plurality of address mapping entries that map physical addresses and logical addresses for a fourth plurality of pages in the second namespace (Fig.5 & Fig.6 and [0108]-[0112]: Translation table 20) (Fig.5 and Fig.6: As shown in Fig.6 entries corresponding to namespace NS0 (e.g., LBA200->PBA300, LBA201->PBA301) are grouped together as a table associated with first namespace, while entries corresponding to another namespace (e.g., NS1, NS2 … NSm) are maintained separately. Thus, the controller of Kanno maintains separate mapping-table space for each namespace by grouping of entries per namespace shown in Fig.6. Kanno requires maintaining non-overlapping, namespace-specific portions of the translation table for NS0, NS1, NS2 …).
Regarding claim 16, Kanno teaches wherein the caching manager is further configured to perform a first input/output operation on the nonvolatile memory device based on a first address mapping entry for a first logical address which is stored in the map data memory device, based on a first input/output request comprising the first logical address for the first namespace provided by an external device (Fig.5: Information processing device D1) ([0108]-[0112]: the read unit 21 reads the read data 9R from the position indicated by PBA corresponding to the namespace NS.sub.M indicated by NSID 6R via the buffer memory F.sub.M corresponding to the namespace NS.sub.M indicated by NSID 6R, and sends the read data 9R to the information processing devices D.sub.M issuing the read command C3 via the interface unit 19. In the present embodiment described above, the nonvolatile memory 5 is divided into a plurality of the namespaces NS.sub.0 to NS.sub.M. The information processing devices D.sub.0 to D.sub.M can access the namespaces whose access rights are granted thereto).
Regarding claim 17, Kanno teaches wherein the caching manager is further configured to: read a fifth address mapping table comprising the first address mapping entry from the nonvolatile memory device and store the fifth address mapping table in the map data memory device, based on the first address mapping entry not being in the first plurality of address mapping tables and the third plurality of address mapping tables (Fig.5: Information processing device D1) ([0108]-[0112]: the read unit 21 reads the read data 9R from the position indicated by PBA corresponding to the namespace NS.sub.M indicated by NSID 6R via the buffer memory F.sub.M corresponding to the namespace NS.sub.M indicated by NSID 6R, and sends the read data 9R to the information processing devices D.sub.M issuing the read command C3 via the interface unit 19. In the present embodiment described above, the nonvolatile memory 5 is divided into a plurality of the namespaces NS.sub.0 to NS.sub.M. The information processing devices D.sub.0 to D.sub.M can access the namespaces whose access rights are granted thereto).
Allowable Subject Matter
Claims 7, 8, 14, 15 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Claim 7 identifies the distinct features “wherein the storage controller is further configured to: store the first address mapping table in the first dedicated caching area based on the first dedicated caching area not being full; store the first address mapping table in the shared caching area, based on the first dedicated caching area being full and the shared caching area not being full; and store the first address mapping table in the first dedicated caching area after deleting a second address mapping table in the first dedicated caching area, based on the first dedicated caching area and the shared caching area being full", which are not taught or suggested by the prior art of records.
Claim 8, which respectively depends on objected-to claim 7, is allowable for at least the same reasons as claim 7.
Claim 14 identifies the distinct features “wherein the caching manager is further configured to convert a first conversion area, that is a portion of the shared caching area, to the first dedicated caching area, based on a first allocation ratio configuration request from an external device", which are not taught or suggested by the prior art of records.
Claim 15, which respectively depends on objected-to claim 14, is allowable for at least the same reasons as claim 14.
Claim 18 identifies the distinct features “wherein the caching manager is configured to: store the fifth address mapping table in the first dedicated caching area, based on the first dedicated caching area not being full; store the fifth address mapping table in the shared caching area, based on the first dedicated caching area being full and the shared caching area not being full; and store the fifth address mapping table in the first dedicated caching area after deleting a sixth address mapping table that is one of the first plurality of address mapping tables, based on the first dedicated caching area and the shared caching area being full", which are not taught or suggested by the prior art of records.
Claims 7, 8, 14, 15 and 18 would be allowable over the prior art of record because the claimed features as mentioned above in combination with other claimed features are not recited or suggested by the prior art of records.
Response to Arguments
Applicant’s arguments filed on 03/05/2026 have been fully considered but they are not persuasive.
1st Point of Argument (Claim 1)
Regarding Applicant’s remarks on page 12, the applicants argue that Kanno does not teach or suggest the claimed "a first dedicated caching area partitioned to cache address mapping tables having a first table type corresponding to the first namespace among the plurality of address mapping tables.
In response, Knno discloses that translation table entries corresponding to a namespace (e.g., NS0) are grouped together and maintained separately from entries corresponding to other namespaces (see Fig.6 and [0108]-[0112]). Under BRI, “partitioned to cache” does not require a physically separate hardware structure. Logical separation and maintenance of namespace-specific mapping-table portions reasonably constitute a partitioned caching area.
2nd Point of Argument (Claim 1)
Regarding Applicant’s remarks on page 12-13, the applicants argue that Schauer does not teach the claimed "wherein the storage controller comprises a first dedicated caching area partitioned to cache address mapping tables" because Schauer does not describe that the SLTs and GMTs stored in the "non-volatile storage array" are cached into a storage controller.
In response, Schauer teaches storing mapping tables in a nonvolatile storage array to retain mapping data in case of power failure ([0018]). Incorporating such nonvolatile storage of mapping tables into Konno’s namespace based architecture would have been an obvious design choice to improve reliability.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate storing mapping tables in a non-volatile storage array, as taught by Schauer into the memory system of Kanno.
Such a modification would have been a predictable design choice because storing the mapping tables within the nonvolatile memory allows the mapping data to be retained in the event of a power failure, thereby improving reliability by preventing data loss in case of a power failure of the memory system (Schauer - [0018]).
3rd Point of Argument (Claim 10)
Regarding Applicant’s remarks on pages 13-15, the applicants argue that Muthiah does not teach or suggest the claimed "a caching manager configured to manage a capacity of each of the first dedicated caching area and the second dedicated caching area.
In response, Muthiah teaches managing available capacity and total capacity for mapping tables ([0065]). Applying such capacity management to namespace-specific portion of mapping tables in Kanno would have been an obvious variation, particularly since Kanno already maintains namespace-specific, non-overlapping mapping table portions. Managing capacity for each namespace-specific hardware portion represents a predictable implementation of known capacity management techniques in multi-namespace system.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate managing capacity of namspaces, as taught by Muthiah into the memory system of Kanno in order to provide aggregate capacity to the host system (Muthiah - [0065]).
4th Point of Argument (Claim 19)
Regarding Applicant’s remarks on pages 15-17, the applicants argue that the cited references, either individually or in combination, do not teach or suggest at least "a caching manager configured to manage a first occupation guarantee ratio of the first plurality of address mapping tables for the map data memory device".
In response, Kanno teaches maintaining namespace-specific portions of the translation table and allocates mapping-table space on a namespace basis (Fig.6 and [0108]-[0112]), entries corresponding to namespace NS0 are grouped together and maintained separately from entries corresponding to other namespaces. Under the BRI, the claimed “occupation guarantee ratio” does not require a particular mathematical calculation, quota algorithm, or reservation mechanism.
5th Point of Argument (Claim 19)
Regarding Applicant’s remarks on pages 15-17, the applicants argue that that the cited references, either individually or in combination, do not teach or suggest "a storage controller comprising a map data memory device configured to cache at least one of the first plurality of address mapping tables or the second plurality of address mapping tables,".
In response, Kanno maintains namespace-specific translation-table portions associated with respective namespaces (Fig.6 and [0108]-[0112]). Under the BRI, the claim does not require a particular cache architecture or a physically distinct cache structure. The namespace-specific storage and maintenance of translation-table information in Kanno reasonably teaches the claimed caching of address mapping tables.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication should be directed to Yong Choe at telephone number 571-270-1053 or email to yong.choe@uspto.gov. The examiner can normally be reached on M-F 8:00am to 5:00pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rutz, Jared Ian can be reached on (571) 272-5535. Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 whose telephone number is (571) 272-2100.
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/YONG J CHOE/Primary Examiner, Art Unit 2135
Prosecution Insights