FINAL OFFICE ACTION
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 6-10, 12, 13, and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. No. 2020/0301495 to Masubuchi in view of U.S. Patent Pub. No. 2021/0167771 to Lee.
Masubuchi discloses:
1. A storage device comprising:
a memory device (para. [0023] and Fig. 1, SSD 20);
a power supply port configured to receive a first external power voltage from a host device (para. [0031] and Fig. 2, connector 44);
a power supply circuit (Fig. 2, power supply circuit 30) configured to:
receive the first external power voltage from the power supply port, and
generate a first internal power voltage based on the first external power voltage (paras. [0035]-[0037]);
a monitoring circuit (Fig. 2, PoR/UVP signal generator 62) configured to:
receive the first external power voltage from the power supply port, and
generate a first power-on-reset signal based on monitoring the first external power voltage (para. [0039]); and
a storage controller (Fig. 2, controller 22) configured to control the memory device,
wherein the storage controller is driven based on the first internal power voltage and the first power-on-reset signal (paras. [0037], [0040]).
Masubuchi does not disclose expressly:
wherein the monitoring circuit is further configured to:
detect a voltage distortion or an abnormal change in the first power-on-reset signal during transmission from the monitoring circuit to the storage controller, and
provide an error detection signal to the storage controller in response to detecting the voltage distortion of the abnormal change.
Lee teaches:
wherein the monitoring circuit is further configured to:
detect a voltage distortion or an abnormal change in the first power-on-reset signal during transmission from the monitoring circuit to the storage controller (paras. [0027], [0040] and Figs. 3, 10), and
provide an error detection signal to the storage controller in response to detecting the voltage distortion of the abnormal change (para. [0040]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Masubuchi by detecting a voltage distortion or abnormal change of the POR signal, as taught by Lee. A person of ordinary skill in the art would have been motivated to do so in order to avoid a malfunction in the power-on-reset signal due to a noisy power supply voltage, as discussed by Lee (para. [0005]). In this manner, it would have been obvious to combine Masubuchi with Lee to achieve the invention as recited in claim 1.
Modified Masubuchi discloses:
6. The storage device of claim 1, wherein the monitoring circuit is further configured to:
provide the error detection signal with a seventh logical value to the storage controller, based on determining that the voltage distortion or the abnormal change in the first power-on-reset signal has occurred (Masubuchi - paras. [0041], [0049]); and
provide the error detection signal with an eighth logical value different from the seventh logical value to the storage controller, based on determining that the voltage distortion or the abnormal change in the first power-on-reset signal has not occurred (Masubuchi - para. [0050] and Fig. 3).
7. The storage device of claim 1, wherein the voltage distortion or the abnormal change in the first power-on-reset signal is caused by at least one of an interference by an adjacent electrical element, a high temperature, and a physical impact on a transmission line through which the first power-on-reset signal is transmitted from the monitoring circuit to the storage controller (Masubuchi - para. [0042]).
8. The storage device of claim 1, wherein, after the storage controller is powered off by the voltage distortion or the abnormal change in the first power-on-reset signal, the power supply port receives a second external power voltage from the host device (Masubuchi - para. [0047]),
wherein the power supply circuit generates a second internal power voltage based on the second external power voltage (Masubuchi - paras. [0035]-[0037]),
wherein the monitoring circuit is further configured to generate a second power-on-reset signal based on monitoring the second external power voltage (Masubuchi - para. [0039]), and wherein the storage controller is further configured to:
be driven again based on the second internal power voltage and the second power-on-reset signal (Masubuchi - paras. [0037], [0040]), and
receive the error detection signal from the monitoring circuit, after driven again (Masubuchi - paras. [0041], [0049]).
9. The storage device of claim 1, wherein the storage controller is further configured to:
based on the storage controller being powered off by the voltage distortion or the abnormal change in the first power-on-reset signal and then being driven again, receive the error detection signal from the monitoring circuit (Masubuchi - paras. [0041], [0048]); and
log error detection information indicating the voltage distortion or the abnormal change in the first power-on-reset signal, based on the error detection signal (Masubuchi - paras. [0049], [0050]).
10. The storage device of claim 9, further comprising:
a first communication port configured to communicate by using an in-band channel, wherein the storage controller is further configured to provide the error detection information to the host device through the first communication port (Masubuchi - paras. [0031], [0079]).
Claims 12, 13, 16, 17, 18, and 19 are a method corresponding to the steps performed by the storage device of claims 1, 6, 9, 8, and 7, and are rejected under the same rationale.
Claims 11 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Masubuchi and Lee and further in view of U.S. Patent Pub. No. 2018/0260342 to Thangaraj et al.
Masubuchi does not disclose expressly:
11. The storage device of claim 9, further comprising:
a second communication port configured to communicate by using an out-of-band channel; and
a micro controller unit (MCU) configured to receive the error detection information from the storage controller and to provide the error detection information to the host device through the second communication port.
Thangaraj teaches:
a second communication port configured to communicate by using an out-of-band channel (para. [0026]); and
a micro controller unit (MCU) configured to receive the error detection information from the storage controller and to provide the error detection information to the host device through the second communication port (paras. [0031], [0039]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Masubuchi by using an out-of-band channel and micro controller unit to receive and provide the error detection information as taught by Thangaraj. A person of ordinary skill in the art would have been motivated to do so in order to have the ability to transmit information externally from the storage device even when the main processor has failed, as discussed by Thangaraj (para. [0031]). In this manner, it would have been obvious to combine Masubuchi with Thangaraj to achieve the invention as recited in claim 11.
Claim 20 is a storage device identical to the storage device of claim 1, with the additional limitation of a MCU for performing steps as recited in claim 11, and is rejected under the same rationale.
Allowable Subject Matter
Claims 2-5, 14, and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PHILIP GUYTON/ Primary Examiner, Art Unit 2113