DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/13/2026 has been entered.
Response to Amendment
1. Amendment filed on 02/13/2026 has been entered. Claims 1 and 14 have been amended and claim 15 has been canceled.
Response to Arguments
2. Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. Claim(s) 1-4, 8, and 19-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al (US 2021/0398488).
As to claim 1, Park teaches a display device, comprising:
a display panel including a plurality of pixels (Fig. 1, [0060]); and
a data driver circuit ([0081] The display driving circuit DDC may include …a data driving circuit) configured to supply a data signal to the plurality of the pixels through data lines ([0085] transmits a data voltage Dm input through the data line DL);
wherein a gate driver circuit (gate driving circuit unit GDC, fig. 2), configured to supply a gate signal to the plurality of the pixels through gate lines ([0085] a scan signal Sn received through the scan line SL, [0074] the plurality of gate lines GL are connected to the gate driving circuit unit GDC), is disposed in the display panel (see GDC1 in figs. 5 and 7),
wherein the display panel includes:
a driving layer including a gate area having the gate driver circuit (an area in fig. 7 where gate driving circuit units GDC1 is located); and
a pixel circuit layer including an active area having a pixel area in which each of the plurality of pixels is disposed (an area in figure 7 where a first display element DE1 and a second display element DE2 are located) and a non-active area around the active area (an area in figure 2, where a pad unit PU is located), and
wherein the pixel circuit layer includes a light emitting diode (an area in figure 7 where a first display element DE1 and a second display element DE2 are located), a clock line configured to supply a clock signal to the gate driver circuit ( clock line CWL, fig. 7, [0076] The plurality of gate driving circuit units GDC sequentially transmit a first gate signal to the plurality of gate lines GL based on the first clock signal received from the first clock pad CLP1), a shielding conductive pattern ( a first electrode layer E1, fig. 7) between the light emitting diode (DE1, fig. 6) and the clock line (clock line CWL, fig. 7), a first planarization layer (first insulating layer IL1, fig. 7), a conductive layer on the first planarization layer (fig. 7 illustrates a conductive layer on top of the first insulating layer IL1, as illustrated in fig. 7, the conductive layer is connected to the source and drain of the transistor TFT), a second planarization layer on the conductive layer (second insulating layer IL2, fig. 7) and the shielding conductive pattern (a first electrode layer E1, fig. 7) on the second planarization layer (second insulating layer IL2, fig. 7), and
wherein a width of the shielding conductive pattern is larger than a width of an anode electrode of the light emitting diode (fig. 7 illustrates that the width of the first electrode layer E1 is larger than the width of opposite electrode OE).
As to claim 2, Park teaches the display device, wherein the pixel area includes a first pixel area in which a first pixel among the plurality of pixels is disposed (the first pixel in the first row of the bottom first pixel circuit unit PC1 in the first area AR1 of figure 10), a second pixel area in which a second pixel is disposed (the third pixel in the first row of the bottom first pixel circuit unit PC1 in the first area AR1 of figure 10), a third pixel area in which a third pixel is disposed (the first pixel in the first row of the top first pixel circuit unit PC1 in the first area AR1 of figure 10), a fourth pixel area in which a fourth pixel is included (the third pixel in the first row of the top first pixel circuit unit PC1 in the first area AR1 of figure 10), and a center area which overlaps the gate area (a second gate driving circuit unit GDC2 in the first area AR1, fig. 10).
As to claim 3, Park teaches the display device, wherein the second pixel area (the third pixel in the first row of the bottom first pixel circuit unit PC1 in the first area AR1 of figure 10) is adjacent to the first pixel area (the first pixel in the first row of the bottom first pixel circuit unit PC1 in the first area AR1 of figure 10) along a first direction (horizontal, fig. 10), the third pixel area (the first pixel in the first row of the top first pixel circuit unit PC1 in the first area AR1 of figure 10) is spaced apart from the first pixel area (the first pixel in the first row of the bottom first pixel circuit unit PC1 in the first area AR1 of figure 10) with a predetermined interval along a second direction (vertical direction, fig. 10) which is different from the first direction (that is horizontal direction), and the fourth pixel area (the third pixel in the first row of the top first pixel circuit unit PC1 in the first area AR1 of figure 10) is adjacent to the third pixel area along the first direction (horizontal direction, fig. 10) and is spaced apart from the second pixel area (the third pixel in the first row of the bottom first pixel circuit unit PC1 in the first area AR1 of figure 10) with the predetermined interval along the second direction (that is in the vertical direction, fig. 10).
As to claim 4, Park teaches the display device, wherein the center area is at an area between the first pixel area (the first pixel in the first row of the bottom first pixel circuit unit PC1 in the first area AR1 of figure 10) and the third pixel area (the first pixel in the first row of the top first pixel circuit unit PC1 in the first area AR1 of figure 10) and an area between the second pixel area (the third pixel in the first row of the bottom first pixel circuit unit PC1 in the first area AR1 of figure 10) and the fourth pixel area (the third pixel in the first row of the top first pixel circuit unit PC1 in the first area AR1 of figure 10).
As to claim 8, Park teaches the display device, wherein the first pixel (the first pixel in the first row of the bottom first pixel circuit unit PC1 in the first area AR1 of figure 10) and the second pixel (the third pixel in the first row of the bottom first pixel circuit unit PC1 in the first area AR1 of figure 10) are symmetric to each other with respect to the second direction (vertical direction, fig. 10), the third pixel (the first pixel in the first row of the top first pixel circuit unit PC1 in the first area AR1 of figure 10) and the fourth pixel (the third pixel in the first row of the top first pixel circuit unit PC1 in the first area AR1 of figure 10) are symmetric to each other with respect to the second direction (vertical direction, fig. 10), the first pixel and the third pixel are symmetric to each other with respect to the first direction (horizontal, fig. 10), and the second pixel and the fourth pixel are symmetric to each other with respect to the first direction (horizontal, fig. 10).
As to claim 19, Park teaches the display device, wherein the driving layer (an area in fig. 7 where gate driving circuit units GDC1 is located) and the pixel circuit layer (an area in figure 7 where a first display element DE1, a second display element DE2 and TFT of PC1 are located) are disposed on the same layer (see fig. 7).
As to claim 20, Park teaches the display device, wherein the display panel includes a plurality of first type transistors (TFT of PC1 for the plurality of pixels, fig. 7) and a plurality of second type transistors (TFT of GDC1 for the plurality of pixels, fig. 7), and wherein at least some of the plurality of first type transistors are included in the pixel circuit layer (TFT for DE1, fig. 7) and remaining ones of the plurality of first type transistors are included in the driving layer (TFT of GDC1, fig.
7).
As to claim 21, Park teaches the display device, wherein a width of the shielding conductive pattern is larger than a width of an anode electrode of the light emitting diode (fig. 7 illustrates that the width of the first electrode layer E1 is larger than the width of opposite electrode OE).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (US 2021/0398488) in view of Kim et al (US 2023/0162664).
As to claim 5, Park does not teach the display device as claimed.
However, Kim teaches the display device, wherein at least one pixel among the plurality of pixels is connected to each of first to fourth scan lines (S1i-S4i, fig. 3), an emission control line (Ei, fig. 3), a data line (Dj, fig. 3), and first to fifth power voltage lines (VDD, VSS, Vint1, Vint2, and Vbs, fig. 3), wherein the first to fourth scan lines (S1i, S2i, S3i and S4i, figs. 8 and 11), the emission control line (Ei, fig. 8), and third to fifth power voltage lines (Vint1, Vbs, and Vint2, figs. 8 and 12) extend along the first direction (horizontal direction) to be spaced apart from each other (Figs. 8, 11, and 12), and wherein the data line (Dj, fig. 8) and the first power voltage line (VDD, fig. 8) extend along the second direction (vertical direction).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Park to teach the disclosure as suggested by Kim. The motivation would have been in order to provide “a display device capable of increasing image quality with respect to various frame frequencies by controlling a bias state of a driving transistor of a pixel” ([0005]).
5. Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (US 2021/0398488) in view of Kim et al (US 2023/0162664) and further in view of Cho et al (US 2024/0122007).
As to claim 6, Park in view of Kim does not teach the display device as claimed.
However, Cho teaches the display device, wherein, on the first pixel area (PXA1, figs. 6 and 8) and the second pixel area (PXA2, figs. 6 and 8), the third power voltage line (VIL, figs. 6 and 8), the fourth scan line (GIL, figs. 6 and 8), the second scan line (GWL, figs. 6 and 8), the first scan line (GCL, figs. 6 and 8), the emission control line (EL, figs. 6 and 8), and the third scan line (GBL, figs. 6 and 8) are sequentially disposed to be spaced apart from each other along the second direction (see figs. 6 and 8), and wherein, on the third pixel area and the fourth pixel area, the third scan line, the emission control line, the first scan line, the second scan line, the fourth scan line, and the third power voltage line are sequentially disposed to be spaced apart from each other along the second direction (PXA1 and PXA 2 in fig. 6 illustrates the pixel structure of all pixels in the display including the third pixel area and the fourth pixel area).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Park and Kim to teach the disclosure as suggested by Cho. The motivation would have been in order to reduce the size of a driver and improve the quality of the images ([0007]-[0008]).
6. Claim(s) 9-10 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (US 2021/0398488) in view of Cho et al (US 2023/0397462).
As to claim 9, Park does not teach the display device as claimed.
However, Cho teaches the display device, wherein the pixel circuit layer includes: a display element layer having at least one first type transistor (DT, fig. 11, [0157] driving transistor DT, the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 of one sub-pixel SPX may be formed of a p-type), at least one second type transistor ([0157] third transistor ST3 and the fourth transistor ST4 may be formed of an N-type ), and at least one capacitor (C1, fig. 5); and a light emitting diode layer having the light emitting diode (ED, fig. 11).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Park to teach the disclosure as suggested by Cho. The motivation would have been in order to improve a reduction in display quality caused by insufficient space of the fan-out lines ([0005]).
As to claim 10, Park in view of Cho teaches the display device, wherein the first type transistor includes a polysilicon semiconductor layer (Cho: [0157] An active layer of each of the driving transistor DT, the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6 and the seventh transistor ST7 configured as the P-type or kind MOSFETs may be formed of polysilicon), and the second type transistor includes an oxide semiconductor layer (Cho: [0157] an active layer of each of the third transistor ST3 and the fourth transistor ST4 configured as the N-type or kind MOSFETs may be formed of an oxide semiconductor).
As to claim 17, Park does not teach the display device as claimed.
However, Cho teaches the display device, wherein each of the plurality of pixels includes: a light emitting diode (ED, fig. 5); a driving transistor, connected between a first node (on VDD side, fig. 5) and a second node (DT, fig. 5), configured to generate a driving current ([0151]) flowing from a first power line to supply a first power voltage (VDD, fig. 5) to a second power line (VSS, fig. 5) to supply a second power voltage through the light emitting diode ([0152]); a first transistor (ST3, fig. 5) connected between the second node and a third node corresponding to a gate electrode of the driving transistor (the gate of DT, fig. 5), the first transistor being configured to turn on in response to a first scan signal supplied to a first scan line (GCL, fig. 5); a second transistor (ST2, fig. 5) connected between a data line (DL, fig. 5) and the first node, the second transistor being configured to turned on in response to a second scan signal supplied to a second scan line (GWL, fig. 5); a third transistor (ST5, fig. 5) connected between the first power line (VDD) and the first node, the third transistor being configured to turn off in response to an emission control signal supplied to an emission control line (EML, fig. 5); a fourth transistor (ST6, fig. 5) connected between the second node (a node where ST3 connects with DT) and a fourth node corresponding to a first electrode of the light emitting diode (a node where ST7 connects with ED), the fourth transistor being configured to turn off in response to the emission control signal (EML, fig. 5); and a fifth transistor (ST4, fig. 5) connected between the third node (a node that connects the gate of DT) and a third power line configured to supply a third power voltage (VGIL, fig. 5), the fifth transistor being configured to turn on in response to a fourth scan signal supplied to a fourth scan line (GIL, fig. 5); a sixth transistor (ST7, fig. 5) connected between the fourth node and a fourth power line configured to supply a fourth power voltage (VAIL, fig. 5), the sixth transistor being configured to turn on in response to a third scan signal supplied to a third scan line (GBL, fig. 5); a seventh transistor (ST1, fig. 5) connected between the first node and a fifth power line configured to supply a fifth power voltage (VOB, fig. 5), the seventh transistor being configured to turn on in response to the third scan signal (GBL, fig. 5); and a storage capacitor (C1, fig. 5) connected between the first power line (VDD, fig. 5) and the third node (a node that connects the gate of DT).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Park to teach the disclosure as suggested by Cho. The motivation would have been in order to improve a reduction in display quality caused by insufficient space of the fan-out lines ([0005]).
As to claim 18, Park in view of Cho teaches the display device, wherein the driving transistor (Cho: DT, fig. 5), the second transistor (Cho: ST2, fig. 5), the third transistor (Cho: ST5, fig. 5), and the fourth transistor (Cho: ST6, fig. 5) include a polysilicon semiconductor layer ([0157] An active layer of each of the driving transistor DT, … the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6 … configured as the P-type or kind MOSFETs may be formed of polysilicon) and the first transistor (Cho: ST3, fig. 5), the fifth transistor (Cho: ST4, fig. 5), the sixth transistor (Cho: ST7, fig. 5), and the seventh transistor (Cho: ST1, fig. 5) include an oxide semiconductor layer ([0157] an active layer of each of the third transistor ST3 and the fourth transistor ST4 configured as the N-type or kind MOSFETs may be formed of an oxide semiconductor… the seventh transistor ST7 may be formed of an N-type or kind MOSFET. In this case, the active layer of the seventh transistor ST7 may also be formed of an oxide semiconductor).
7. Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (US 2021/0398488) in view of Cho et al (US 2023/0397462) and further in view of Bae (US 2024/0099082).
As to claim 11, Park in view of Cho does not teach the display device as claimed.
However, Bae teaches the display device, wherein the display element layer includes: a first buffer layer (first buffer layer 110, fig. 10); a first semiconductor layer on the first buffer layer and including a first semiconductor pattern of the first type transistor (second semiconductor layer Act2 of T2, fig. 10); a first gate insulating layer on the first semiconductor layer ( first gate insulating layer 111, fig. 10); a first conductive layer on the first gate insulating layer and including a first gate electrode of the first type transistor (second gate electrode GE2, fig. 10); a first insulating layer on the first conductive layer (second gate insulating layer 113, fig. 10); a second conductive layer on the first insulating layer (first connection pattern CM1, fig. 10); a second insulating layer on the second conductive layer (second planarization layer 116, fig. 10); a third conductive layer on the second insulating layer, and including a first source electrode (first conductive line CLa, fig. 10) and a first drain electrode of the first type transistor ( third conductive line CLc, fig. 10); and a third insulating layer on the third conductive layer (first planarization layer 117, fig. 10).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Park and Cho to teach the disclosure as suggested by Bae. The motivation would have been in order to improve “the yield of a display apparatus by solving a defect in a pixel circuit.” ([0002]).
As to claim 12, Park in view of Cho and further in view of Bae teaches the display device, wherein the display element layer further includes: a second buffer layer on the third insulating layer (Bae: second buffer layer 210, fig. 10); a second semiconductor layer on the second buffer layer and including a second semiconductor pattern of the second type transistor (Bae: fig. 10 illustrates a semiconductor layer above the second buffer layer 210 ); a second gate insulating layer on the second semiconductor layer (Bae: third gate insulating layer 211, fig. 10); a fourth conductive layer on the second gate insulating layer and including a second gate electrode of the second type transistor (Bae: fig. 10 illustrates a gate electrode disposed above the third gate insulating layer 211); a fourth insulating layer on the fourth conductive layer (Bae: fourth gate insulating layer 213, fig. 10); and a fifth conductive layer on the fourth insulating layer, and including a second source electrode (Bae: the second bridge electrode BE2, fig. 10) and a second drain electrode of the second type transistor (Bae: an electrode connecting the first transistor with the second transistor above fourth gate insulating layer 213).
8. Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (US 2021/0398488) in view of Na et al (US 2022/0310013).
As to claim 16, Park does not teach the display device as claimed.
However, Na teaches the display device, wherein each of the plurality of pixels includes a driving transistor, a second transistor, a third transistor, and a fourth transistor each including a polysilicon semiconductor layer and a first transistor, a fifth transistor, a sixth transistor, and a seventh transistor each including an oxide semiconductor layer, and each of the plurality of transistors included in the gate driver circuit includes the polysilicon semiconductor layer (paragraph [0157] describes that “each of the first to eighth transistors ST1 to ST8 may be formed of any of polysilicon, amorphous silicon, and an oxide semiconductor”.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Park to teach the disclosure as suggested by Na. The motivation would have been in order to provide “a display device capable of preventing a voltage of a gate electrode of a driving transistor from fluctuating.” ([0005]).
Allowable Subject Matter
9. Claims 7, 13 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMEN W BOGALE whose telephone number is (571)270-1579. The examiner can normally be reached M-F 10:AM-6:PM.
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/AMEN W BOGALE/Examiner, Art Unit 2628
/NITIN PATEL/Supervisory Patent Examiner, Art Unit 2628