Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the response to this Office action, the Office respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Office in prosecuting this application.
The Office has cited particular figures, elements, paragraphs and/or columns and line numbers in the references as applied to the claims for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider each of the cited references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage disclosed by the Office.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on September 29, 2026 has been entered.
Status of Claims
- Applicant’s Amendment filed [date] is acknowledged.
- Claim(s) # is/are amended
- Claim(s) [#] is/are canceled
- Claim(s) [#} is/are withdrawn as non-elected
- Claim(s) [#] is/are pending in the application.
- Claim(s) [#] is/are examined on the merits
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Application Notes
The term “stage” has been used throughout the disclosure in a vague manner. It appears that at least one interpretation of “stage” corresponds to a time period of an image frame of the display area including all data refresh regions (see Applicant’s published application U.S. Patent Publication No. 20240412692 paragraphs 0024, 0037, 0050).
Examiner also notes that paragraph 0012 indicates “ It is to be noted that, in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not require or imply any actual relationship or sequence between these entities or operations. “.
Specification
Examiner respectfully withdraws the objection to the specification. Applicant’s amendment to reincorporate paragraph 0012 which was previously deleted has rendered the objection moot.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
Preset
Figure 2, element 10 and paragraphs 0030-0046 of Applicant’s published application U.S. Patent Publication No. 202401412692
It does not appear that any specific structure has been disclosed corresponding to a “preset module”
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 2-7 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. As illustrated above, Applicant’s original specification does not appear to have disclosed any specific corresponding structure for “preset
In order to further prosecution, Examiner had construed “drive For claim 2 and claims 4-7, the original disclosure supports the broader controlled circuit and driver relationships without requiring every circuit to be limited to a single transistor.”. Since Applicant’s original specification merely illustrates labeled boxes in the figures and generally teaches “circuit” without any specific example or description of a broader multi-component “circuit”., Examiner must maintain that the original specification fails to provide sufficient written description of the claimed features because Applicant maintains that the claims should not be limited to a single transistor circuit as now recited in claim 3. Further emphasizing that none of the original disclosure specifically identifies specific structure components. Leaving one unable to discern specifically what single/multi-component “circuit” has been contemplated by Applicant.
Dependent claims inherit the deficiencies of the respective parent.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The metes and bounds for which protection is sought are not clear. Claim 2 recites “the pixel circuit comprises a preset circuit in a data signal input path, a control terminal of the preset circuit is configured to receive a preset control signal, and when the preset control signal controls the preset circuit to be turned on, a data refresh is performed on the pixel circuit; and the driver circuit comprises a preset driver circuit, and the preset driver circuit is configured to provide the preset control signal to the control terminal of the preset circuit”. However, it is not clear whether “the preset the preset circuit is one of the data write transistor, the reset transistor, or the compensation transistor”.
Applicant’s published application U.S. Patent Publication No. 20240412692, paragraph 0035 indicates “According to the embodiments of the present application, the data signal input path is as follows in the working process of the pixel circuit: a data signal Vdata is input into the drive module 100 via the data write module 200, and then reaches the reset module 300 via the compensation module 400, to complete the display of regions with different data refresh frequencies in the display panel”
However, it is not clear how “a preset circuit in a data signal input path “ can correspond to any other transistor than a data write transistor since this is the only transistor (circuit) that is in the data input path. Applicant’s figure 3 does not illustrate what structure corresponds to each circuit nor how such structure is connected. However based on Applicant’s published application paragraph 0035 “Referring to FIG. 3, the pixel circuit includes a drive module 100, a data write module 200, a reset module 300, and a compensation module 400. The data write module 200 is connected to a first terminal of the drive module 100 to provide a data signal to the drive module 100. The reset module 300 is connected to a control terminal of the drive module 100 to provide a reset signal to the drive module 100. The compensation module 400 is connected between a second terminal of the drive module 100 and the control terminal of the drive module 100. “ It is unclear how a control terminal of a drive transistor (circuit) would receive the input Vdata so as to facilitate a “reset circuit” or “compensation circuit” to be in the “data signal input path”.
Dependent claims inherit the deficiencies of the respective parent.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-7, 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maruyama et al, U.S. Patent Publication No. 20110032231.
Consider claim 1, Maruyama teaches a display panel (see Maruyama figure 6, element 510 display panel), comprising:
a first data refresh region (see Maruyama paragraphs 0064-0066 where for example in the course of shift from the first display mode that operates at the first frame frequency to the second display mode that operates at the second frame frequency, the display device according to the first embodiment changes a frame frequency from the first frame frequency to the second frame frequency for each preset region within the display screen of the display panel 510 so that the frame frequencies of all the regions within the display screen (whole display screen) may eventually be changed to the second frame frequency.), wherein a data refresh frequency of the first data refresh region is F1 (see Maruyama paragraphs 0015, 0043 specifically for example paragraph 0043 where a display mode that operates at the first frame frequency (for example, 60 Hz) is referred to as a first display mode, a display mode that operates at the second frame frequency (for example, 120 Hz) is referred to as a second display mode, and a display mode in which one screen is constituted by mixing a first display area driven at the first frame frequency and a second display area driven at the second frame frequency is referred to as a third display mode.);
wherein a working process of the display panel comprises a first stage and a second stage (see Maruyama paragraphs 0043, 0064-0066 where for example a first stage may correspond to a whole screen operating at a first display mode and a second stage may correspond to a portion of a screen operating at a first display mode and another portion operating at a second display mode);
in the first stage, a width of the first data refresh region in a first direction is W1 (see Maruyama paragraphs 0043, 0064-0066 where for example a first stage may correspond to a whole screen operating at a first display mode and a second stage may correspond to a portion of a screen operating at a first display mode and another portion operating at a second display mode);
in the second stage, the width of the first data refresh region in the first direction is W2 (see Maruyama figures 4-5, element 401 and paragraphs 0043, 0064-0066 where for example a first stage may correspond to a whole screen operating at a first display mode and a second stage may correspond to a portion of a screen operating at a first display mode and another portion operating at a second display mode);
and W1 > W2 (see Maruyama paragraphs 0043, 0064-0066 where a whole screen operating in a first display mode corresponds to W1 and a portion of the screen operating in a first display mode corresponds to W2); and
wherein at least in the second stage (see Maruyama paragraphs 0043, 0064-0066 where for example a first stage may correspond to a whole screen operating at a first display mode and a second stage may correspond to a portion of a screen operating at a first display mode and another portion operating at a second display mode),
the display panel further comprises a second data refresh region (see Maruyama figure 4-5, element 402),
a data refresh frequency of the second data refresh region is F2, the first data refresh region and the second data refresh region are arranged in the first direction, and F1 ≠ F2 (see Maruyama paragraphs 0015, 0043 specifically for example paragraph 0043 where a display mode that operates at the first frame frequency (for example, 60 Hz) is referred to as a first display mode, a display mode that operates at the second frame frequency (for example, 120 Hz) is referred to as a second display mode, and a display mode in which one screen is constituted by mixing a first display area driven at the first frame frequency and a second display area driven at the second frame frequency is referred to as a third display mode.),
wherein the working process of the display panel further comprises a third stage, in the third stage, a width of the first data refresh region in the first direction is W3, and W3 < W2 (see Maruyama figures 4-5 and paragraphs 0063-0067 specifically for example paragraph 0065 where in the course of the shift where the first display mode is switched to the second display mode, the third display mode is provided as illustrated in FIG. 4, in which the display screen is constituted by first display areas 401 driven in the first display mode and a second display area 402 driven in the second display mode. Further, in the third display mode, the size of the second display area 402 is gradually increased with time in the screen vertical direction, for example, starting from zero in a central area (zero area) in the screen vertical direction, so that the second display area 402 may constitute the whole screen eventually. In contrast, in the case where the second display mode is switched to the first display mode, in the third display mode, the size of the first display area 401 is gradually increased with time, starting from zero, so that the first display area 401 may constitute the whole screen eventually.)
wherein W1 - W2 > W2 - W3, or W1 - W2 < W2 - W3 (see Maruyama figures 4-5 and paragraphs 0063-0067 specifically for example paragraph 0065 where in the course of the shift where the first display mode is switched to the second display mode, the third display mode is provided as illustrated in FIG. 4, in which the display screen is constituted by first display areas 401 driven in the first display mode and a second display area 402 driven in the second display mode. Further, in the third display mode, the size of the second display area 402 is gradually increased with time in the screen vertical direction, for example, starting from zero in a central area (zero area) in the screen vertical direction, so that the second display area 402 may constitute the whole screen eventually. In contrast, in the case where the second display mode is switched to the first display mode, in the third display mode, the size of the first display area 401 is gradually increased with time, starting from zero, so that the first display area 401 may constitute the whole screen eventually.);
wherein at least one of the following is satisfied: a duration of the first stage is longer than a duration of the second stage; or a duration of the third stage is longer than a duration of the second stage (see Maruyama figures 4-5 and paragraph 0039 and figures 4-5 and paragraphs 0063-0067 specifically for example paragraph 0065 where in the course of the shift where the first display mode is switched to the second display mode, the third display mode is provided as illustrated in FIG. 4, in which the display screen is constituted by first display areas 401 driven in the first display mode and a second display area 402 driven in the second display mode. Further, in the third display mode, the size of the second display area 402 is gradually increased with time in the screen vertical direction, for example, starting from zero in a central area (zero area) in the screen vertical direction, so that the second display area 402 may constitute the whole screen eventually. In contrast, in the case where the second display mode is switched to the first display mode, in the third display mode, the size of the first display area 401 is gradually increased with time, starting from zero, so that the first display area 401 may constitute the whole screen eventually and figures 12-17 and paragraphs 0097-0106, specifically for example paragraphs 0105-0106 where how the second display area is increased in the third display mode period between the times t1 and t2 is not limited to the above. For example, as illustrated in FIG. 14, the ratio of the second display area may be increased gradually in a ramp waveform pattern. Alternatively, as illustrated in FIG. 15, the second display area may be increased in a sawtooth pattern, that is, the ratio of the second display area may be varied to be increased eventually. How the second display area is increased in the third display mode period is appropriately set taking into account the calculation amount of the control parameters, the amount of holding parameters, and the suppression of image quality degradation. How the second display area is increased in the third display mode period is not limited to the above, and other increase patterns may be employed. Specifically when first display area is operating at 60 Hz and second display area is operating at 120 Hz as the stages transition there may be a point where the duration of display area 401 is equal a duration of 402 but most of the time the duration between the two would be different since 60 Hz updates at a different rate than 120 Hz).
Maruyama does not explicitly disclose W1 - W2 > W2 - W3, or W1 - W2 < W2 - W3. Further, Maruyama does not explicitly discuss length of time each display mode. One of ordinary skill would have been motivated to have W1 - W2 > W2 - W3, or W1 - W2 < W2 - W3 so as to transition between a starting display mode to an ending display mode using width options which gradually transition. Specifically as “the size of the second display area 402 is gradually increased with time in the screen vertical direction, for example, starting from zero in a central area (zero area) in the screen vertical direction, so that the second display area 402 may constitute the whole screen eventually. “ the widths of each stage would result in the recited configuration when a starting position of a second display is not in the center (see Maruyama paragraph 0066 where It should be noted that the second display area 402 is positioned in the vertical center of the screen in FIG. 4, but the position of the second display area 402 is not limited thereto. For example, as illustrated in FIG. 5, the second display area 402 may be formed from the upper side of the screen so that the first display area 401 on the lower side may be sequentially replaced with the second display area 402 downward. Alternatively, other dividing methods may be employed.)
Therefore, by merely following the teachings of the prior art the recited configuration of W1 - W2 > W2 - W3, or W1 - W2 < W2 - W3 would result. Further since such a configuration, absent any criticality (i.e., unobvious and/or unexpected result(s)), is generally achievable through routine optimization/experimentation, and since discovering the optimum or workable configuration, where the general conditions of a claim are disclosed in the prior art, involves only routine skill in the art. Moreover, in the absence of any criticality (i.e., unobvious and/or unexpected result(s)), the configuration set forth above would have been obvious to a person having ordinary skill in the art.
Maruyama does not explicitly discuss length of time for each display mode. However, one of ordinary skill would have found it an obvious matter of design depending on what type of images are to be displayed and how long each type of image is to be displayed that at least one configuration would correspond to having at least one of the following satisfied: a duration of the first stage is longer than a duration of the second stage; or a duration of the third stage is longer than a duration of the second stage. Specifically when first display area is operating at 60 Hz and second display area is operating at 120 Hz as the stages transition there may be a point where the duration of display area 401 is equal a duration of 402 but most of the time the duration between the two would be different since 60 Hz updates at a different rate than 120 Hz.
Consider claim 2, Maruyama teaches all the limitations of claim 1 and further teaches wherein: the display panel comprises a pixel circuit (see Maruyama figure 6, element 511 and paragraph 0053) and a driver circuit (see Maruyama figure 6, elements 530, 520, 540, 580, 590, 570, 560);
the pixel circuit comprises a preset circuit to be turned on, a data refresh is performed on the pixel circuit (see Maruyama paragraph 0053 where Each of the pixels 511 of the liquid crystal display panel 510 includes a thin film transistor (TFT), which is formed of a source electrode, a gate electrode, and a drain electrode, a pixel electrode connected to the source electrode of the TFT, and the TFT performs a switch operation when the gate electrode is applied with a scanning signal. While the TFT is in a closed state, a voltage of the data line connected to the drain electrode is written into the pixel electrode connected to the source electrode. Where TFT corresponds to preset module and scanning signal corresponds to preset control signal); and
the driver circuit comprises a preset driver circuit, and the preset driver circuit is configured to provide the preset control signal to the control terminal of the preset
Consider claim 4, Maruyama teaches all the limitations of claim 2 and further teaches wherein: the preset driver circuit comprises a first drive portion and a second drive portion (see Maruyama figure 6 and figure 4, reproduced below, where first drive portion corresponds to scanning line drive circuit portion which provides scan signals to scan lines corresponding to first display area and second drive portion corresponds to scanning line drive circuit portion which provides scan signals to scan lines corresponding to second display area);
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the preset control signal comprises a first preset control signal and a second preset control signal (see Maruyama paragraph 0052 where scanning line drive circuit 530 generates scanning line selection signals (gate signals) 531 based on the scanning line drive circuit control signal group 543, and outputs the scanning line selection signals 531 to scanning lines of the display panel 510. Where each scan line receives a scan signal corresponding to a control signal and a scan signal provided to a first display area scan line corresponds to a first preset control signal and a scan signal provided to a second display area scan line corresponds to a second preset control signal);
the first drive portion is configured to provide the first preset control signal to the first data refresh region; and the second drive portion is configured to provide the second preset control signal to the second data refresh region (see Maruyama figures 4 and 6, reproduced above, where first drive portion corresponds to scanning line drive circuit portion which provides scan signals to scan lines corresponding to first display area and second drive portion corresponds to scanning line drive circuit portion which provides scan signals to scan lines corresponding to second display area).
Consider claim 5, Maruyama teaches all the limitations of claim 4 and further teaches wherein: in the first stage, a width of the first drive portion in the first direction is W11 (see Maruyama paragraphs 0043, 0064-0066 where a first stage corresponds to a whole screen operating in a first display mode therefore W11 would be all scan lines supplied a scanning signal); and in the second stage, a width of the first drive portion in the first direction is W22 (see Maruyama paragraphs 0043, 0064-0066 where a second stage corresponds to a portion of the screen operating in a first display mode therefore W22 would be only scan lines supplied a scanning signal corresponding to a first display mode as illustrated in figures 6 and 4 reproduced above), and W11 > W22 (where a portion of the scan driving circuit providing signals to all scan lines for a whole screen corresponding to W11 is larger than a portion of the scan driving circuit providing signals to a portion of a screen corresponding to W22).
Consider claim 6, Maruyama teaches all the limitations of claim 4 and further teaches wherein: in at least part of a time period during which the display panel operates, the first preset control signal is different from the second preset control signal (see Maruyama paragraphs 0131-0144 and figure 17(a) and 17(c) specifically for example paragraph 0133 where as illustrated in FIG. 17(a), for example, input display data corresponding to even-numbered frames of the input display data to be input in a frame period (T period) corresponding to the frame frequency of 120 Hz is displayed as images in a period between times t0 and t6, which is a two-frame period (2T period), that is, in a frame cycle corresponding to the frame frequency of 60 Hz, by way of whole screen scanning from the upper portion toward the lower portion of the display panel as indicated by an arrow (vector) 1701. And paragraph 0136 where as illustrated in FIG. 17(c), the whole screen is scanned during the period between the times t0 and t1 indicated by the arrow 1701).
Maruyama does not explicitly discuss differences between scanning signals for an image frame where a whole screen is at a same frame frequency and an image frame where a portion of a screen is at a different frequency. However, one of ordinary skill in the art would readily recognize based on Maruyama’s disclosure that it is implicit that at least part of a time to display a whole screen at a same frame frequency will be different from an image frame where a portion of a screen is at a different frequency. Therefore, the recited features would have been obvious to one of ordinary skill.
Consider claim 7, Maruyama as modified by ordinary skill teaches all the limitations of claim 6 and further teaches wherein: F1 > F2, in the at least part of the time period during which the display panel operates, the first preset control signal controls the preset or F1 < F2, in the at least part of the time period during which the display panel operates, the first preset control signal controls the preset first frame frequency (for example, 60 Hz) is referred to as a first display mode, a display mode that operates at the second frame frequency (for example, 120 Hz) is referred to as a second display mode, and a display mode in which one screen is constituted by mixing a first display area driven at the first frame frequency and a second display area driven at the second frame frequency is referred to as a third display mode. And paragraphs 0066, 0097 where is applicable to a case where a display mode is switched from the second display mode (120 Hz) to the first display mode (60 Hz) as long as the transition is reversed).
Claims 8-12 canceled
Consider claim 13, Maruyama teaches all the limitations of claim 1 and further teaches wherein: the working process of the display panel comprises a transition stage (see Maruyama figure 8, display mode transition period and figure 15, third display mode and paragraph 0105 where third display mode period corresponds to transition period); and in the transition stage, at least two of the first stage, the second stage and the third stage are repeated units and are repeated at least once (see Maruyama figure 15, reproduced below, element repeated units and paragraph 0106 where second display area may be increased in a sawtooth pattern).
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Consider claim 14, Maruyama teaches a display device (see Maruyama paragraph 0038 where FIG. 6 is a diagram illustrating a schematic configuration of a display device), comprising a display panel (see Maruyama figure 6, element 510 display panel), wherein the display panel comprises:
a first data refresh region (see Maruyama paragraphs 0064-0066 where for example in the course of shift from the first display mode that operates at the first frame frequency to the second display mode that operates at the second frame frequency, the display device according to the first embodiment changes a frame frequency from the first frame frequency to the second frame frequency for each preset region within the display screen of the display panel 510 so that the frame frequencies of all the regions within the display screen (whole display screen) may eventually be changed to the second frame frequency.), wherein a data refresh frequency of the first data refresh region is F1 (see Maruyama paragraphs 0015, 0043 specifically for example paragraph 0043 where a display mode that operates at the first frame frequency (for example, 60 Hz) is referred to as a first display mode, a display mode that operates at the second frame frequency (for example, 120 Hz) is referred to as a second display mode, and a display mode in which one screen is constituted by mixing a first display area driven at the first frame frequency and a second display area driven at the second frame frequency is referred to as a third display mode.);
wherein a working process of the display panel comprises a first stage and a second stage (see Maruyama paragraphs 0043, 0064-0066 where for example a first stage may correspond to a whole screen operating at a first display mode and a second stage may correspond to a portion of a screen operating at a first display mode and another portion operating at a second display mode);
in the first stage, a width of the first data refresh region in a first direction is W1 (see Maruyama paragraphs 0043, 0064-0066 where for example a first stage may correspond to a whole screen operating at a first display mode and a second stage may correspond to a portion of a screen operating at a first display mode and another portion operating at a second display mode);
in the second stage, the width of the first data refresh region in the first direction is W2 (see Maruyama figures 4-5, element 401 and paragraphs 0043, 0064-0066 where for example a first stage may correspond to a whole screen operating at a first display mode and a second stage may correspond to a portion of a screen operating at a first display mode and another portion operating at a second display mode); and
W1 > W2 (see Maruyama paragraphs 0043, 0064-0066 where a whole screen operating in a first display mode corresponds to W1 and a portion of the screen operating in a first display mode corresponds to W2); and
wherein at least in the second stage (see Maruyama paragraphs 0043, 0064-0066 where for example a first stage may correspond to a whole screen operating at a first display mode and a second stage may correspond to a portion of a screen operating at a first display mode and another portion operating at a second display mode),
the display panel further comprises a second data refresh region (see Maruyama figure 4-5, element 402),
a data refresh frequency of the second data refresh region is F2, the first data refresh region and the second data refresh region are arranged in the first direction, and F1 ≠ F2 (see Maruyama paragraphs 0015, 0043 specifically for example paragraph 0043 where a display mode that operates at the first frame frequency (for example, 60 Hz) is referred to as a first display mode, a display mode that operates at the second frame frequency (for example, 120 Hz) is referred to as a second display mode, and a display mode in which one screen is constituted by mixing a first display area driven at the first frame frequency and a second display area driven at the second frame frequency is referred to as a third display mode.),
wherein: the working process of the display panel further comprises a third stage, in the third stage, a width of the first data refresh region in the first direction is W3, and W3 < W2 (see Maruyama figures 4-5 and paragraphs 0063-0067 specifically for example paragraph 0065 where in the course of the shift where the first display mode is switched to the second display mode, the third display mode is provided as illustrated in FIG. 4, in which the display screen is constituted by first display areas 401 driven in the first display mode and a second display area 402 driven in the second display mode. Further, in the third display mode, the size of the second display area 402 is gradually increased with time in the screen vertical direction, for example, starting from zero in a central area (zero area) in the screen vertical direction, so that the second display area 402 may constitute the whole screen eventually. In contrast, in the case where the second display mode is switched to the first display mode, in the third display mode, the size of the first display area 401 is gradually increased with time, starting from zero, so that the first display area 401 may constitute the whole screen eventually.)
wherein W1 - W2 > W2 - W3, or W1 - W2 < W2 - W3 (see Maruyama figures 4-5 and paragraphs 0063-0067 specifically for example paragraph 0065 where in the course of the shift where the first display mode is switched to the second display mode, the third display mode is provided as illustrated in FIG. 4, in which the display screen is constituted by first display areas 401 driven in the first display mode and a second display area 402 driven in the second display mode. Further, in the third display mode, the size of the second display area 402 is gradually increased with time in the screen vertical direction, for example, starting from zero in a central area (zero area) in the screen vertical direction, so that the second display area 402 may constitute the whole screen eventually. In contrast, in the case where the second display mode is switched to the first display mode, in the third display mode, the size of the first display area 401 is gradually increased with time, starting from zero, so that the first display area 401 may constitute the whole screen eventually.);
wherein at least one of the following is satisfied: a duration of the first stage is longer than a duration of the second stage; or a duration of the third stage is longer than a duration of the second stage (see Maruyama figures 4-5 and paragraph 0039 and figures 4-5 and paragraphs 0063-0067 specifically for example paragraph 0065 where in the course of the shift where the first display mode is switched to the second display mode, the third display mode is provided as illustrated in FIG. 4, in which the display screen is constituted by first display areas 401 driven in the first display mode and a second display area 402 driven in the second display mode. Further, in the third display mode, the size of the second display area 402 is gradually increased with time in the screen vertical direction, for example, starting from zero in a central area (zero area) in the screen vertical direction, so that the second display area 402 may constitute the whole screen eventually. In contrast, in the case where the second display mode is switched to the first display mode, in the third display mode, the size of the first display area 401 is gradually increased with time, starting from zero, so that the first display area 401 may constitute the whole screen eventually and figures 12-17 and paragraphs 0097-0106, specifically for example paragraphs 0105-0106 where how the second display area is increased in the third display mode period between the times t1 and t2 is not limited to the above. For example, as illustrated in FIG. 14, the ratio of the second display area may be increased gradually in a ramp waveform pattern. Alternatively, as illustrated in FIG. 15, the second display area may be increased in a sawtooth pattern, that is, the ratio of the second display area may be varied to be increased eventually. How the second display area is increased in the third display mode period is appropriately set taking into account the calculation amount of the control parameters, the amount of holding parameters, and the suppression of image quality degradation. How the second display area is increased in the third display mode period is not limited to the above, and other increase patterns may be employed. Specifically when first display area is operating at 60 Hz and second display area is operating at 120 Hz as the stages transition there may be a point where the duration of display area 401 is equal a duration of 402 but most of the time the duration between the two would be different since 60 Hz updates at a different rate than 120 Hz).
Maruyama does not explicitly disclose W1 - W2 > W2 - W3, or W1 - W2 < W2 - W3. Further, Maruyama does not explicitly discuss length of time each display mode. One of ordinary skill would have been motivated to have W1 - W2 > W2 - W3, or W1 - W2 < W2 - W3 so as to transition between a starting display mode to an ending display mode using width options which gradually transition. Specifically as “the size of the second display area 402 is gradually increased with time in the screen vertical direction, for example, starting from zero in a central area (zero area) in the screen vertical direction, so that the second display area 402 may constitute the whole screen eventually. “ the widths of each stage would result in the recited configuration when a starting position of a second display is not in the center (see Maruyama paragraph 0066 where It should be noted that the second display area 402 is positioned in the vertical center of the screen in FIG. 4, but the position of the second display area 402 is not limited thereto. For example, as illustrated in FIG. 5, the second display area 402 may be formed from the upper side of the screen so that the first display area 401 on the lower side may be sequentially replaced with the second display area 402 downward. Alternatively, other dividing methods may be employed.)
Therefore, by merely following the teachings of the prior art the recited configuration of W1 - W2 > W2 - W3, or W1 - W2 < W2 - W3 would result. Further since such a configuration, absent any criticality (i.e., unobvious and/or unexpected result(s)), is generally achievable through routine optimization/experimentation, and since discovering the optimum or workable configuration, where the general conditions of a claim are disclosed in the prior art, involves only routine skill in the art. Moreover, in the absence of any criticality (i.e., unobvious and/or unexpected result(s)), the configuration set forth above would have been obvious to a person having ordinary skill in the art.
Maruyama does not explicitly discuss length of time for each display mode. However, one of ordinary skill would have found it an obvious matter of design depending on what type of images are to be displayed and how long each type of image is to be displayed that at least one configuration would correspond to having at least one of the following satisfied: a duration of the first stage is longer than a duration of the second stage; or a duration of the third stage is longer than a duration of the second stage. Specifically when first display area is operating at 60 Hz and second display area is operating at 120 Hz as the stages transition there may be a point where the duration of display area 401 is equal a duration of 402 but most of the time the duration between the two would be different since 60 Hz updates at a different rate than 120 Hz.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maruyama et al, U.S. Patent Publication No. 20110032231 in view of Seo et al, U.S. Patent Publication No. 20210035489.
Consider claim 3, Maruyama teaches all the limitations of claim 2. Maruyama is silent regarding wherein the pixel circuit comprises a drive
Maruyama does disclose in paragraph 0038 that other display panels than liquid crystal display panels are applicable as long as a corresponding display device includes a scanning line drive circuit and a data line drive circuit, such as an organic electroluminescence (EL) panel, a liquid crystal on silicon (LCOS) display, a plasma display panel, a field emission display, and electronic paper.
In the same field of endeavor, displaying images in different modes including at least one mode with regions displayed having different frequencies (see Seo figure 1, element 100, PXL; figure 2, MODE1, MODE2, figure 3, PXL and paragraphs 0066-0082), Seo teaches a pixel circuit comprises a drive transistor (see Seo figure 3, element T1 and paragraph 0096 where first transistor T1 (drive transistor)), a data write transistor (see Seo figure 3, element T2 and paragraph 0097 where second transistor T2 may be connected between the data line DLj and the second node N2. A gate electrode of the second transistor T2 may be connected to the scan line SLi. The second transistor T2 may be turned on when the scan signal is supplied to the scan line SLi to electrically connect the first electrode of the first transistor T1 to the data line DLj), a reset transistor (see Seo figure 3, element T4 and paragraphs 0100 where fourth transistor T4 may be turned on to supply the initialization power supply voltage Vint to the third node N3) and a compensation transistor (see Seo figure 3, element T3 and paragraph 0098-0099 where when the third transistor T3 is turned on, the first transistor T1 may be connected in the form of a diode and storage capacitor Cst may store a voltage corresponding to the data signal and to a threshold voltage of the first transistor T1), wherein the data write transistor is connected to a first terminal of the drive transistor and is configured to provide a data signal to the drive transistor (see Seo figure 3, element T2 and paragraph 0097 where second transistor T2 may be connected between the data line DLj and the second node N2. A gate electrode of the second transistor T2 may be connected to the scan line SLi. The second transistor T2 may be turned on when the scan signal is supplied to the scan line SLi to electrically connect the first electrode of the first transistor T1 to the data line DLj); the reset transistor is connected to a control terminal of the drive transistor and is configured to provide a reset signal to the drive transistor (see Seo figure 3, element T4 and paragraphs 0100 where fourth transistor T4 may be turned on to supply the initialization power supply voltage Vint to the third node N3); the compensation transistor is connected between a second terminal of the drive transistor and the control terminal of the drive transistor (see Seo figure 3, element T3, T1, N3, N1); and the preset circuit is one of the data write transistor, the reset transistor, or the compensation transistor (see Seo figure 1, element 120 scan driver, figure 3, element T2 where element T2 is between the data signal input node and N2 and the data signal is input by activation of the scan line).
One of ordinary skill would have been motivated to have modified Maruyama with the teachings of Seo to have the recited pixel circuit so as to form a display having a light emitting element as suggested by Maruyama at paragraph 0038.
Response to Arguments
Applicant's arguments filed September 29, 2026 have been fully considered but they are not persuasive.
With respect to the claim interpretation under 35 USC 112(f) Examiner respectfully disagrees. For a term to be considered a substitute for "means," and lack sufficient structure for performing the function, it must serve as a generic placeholder and thus not limit the scope of the claim to any specific manner or structure for performing the claimed function. It is important to remember that there are no absolutes in the determination of terms used as a substitute for "means" that serve as generic placeholders. The examiner must carefully consider the term in light of the specification and the commonly accepted meaning in the technological art. Every application will turn on its own facts. The USPTO must apply 35 U.S.C. 112(f) in appropriate cases, and give claims their broadest reasonable interpretation (BRI), in light of and consistent with the written description of the invention in the application. In determining the BRI, examiners should establish the meaning of each claim term consistent with the specification as it would be interpreted by one of ordinary skill in the art, including identifying and construing functional claim limitations. If a claim limitation recites a term and associated functional language, the examiner should determine whether the claim limitation invokes 35 U.S.C. 112(f). Application of 35 U.S.C. 112(f) is driven by the claim language, not by applicant’s intent or mere statements to the contrary included in the specification or made during prosecution. To determine whether a word, term, or phrase coupled with a function denotes structure, examiners may check whether: (1) the specification provides a description sufficient to inform one of ordinary skill in the art that the term denotes structure; (2) general and subject matter specific dictionaries provide evidence that the term has achieved recognition as a noun denoting structure; and/or (3) the prior art provides evidence that the term is an art-recognized structure to perform the claimed function. Ex parte Rodriguez, 92 USPQ2d 1395, 1404 (Bd. Pat. App. & Int. 2009) (precedential). Note that there is no fixed list of generic placeholders that always result in 35 U.S.C. 112(f) interpretation, and likewise there is no fixed list of words that always avoid 35 U.S.C. 112(f) interpretation. Every case will turn on its own unique set of facts. MPEP 2181.
One of the limitations in question recites, “preset circuit”. The MPEP states in 2181 that the presumption that 35 U.S.C. 112(f) applies is overcome when the limitation further includes the structure, material or acts necessary to perform the recited function. The term “circuit” is not the structure as “circuit” is a generic term of reference for a group of components in an electronic circuit that is composed of items such as resistors, transistors, capacitors, inductors and diodes etc. connected by wires or traces that allow or prevent the flow of current. In fact, the Cambridge dictionary defines circuit as “a closed system of wires or pipes through which electricity or liquid can flow”. Clearly this claim limitation is attempting to describe a singular part of a closed system and not the system itself. This particular limitation, nor the application, limits how one defines “circuit”. "Sufficient structure exists when the claim language specifies the exact structure that performs the function in question without need to resort to other portions of the specification or extrinsic evidence for an adequate understanding of the structure." See TriMed, Inc. v. Stryker Corp., 514 F.3d 1256, 1259-60, 85 USPQ2d 1787, 1789 (Fed. Cir. 2008) The term “circuit” is being used here as a generic placeholder for the term “means” and would not be recognized by one of ordinary skill in the art, in this context, as being sufficiently definite structure for performing the claimed function without having to resort to looking to the specification for an understanding for how that function is performed. In the case of Mass. Inst. of Tech., 462 F.3d at 1355-1356, 80 USPQ2d at 1332, the court found that the recitation of "aesthetic correction circuitry" was sufficient to avoid pre-AIA 35 U.S.C. 112, paragraph 6 because the term “circuit”, combined with a description of the function of the circuit, connoted sufficient structure to one of ordinary skill in the art. In the instant application, as noted above, the claim limitations lack sufficient description of the circuit that performs the function of controlling the first node. The addition of the word “circuit” to a claim limitation, in this instance, will not avoid a 112(f) interpretation unless sufficient structure or acts for performing the function are additionally recited.
Regarding Applicant’s incorporation of the term “transistor” in claim 3, Examiner respectfully notes that Applicant’s original disclosure does not use the term “transistor”, “TFT” or “switching element”. Therefore, Applicant’s argument on page 8 that “Claim 2 separately recites a circuit in the pixel circuit's data signal input path, a control terminal that receives a preset control signal, an on-state associated with pixel data refresh, and a driver circuit supplying that signal to the control terminal. In this context, the limitation identifies an electrically controlled switching circuit at a specified location in the pixel circuit. "Preset" identifies the selected circuit and associated control signal; it does not remove the structural significance of the recited path, control terminal, and switching relationship. Applicant does not import the narrower transistor limitations of claim 3 into claim 2. Rather, claim 2 identifies the broader switching-circuit structure through its own limitations, and claim 3 specifies particular transistor implementations. The breadth of the former does not, by itself, establish that its circuit terminology is merely a substitute for "means." Claims 4-7 further concern the driver portions and control signals associated with the circuit of claim 2.”, further emphasizes the ambiguity of structure corresponding to “preset circuit” since none of Applicant’s original figures illustrate any specific components of the alluded to “circuit” nor does Applicant’s original disclosure mention any specific components such as transistors which are commonly known in the art. Therefore not patentably distinguishing over the prior art without more.
Regarding Applicant’s assertion with respect the rejection under 35 USC 112(a) that “”the original disclosure, read through the understanding of a person skilled in pixel-circuit design, supports the claimed structures and the present amendments”, Examiner respectfully disagrees. As articulated above, Examiner specifically notes that Applicant’s original specification does not mention “transistor”, “TFT: or “switching element”. Further, Applicant’s remarks dated September 29, 2026, fails to identify which portion of the original specification supports the incorporation of the term “transistor” and that original disclosure intended to corresponds to a single transistor. Particularly in view of Applicant’s remarks dated September 29, 2026 on page ten “For claim 2 and claims 4-7, the original disclosure supports the broader controlled circuit and driver relationships without requiring every circuit to be limited to a single transistor.”. Since Applicant’s original specification merely illustrates labeled boxes in the figures and generally teaches “circuit” without any specific example or description of a broader multi-component “circuit”., Examiner must maintain that the original specification fails to provide sufficient written description of the claimed features because Applicant maintains that the claims should not be limited to a single transistor circuit as now recited in claim 3. Further emphasizing that none of the original disclosure specifically identifies specific structure components. Leaving one unable to discern specifically what single/multi-component “circuit” has been contemplated by Applicant.
Regarding Applicant’s remarks with respect to the rejection under 35 USC 112b, Examiner is unpersuaded. As discussed, Applicant’s original disclosure does not provide any specific structure for the “circuits”. Examiner can find no reasonable interpretation that any other transistor than a data write transistor (module) is “in the data path”. There are no figures illustrating how Vdata path would correspond to any other component.
Regarding Applicant’s remarks with respect to the rejection of the claims under 35 USC 103 in view of Maruyama, Examiner has attempted to better explain in the rejection above. .
The fact that applicant has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Nakano et al, U.S. Patent Publication No. 20040051706 (display apparatus), Jang et al, U.S. Patent Publication No. 20140085276 (display apparatus), Yamazaki et al, U.S. Patent Publication No. 20140292741 (display device), Kim et al, U.S. Patent Publication No. 20150358018 (display device), Park et al, U.S. Patent Publication No. 20210027707 (display device), Park et al, U.S. Patent Publication No. 20210027720 (display device), Lee et al, U.S. Patent Publication No. 20210110771 (display device), Jung, U.S. Patent Publication No. 20220189363 (display device), Kim et al, U.S. Patent Publication No. 20220351660 (display device).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dorothy H Harris whose telephone number is (571)270-7539. The examiner can normally be reached Monday - Friday 8am - 4pm.
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/Dorothy Harris/Primary Examiner, Art Unit 2625
