The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination
Allowable Subject Matter
Claims 5, 7-8, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 9-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cooper (US Patent Application 20210208663) in the view of Ibrahim (US Patent Application 20110291746)
As per claim 1, Cooper teaches an apparatus [100, fig. 1], comprising:
a processing circuit [120, fig. 1] that includes a set of functional block circuits [125, fig. 1] and performance counter registers [performance counter values stored in register: 0047] configured to store utilization values indicative of utilization of associated ones of the set of functional block circuits [0047, as pointed out the CPU’s utilization values are stored in the performance counter register].
a set of trace buffer circuits [132, fig. 1 or storage elements 0105].
a register interface circuit [architectural counter, fig. 2B] configured, during operation of the processing circuit, to [0054, sampling CPU’s operation during CPU execution]:
periodically sample the processing circuit to obtain aggregated utilization values generated from utilization values stored in the performance counter registers [0100, sampling utilization over a period of time and perform averaging of the CPU’s].
write the aggregated utilization values to the set of trace buffer circuits [0105, the values are from steps of figure 4 are stored].
Cooper does not teach a power management processor circuit configured to utilize a set of information stored in the set of trace buffers to determine whether to change a performance state of the processing circuit, the set of information including time-domain and frequency-domain representations of utilization of the processing circuit that are generated from the aggregated utilization values.
However, Ibrahim teaches a power management processor circuit [212, fig. 1] configured to utilize a set of information stored in the set of trace buffers [accumulated values stored in memory: 0035] to determine whether to change a performance state of the processing circuit, the set of information including time-domain [this approach enable the GPU to adjust: 0035] representations of utilization of the processing circuit that are generated from the aggregated utilization values [0032, 0033, 0035, 0056 fig. 6-7, as shown in figure 6-7, the accumulated values are used to perform power adjustment for the GPU].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Cooper to include the method of Ibrahim to store the accumulated time interval values then user them to perform power adjustment for the system in order to manage power consumption.
A per claim 12, Cooper teaches a method [method shown in figure 5] comprising:
maintaining, in a graphics processing unit (GPU) [120, fig. 1] having a set of functional block circuits [125, fig. 1], utilization values in a set of performance counter registers [performance counter values stored in register: 0047], the utilization values being indicative of the utilization of associated ones of the set of functional block circuits [0047, as pointed out the CPU’s utilization values are stored in the performance counter register].
periodically sampling, by the GPU, the performance counter registers for the set of functional blocks, wherein the periodically sampling includes [0100, sampling utilization over a period of time and perform averaging of the CPU’s]:
aggregating, by the GPU, utilization values in the sampled performance counter registers [0105, the values are from steps of figure 4 are stored].
Cooper does not teach storing, by the GPU, the aggregated utilization values in a set of trace buffer circuits that is configured to generate time-domain and frequency-domain representations of utilization of the GPU;
and determining, by the GPU in real time based on information stored in the set of trace buffer circuits, whether to change a performance state of the GPU.
storing, by the GPU, the aggregated utilization values in a set of trace buffer circuits that is configured to generate time-domain and frequency-domain representations of utilization of the GPU;
and determining, by the GPU in real time based on information stored in the set of trace buffer circuits, whether to change a performance state of the GPU.
However, Ibrahim teaches storing, by the GPU, the aggregated utilization values in a set of trace buffer circuits buffers [accumulated values stored in memory: 0035] that is configured to generate time-domain [signal sampling interval time interval: 0031] and frequency-domain [frequency parameter: 0030] representations of utilization of the GPU [0030-0033, 0035, as pointed out the value are accumulated and summed which determine the performance utilization of the processor].
determining, by the GPU in real time based on information stored in the set of trace buffer circuits, whether to change a performance state of the GPU [0032, 0033, 0035, 0056 fig. 6-7, as shown in figure 6-7, the accumulated values are used to perform power adjustment for the GPU].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Cooper to include the method of Ibrahim to store the accumulated time interval values then user them to perform power adjustment for the system in order to manage power consumption.
As per claim 2, Cooper teaches the register interface circuit [architectural counter, fig. 2B] is further configured, during operation of the processing circuit, to:
periodically sample the processing circuit to obtain values indicative of work information and stall information for individual ones of the set of functional block circuits [0054-0054, fig. 2B, perform time sampling of data or signals active or stalled].
write the work information and the stall information to the set of trace buffer circuits [0105, where values can be written to the memory as indicated].
As per claim 3, Cooper teaches the power management processor circuit is configured to utilize the values indicative of the work information and the stall information for individual ones of the set of functional block circuits to determine one or more functional block circuits that are hardware limiters for the processing circuit [0076, 0085, 0088, the workload, frequency and stall information can be used to make power adjustment decision].
As per claim 4, Cooper teaches values indicative of the work information and the stall information are usable to compute a relationship between frequency dependence and performance for individual ones of the set of functional block circuits [0027-0028, workload information and install information can be used to make power decision by circuit 110].
As per claim 6, Cooper teaches a given utilization value is indicative of switching capacitance of a corresponding one of the set of functional block circuits [0041, power related to processor capacitance].
As pe claim 9, Cooper teaches the register interface circuit is configured, for a particular sample of the processing circuit, to simultaneously determine an average aggregated utilization value, a maximum aggregated utilization value, and a minimum aggregated utilization value [0093, aggregate value as well as accumulated values].
As per claim 10, Cooper teaches the power management processor circuit is configured to operate in a max thermal mode in which the processing circuit has a specified power budget and dithering is performed between two p-states, in which the timing of the two p-states is selected based on the time-domain representation of utilization of the processing circuit stored in the set of trace buffers [0034, 0046, different power level or limit can be selected by the platform power governance 110].
As per claim 11, Cooper teaches the power management processor circuit is configured to operate in a max current mode in which the processing circuit attempts to reduce current throttles by transitioning to a lower p-state during utilization peaks and by transitioning to a higher p-state during utilization valleys [0022, 0024, power or current throttling signals to activate a power reduction of the processing units].
As per claims 13-17 and 19-29, they do not teach or further define over the limitations recited in the rejected claims above. Therefore, claims 12-17 and 19-20 are also anticipated by Cooper for the same reasons set forth in the rejected claims above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Iwamoto (US 20180349146) teaches GPU resource tracking.
Altmejd (US 6895520) teaches performance and power optimization via block oriented performance measurement and control.
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/VOLVICK DEROSE/Primary Examiner, Art Unit 2176