DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US publication 2012/0299093 A1), hereinafter referred to as Kim093.
Regarding claim 1, Kim093 teaches a method (a method of making of a device in fig. 1 and related text), comprising: implanting a chemical species within lightly doped drain (LDD) regions (120/140, [0033-0038]) extending into a semiconductor substrate (10, [0033]) to form breakdown-enhancement implant (BEI) intrusion regions 150/155, [0033 and 0053]) within the LDD regions and having upper boundaries below an upper surface of the semiconductor substrate (fig. 1), the chemical species of the BEI intrusion regions having a different conductivity type than additional chemical species within LDD regions (fig. 1); and forming a gate electrode (160, [0033]) over a channel region horizontally interposed the LDD regions (fig. 1).
Regarding claim 2, Kim093 teaches further comprising: forming the BEI intrusion regions to vertically extend into and terminate within portions of the semiconductor substrate to underlying the LDD regions; and forming the BEI intrusion regions to be horizontally interposed between the channel region and source/drain (S/D) regions extending into the LDD regions (fig. 1).
Regarding claim 3, Kim093 teaches further comprising forming the BEI intrusion regions to be substantially horizontally centered between the channel region and the S/D regions (fig. 1).
Regarding claim 4, Kim093 teaches further comprising forming upper boundaries of the S/D regions and the LDD regions to be substantially coplanar with the upper surface of the semiconductor substrate (fig. 1).
Regarding claim 5, Kim093 teaches further comprising: selecting the semiconductor substrate to comprise semiconductor material doped with P-type dopant; selecting the chemical species to comprise P-type dopant; and selecting the additional chemical species to comprise N-type dopant (fig. 1).
Regarding claim 6, Kim093 teaches further comprising: selecting the semiconductor substrate to comprise semiconductor material doped with N-type dopant; selecting the chemical species to comprise P-type dopant; and selecting the additional chemical species to comprise N-type dopant (fig. 1).
Allowable Subject Matter
Claims 7-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 7 is allowable primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combinations with all other limitations:
“…two lightly doped drain (LDD) regions horizontally surrounding the two S/D regions, portions of the two LDD regions horizontally interposed between the channel region and the two S/D regions; a gate structure vertically overlying and horizontally overlapping the channel region; and gate dielectric material vertically interposed between and horizontally overlapping the gate structure and the channel region; and forming breakdown-enhanced implant (BEI) intrusions within the portions of the two LDD regions of the transistor, the BEI intrusions respectively having a different conductivity type than the LDD regions".
Kim (US publication 2012/0299093 A1) discloses some features of the claimed invention as explained above for claim 1.
However Kim or the prior arts of record, singly or in combination, neither anticipates nor render obvious the above quoted limitations when taken in combinations with all other limitations.
Therefore, the independent claim 7 is allowed. The dependent claims 8-15 are allowed for their dependency to claim 7.
Claim 16 is allowable primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combinations with all other limitations:
“…a channel region horizontally interposed between the LDD N−wells; and a gate electrode vertically overlying and horizontally overlapping the channel region; and forming P-type breakdown-enhanced implant (BEI) intrusions within the LDD N−wells of the NMOS structures, the P-type BEI intrusions individually horizontally interposed between the channel region and the N+ S/D contact regions of respective ones of the NMOS structures”.
Kim (US publication 2012/0299093 A1) discloses some features of the claimed invention as explained above for claim 1.
However Kim or the prior arts of record, singly or in combination, neither anticipates nor render obvious the above quoted limitations when taken in combinations with all other limitations.
Therefore, the independent claim 16 is allowed. The dependent claims 17-20 are allowed for their dependency to claim 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohammed R Alam whose telephone number is 469-295-9205 and can normally be reached between 8:00am-6:00pm (M-F) or by e-mail via Mohammed.Alam1@uspto.gov.
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/MOHAMMED R ALAM/Primary Examiner, Art Unit 2897