Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
1. Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 112
2. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 5-7, the phrase "may" renders the claim indefinite because it is unclear whether the limitation(s) following the phrase are part of the claimed invention. See MPEP § 2173.05(d).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
3.1 Claims 11-16, 18-20 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Malley et al. (A Programmable Digital Pulse Width Modulator Providing Versatile Pulse Patterns and Supporting Switching Frequencies Beyond 15 MHz) in view of Fernald (US 7,568,117 B1)
Regarding claim 1, Malley discloses a power supply controller (Fig. 1, the digital controller) for a switching power converter (page 53, column 1, par. 2, Fig. 1, digitally controlled by digital controller (shaded area of Fig. 1) power converter is shown in Figure 1. Power is taken from a source, processed by
a switching converter, and delivered to a load), the power supply controller (Fig. 1, microcontroller) being implemented in an integrated circuit (Fig. 1, page 53, column 2, par. 2-3, the microprocessor is integrated circuit (IC) with the DPWM, as shown in Fig. 1) and comprising:
a digital pulse width modulator (Fig. 1, DPWM IC) arranged to generate a switching signal to drive the switching power converter (Abstract, Fig. 1, page 53, column 2, par 2-3, page 54, column1, par. 2, page 55, column 2, par. 2, programmable DPWM module, allows the generation of high resolution, high switching frequency PWM signals. Digitally controlled switching converters (Figure 1) typically require the DPWM to interface to both a CPU (for programming parameters on start-up and status monitoring during normal operation) and a feedback controller (for cycle-by-cycle duty-cycle updates) as shown in Figure 2);
a control processor (CPU) arranged to provide a control signal to the digital pulse width modulator for controlling the switching power converter (Fig. 1, Fig. 2, Fig. 5, page 54, column 2, Digitally controlled switching converters (Figure 1) typically require the DPWM to interface to both a CPU (for programming parameters on start-up and status monitoring during normal operation) and a feedback controller (for cycle by-cycle duty-cycle updates) as shown in Figure 2); and
a fault protection circuit (Fig. 6, power supply protection features) arranged to limit an operation of the digital pulse width modulator (Fig. 5, Fig. 6, page 55, column 1, par. column 2, par. 4, An asynchronous input Stop-n supports power supply protection features (such as high-speed over-current protection). To protect the switches in the power stages activation of Stop-n resets all PWM outputs to zero within 1 ns).
Malley fails to disclose a housekeeping processor arranged to facilitate communications over a serial communication bus.
However, Fernald discloses a housekeeping processor (controller 502 or microcontroller 302) arranged to facilitate communications over a serial communication bus (column 4, lines 8-17, column 6, lines 37-53, a digital bus 504. Digital bus 504 may be a serial bus enabling communication with reduced wiring requirements. In the configuration shown in FIG. 5, real-time communication is made possible between power converters 510, 512, and 514 and controller 502 by their being coupled to serial digital bus 504. It is noted, however, that in other embodiments the power converters may communicate with the controller 502 and with each other by other means, e.g., a parallel bus, or some of the functionality has be programmed into a microcontroller that may communicate with attached POL converters over an I.sup.2C (inter-IC communication) bus to coordinate control of all POL converters in the system. The microcontroller 302 may be coupled to POL converters 320, 322, 324, and 326, with the connections between the devices representing an I.sup.2C bus).
Mally and Fernald are analogous art. They relate to a fault detection mechanism for monitoring an output voltage of the power supply. Therefore, before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify DC-to-DC converter, thought by Fernald, incorporated with a digitally controlled switching power converters, taught by Malley, in order to modify in various ways and by various methods in response to detecting a margining event and adapts thresholding technique to implemented for current thresholds and/or power thresholds.
Regarding claim 2, Malley discloses the fault protection circuit (page 55, such as high-speed over-current protection) is capable of limiting (Page 55, stop-n) the operation of the digital pulse width modulator (Fig. 1, programmable DPWM) in response to a fault condition set by the housekeeping processor (page 55, column 2, par. 4, Fig. 5, an asynchronous input Stop-n supports power supply protection features (such as high-speed over-current protection). To protect the switches in the power stages activation of Stop-n resets all PWM outputs to zero within 1 ns).
Regarding claim 3, Malley discloses the serial communications bus is arranged to transfer multiple signals serially (Fig. 2, Fig. 5, Fig. 7, Fig. 8, page 56, column 1, par, 4, a multiple communication bus and The I/O Control block contains all the programmable registers (e.g. duty-cycle, dead/delay times, number of bits resolution) and controls all communication via the CPU or DSP to/from the DPWM).
Regarding claim 4, Malley discloses the housekeeping processor (Fig. 1, microprocessor) arranged to ensure that the control processor (CPU) is not distracted from controlling the switching power converter through the digital pulse width modulator (Fig. 1, page 53 the digitally controlled switching converters, as shown in Fig, 1, is directly control by microprocessor without the need or CPU; and page 54, column 2, par. 2, digitally controlled switching converters (Figure 1) typically require the DPWM to interface to both a CPU (for programming parameters on start-up and status monitoring during normal operation) and a feedback controller (for cycle by-cycle duty-cycle updates) as shown in Figure 2).
Regarding claim 5, Ferland discloses a fault condition (fault detection mechanism 775) set by the housekeeping processor (master controller 800) may include one of the following conditions: an input Under-Voltage Lockout; or a programmable response to Under Voltage Lock Out condition (Abstract, Fig. 8 and 9, column 2, lines 30-43, 17) The final voltage presented to a load may need to be programmed to the desired value or may need to be "trimmed" to a precise value. Some systems require active voltage programming of devices during their use. To maintain high reliability of an electronic system, monitoring of load status is sometimes required. Both current and voltage may need to be monitored, and action may need to be taken based on the load status measurements. Current and voltage may also need to be monitored for undershoot and overshoot conditions. In some systems, when an error is detected, the system may take corrective action by switching the load off, isolating the load or just setting a system flag).
Regarding claim 6, Fernald discloses a fault condition set (fault detection mechanism 775) by the housekeeping processor (a controller 502 managing functions 1) may include one of the following conditions: an output voltage Over-voltage protection trip-point; an input voltage over-voltage protection threshold; a programmable response to Over Voltage Lock Out condition; or a programmable response to Over Current Protection condition (Abstract, Fig. 8 and 9, column 4, lines 45-58, column 5, lines 9-25, a power supply may include a fault detection mechanism for monitoring an output voltage of the power supply to determine whether the output voltage is greater than a first over-voltage threshold or less than a first under-voltage threshold).
Regarding claim 7, Fernald discloses a fault condition set (fault detection mechanism 7727) by the housekeeping processor (master controller 800) may include one of the following conditions: an over-temperature protection threshold () or a programmable response to Over Temperature Protection condition (column 2, line 65-column 4, line 10; Temperatures can be measured using several methods. Some large digital processors sometimes incorporate embedded temperature sensor diodes on chip. Other systems may employ thermistors and IC temperature sensors. When temperatures reach unacceptable limits, action may need to be taken locally and/or at the system level. Such corrective actions often include turning on or speeding up fans, setting an alarm or simply shutting down the power to the problematic load).
Regarding claim 8, Malley discloses the power supply controller (FIG. 1, Fig. 5, page 53, column 2, par. 2 and 5, digital controller IC) is provided with a single processor (Fig. 2, Fig. 5, DSP interface) combining functions of the control processor (Fig. 2, Fig. 5, page 55, par. CPU interface) and the housekeeping processor (Fig. 1, page 53, column 2, par. 2, and 5, microprocess).
Regarding claim 9, Fernald discloses roles of the control processor (supply controller 350) are further broken-down with more than two functional blocks (Fig. 4, Fig. 5, supply controller 350 are included a plurality of blocks of DC-to-DC converter function 352, 354, 356, 358).
Regarding claim 10, Fernald discloses roles of the housekeeping processor (master controller IC 800) are further broken-down with more than two functional blocks (Fig. 6, the master controller 800 are divided to a multiple function 602, 604…606).
Regarding claim 11, Fernald discloses the control processor is arranged to operate upon external measurement of sensed output voltage (column 2, lines 35-55, both current and voltage may need to be monitored, and action may need to be taken based on the load status measurements. Current and voltage may also need to be monitored for undershoot and overshoot conditions. In some systems, when an error is detected, the system may take corrective action by switching the load off, isolating the load or just setting a system flag).
Regarding claim 12, Fernald discloses the control processor is arranged to operate upon external measurement of output current (column 2, lines 35-55, Current and voltage may also need to be monitored for undershoot and overshoot conditions, both current and voltage may need to be monitored, and action may need to be taken based on the load status measurements).
Regarding claim 13, Fernald discloses the housekeeping processor (microprocessor 305) is arranged to receive data for programming a configuration setting through the serial communication bus (Fig. 3, column 4, lines 8-26, functionality is programmed into a microcontroller that may communicate with attached POL converters over an I.sup.2C (inter-IC communication) bus to coordinate control of all POL converters in the system).
Regarding claim 14, Farnald discloses the power supply controller (supply controller 502) is used in different converter circuits (converter circuits 510-514) and the configuration setting (Fig. 5, configuration within the system) for the different converter circuits (POL converters 320-326) is set by the data through the serial communication bus (column 6, lines 46-53, real-time communication is made possible between power converters 510, 512, and 514 and controller 502 by their being coupled to serial digital bus 504) (Fig. 5, Fig. 7,column 6, lines 36-53).
Regarding claim 15, Fernald discloses the control processor (Fig. 4-7, digital power management devices (DPMD)) using a set of configuration parameters in a configuration setting set by the housekeeping processor (master controller 800) (Fig. 4-7, Bus 610 allow each digital power management devices (DPMD) to be coupled to a master control IC 800, to enabling all system level functions to be configured, controlled and monitored providing simple and flexible results).
Regarding claim 16, Farnald discloses the housekeeping processor (microcontroller 302)is arranged to perform a measurement for a single measurement value (column 3, lines 7 and 53-55, single points of temperature measurement form the IC temperature sensors) for programming a configuration setting from at least one external component connected (column 4, lines 10-15, a microcontroller 302 may be coupled to POL converters 320, 322, 324, and 326, with the connections between the devices representing an I.sup.2C bus) to a first programming pin (column 4, lines 7-25, functionality (configuration setting) is programmed into a microcontroller that may communicate with attached POL converters (outside device) over an I.sup.2C (inter-IC communication) bus to coordinate control of all POL converters in the system and implement the functions in control ICs (pin) responsible for controlling respective POL converters).
Regarding claim 18, Farland discloses the power supply controller (Fig. 6, master controller 800) is used in different converter circuits (Fig. 7, POL power converter 7754A-7750D) and the configuration setting for the different converter circuits is set by the single measurement value (column 7, lines 43-60, bus converter 750 and/or power converters 725 may be configured as DC-to-DC converters, digital power management devices (DPMDs), and AC-to-DC converters, among others. In one embodiment, power converters 725A-725D are connected to loads 770A-770D, respectively that shows a fault detection mechanism 7757 using a signal threshold for a different converter circuit).
Regarding claim 19, Farland discloses the power supply controller (Fig. 6, master controller 800) is operable to adopt a set of two or more configuration parameters in the configuration setting corresponding to the single measurement value (column 2, lines 65-column 4, line 10, When temperatures measured reach unacceptable limits (single measurement value), action may need to be taken locally and/or at the system level. Such corrective actions often include turning on or speeding up fans, setting an alarm or simply shutting down the power to the problematic load (a plurality configuration parameter).
Regarding claim 20, Farland discloses at least one of the set of configuration parameters in the configuration setting are one of: a) an output voltage set-point (; b) a communication address; c) a switching frequency; d) an output current limit; e) an input Under-Voltage Lockout; f) a maximum output voltage set-point which can be commanded; g) an output voltage set-point for margin high test; h) an output voltage set-point for margin low test; i) an output voltage Over-voltage protection trip-point; j) an output voltage offset correction parameter; k) an output voltage rise time; l) an output voltage ramp delay following an ON command; m) an output voltage ramp delay following an ON command; n) a programmable response to Under Voltage Lock Out condition; o) an input voltage over-voltage protection threshold; p) a programmable response to Over Voltage Lock Out condition; q) a programmable response to Over Current Protection condition; r) an output current lethal protection; s) a phase drop feature on/off; t) an output current phase drop threshold; u) an over-temperature protection threshold; v) a programmable response to Over Temperature Protection condition; w) a programmable response to OPERATION command; x) a programmable response to CTRL pin; y) a programmable polarity of CTRL pin; z) a minimum duty cycle; aa) a maximum duty cycle; bb) a MOSFET driver type; cc) a multi-Point Of Load stress share feature; dd) a multi-Point Of Load synchronization feature; or ee) a multi- Point Of Load synchronization phase shift (Abstract, a fault detection mechanism for monitoring an output voltage of the power supply to determine whether the output voltage is greater than a first over-voltage threshold or less than a first under-voltage threshold; column 2, lines 35-44, monitoring of load status is sometimes required. Both current and voltage may need to be monitored, and action may need to be taken based on the load status measurements. Current and voltage may also need to be monitored for undershoot and overshoot conditions; column 2, lines 60-67, temperature motoring; column 3, lines 62-67, control of the POL converters in order for the particular function to be successfully executed during system operation).
3.2 Claim 17 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Malley et al. (A Programmable Digital Pulse Width Modulator Providing Versatile Pulse Patterns and Supporting Switching Frequencies Beyond 15 MHz) in view of Fernald (US 7,568,117 B1) further in view of Brinkhus (US 20040199674 A1).
Regarding claim 17, the combination of Malley and Fernald discloses the limitations of claims 1 and 16 but fails to disclose the limitations of claim 17. However, Brinkhus discloses as follows:
Regarding claim 17, Brinkhus discloses an analog to digital converter for the measurement for the single measurement value, and the single measurement value is provided from the analog-to-digital converter to the housekeeping processor ([0002],[0113], [0122], [Fig.1-3, measurement values, control signals, analog-to-digital converter and the like are transferred to a computer or from the computer back to machines and instruments).
Brinkhus, Malley and Fernald are analogous art. They relate to a fault detection mechanism for monitoring an output voltage of the power supply. Therefore, before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify ADC and DCA converter, thought by Brinkhus incorporated with teaching of Fernald and Malley, in order to increase measurement accuracy, the measurement method can also be dynamically switched during operation between the counting of pulses per unit time and the pulse width or period measurement, that give the interface circuit chip a simple and universal structure.
Citation Pertinent prior art
4. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Leung (US20060022731A1) discloses DPWM with built-in protection functions for over current, over voltage and temperature.
Lavier (US 20080239593 A1) discloses providing digital pulse width modulator (DPWM) with built-in protection functions for over current, over voltage and temperature. A voltage regulator failure detection circuit, system, and operating method enable fast detection of failure that is highly useful in redundant voltage regulator arrangements.
Sasaki (US20090108827A1) discloses an under voltage lock out circuit which monitors an input voltage and executes a predetermined sequence when the input voltage satisfies a predetermined condition may include a voltage comparison unit which compares the input voltage and a predetermined threshold voltage, and outputs a comparison signa.
CHEN (CN 1464607 A) discloses an automatic power supply protection device that can be configured in an electronic device. All power supplies can be pulled to the utmost point low-voltage of practically negligible volt, at this moment will not have any power available in the system and start circuit overcurrent protection (over current protection circuit).
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for allthat it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed wereinstead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1 009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. Biocraft Labs., Inc., 874 F.2d804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163USPQ 545, 549 (CCPA 1969).
Conclusion
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kidest Worku, whose telephone number is 571-272-3737. The examiner can normally be reached on Mon-Fri 9am to 5pm, ET.
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/KIDEST WORKU/Primary Examiner, Art Unit 2119
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