DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6, 11-15, 16-17 and 22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. 20230020883 herein Liu.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 6, 11-15, 16-17 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Erez 20170060461 herein Erez.
Per claim 1, Liu discloses: c comprising a plurality of planes, each plane in the plurality of planes comprising a plurality of word lines; (¶0022; a projection of the first word line 151 on a plane formed jointly by the second direction D2 and the direction D3 perpendicular to the top surface of the substrate is arranged in an at least partially staggered manner from a projection of the second word line 152 on the plane formed jointly by the second direction D2 and the direction D3 perpendicular to the top surface of the substrate. Therefore, an opposite area of the first word line 151 and the second word line 152 in the first direction D1 is reduced, thereby reducing the capacitive coupling effect between the first word line 151 and the second word line 152.; the examiner notes that the planes are merely memory substates/dies in the memory) the method comprising: configuring the storage device with a multi-plane word line that comprises a word line from each of the plurality of planes: (fig. 1&2, ¶0022; FIGS. 1 and 2, each of the word lines 15 extends in the direction D3 perpendicular to the top surface of the substrate, to form vertical word line structures. The plurality of the word lines 15 are arranged at intervals along the first direction D1) and performing a write operation or read operation on the multi-plane word line (¶0022; the capacitive coupling effect between the word lines is reduced by arranging the adjacent word lines in a staggered manner; ¶0002A word line voltage on the word line can control on and off of the transistor, so that data information stored in the capacitor can be read or written into the capacitor through the bit line; the examiner notes that the capacitive coupling occurs during reads/writes).
Lui discloses partially staggered adjacent word lines or memory substrates/dies but does not specifically disclose: wherein a first word line of the multiple-plane word line has a first index, and wherein a second word line of the multi-plane word line has a second index that is offset from the first index.
However, Erez discloses: wherein a first word line of the multiple-plane word line has a first index, and wherein a second word line of the multi-plane word line has a second index that is offset from the first index (¶0078; If the memory comprises a multi-plane memory die, the controller 102 can create a meta wordline by grouping together a word line from each of the planes. If the memory comprises a plurality of multi-plane memory dies, the controller 102 can create a meta wordline by grouping together a word line from each of the planes. Also, in creating a meta wordline by grouping together word lines with complementary memory addresses, the controller 102 can use a formula-based constant shift address option (such as WL_Address_B=WL_Address_A+Max_WL_Per_Block/2, that wraps around at Max_WL_Per_Block boundary) or an offset option (e.g., program WL N from die 1 together with WL N+Offset from die 0, where the Offset=Max_WL_Per_Block/2), for example.)
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Lui and Erez’s meta wordlines with offsets to achieve efficient peak current consumption (¶0046; The controller is configured to perform at least one of the following: create a plurality of sets of blocks that will have similar peak current consumption when programmed in parallel by grouping together blocks with complementary peak current consumption; and creating a plurality of metawordlines that will have similar peak current consumption by grouping together word lines with complementary peak current consumption).
Per claim 2, Lui discloses: wherein the multi-plane word line comprises a third word line of a third plane having a third index, and wherein the third index is offset from the second index by a magnitude that is equal to a magnitude of the offset from the second index to the first index (fig. 2, ¶0024; Take the plurality of the word lines 15 arranged at intervals along the first direction D1 as an example, arranging any two adjacent ones of the word lines 15 in a completely staggered manner means that projections of any two adjacent ones of the word lines 15 along the first direction D1 on a plane formed jointly by the second direction D2 and the direction D3 perpendicular to the top surface of the substrate are separated from each other (that is, the projections do not overlap each other). By arranging the two adjacent word lines 15 in a completely staggered manner, the capacitive coupling effect between the two adjacent word lines 15 can be sufficiently eliminated, thereby better improving the performance of the semiconductor structure; the examiner notes that the third wordline is merely extending the word lines in the plane as seen in the cited fig. 2 ).
Per claim 3, Lui discloses: wherein the first index and the second index are associated with a range of indices associated with tiers of word lines, wherein the first index has a first value and is associated with a first tier of word lines, wherein the second index has a second value and is associated with a second tier of word lines, and wherein the second value is equal to the first value (fig. 2, ¶0032; long the first direction D1, the plurality of word lines are sequentially ordered. That is, in the first direction D1, the odd-numbered word lines 15 (e.g. the first word lines 151) are alternately arranged with the even-numbered word lines 15 (e.g. the second word lines 152). Any odd-numbered word line 15 and the even-numbered word line 15 that are adjacent are arranged in an at least partially staggered manner along the first direction D1. Projections of any two adjacent ones of the odd-numbered word lines 15 overlap on the plane formed jointly by the second direction D2 and the direction D3 perpendicular to the top surface of the substrate, which means projections of any two adjacent ones of the odd-numbered word lines 15 are aligned along the first direction D1. Projections of any two adjacent ones of the even-numbered word lines 15 overlap on the plane formed jointly by the second direction D2 and the direction D3 perpendicular to the top surface of the substrate, which means projections of any two adjacent ones of the even-numbered word lines 15 are aligned along the first direction D1; the examiner notes that the tiers are interpreted as the odd and even word lines in plane).
Per claim 6, Lui discloses: wherein an additional multi-plane word line of a plurality of multi-plane word lines comprises: a third word line of the first plane having a third index, and a fourth word line of the second plane having a fourth index that is offset from the third index by an amount that is different from an offset from the first index to the second index (fig. 2, ¶0032; long the first direction D1, the plurality of word lines are sequentially ordered. That is, in the first direction D1, the odd-numbered word lines 15 (e.g. the first word lines 151) are alternately arranged with the even-numbered word lines 15 (e.g. the second word lines 152). Any odd-numbered word line 15 and the even-numbered word line 15 that are adjacent are arranged in an at least partially staggered manner along the first direction D1. Projections of any two adjacent ones of the odd-numbered word lines 15 overlap on the plane formed jointly by the second direction D2 and the direction D3 perpendicular to the top surface of the substrate, which means projections of any two adjacent ones of the odd-numbered word lines 15 are aligned along the first direction D1. Projections of any two adjacent ones of the even-numbered word lines 15 overlap on the plane formed jointly by the second direction D2 and the direction D3 perpendicular to the top surface of the substrate, which means projections of any two adjacent ones of the even-numbered word lines 15 are aligned along the first direction D1; the examiner notes that the tiers are interpreted as the odd and even word lines in plane).
Claims 11-15 are the system claim corresponding to the method claims 1-3 and are rejected under the same reasons set forth in connection with the rejection of claims 1-3.
Claims 16-17 and 22 are the system claim corresponding to the method claims 1-3 and are rejected under the same reasons set forth in connection with the rejection of claims 1-3.
Claim(s) 7 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu and Erez in view of Ryu et al. 20210193245 herein Ryu.
Per claim 7, Liu and Erez do not specifically disclose: wherein performing the read operation comprises: applying an error correction operation to correct one or more word lines of the multi-plane word line.
However, Ryu discloses: wherein performing the read operation comprises: applying an error correction operation to correct one or more word lines of the multi-plane word line (¶0148; in a third mode of the read operation, the second ECC engine 500 reads the main data MD and the second parity data PRT2 from the target page coupled to the word-line WLj in the memory cell array 400, performs an ECC decoding on the main data MD and the second parity data PRT2 using the second ECC to correct a multi-bit bit error in the main data MD ).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Liu, Erez and Ryu because Ryu increases error correction capabilities (¶0006).
Per claim 19, Ryu discloses: enable reliability address coding based at least in part on one or more metrics associated with an expected error rate of data stored on the block; and identify whether a condition is met (¶0010; in a read operation of the semiconductor memory device perform an ECC decoding on the main data read from the normal cell region using a second ECC, based on the first parity data read from the parity cell region to correct a first type of error in the main data, wherein the second ECC has a parity check matrix which is the same as a parity check matrix of the first ECC; the examiner notes that the claim does not set forth what the condition is and how it relates to the reliability coding).
Allowable Subject Matter
Claims 4-5, 8-10, 18 and 20-21 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Remark
Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BABOUCARR FAAL whose telephone number is (571)270-5073. The examiner can normally be reached M-F 8:30-5:30 EST.
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BABOUCARR . FAAL
Primary Examiner
Art Unit 2138
/BABOUCARR FAAL/Primary Examiner, Art Unit 2138
Prosecution Insights