DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 9-11 are objected to because of the following informalities:
Claim 9 appears to recite what the Examiner assumes is a grammatical error. In claim 9, the phrase “wherein the there is no enhanced ...” should read “wherein there is no enhanced ...”.
Claims 10 and 11 appear to recite what the Examiner assumes is a typographical error. In claims 10 and 11, the phrase “the enhance body layer” should read “the enhanced body layer”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2 and 9-14 recite the limitation “the device” in lines 4-6 in claim 2 on page 2, 19-21 in claim 9 on page 3, 1 in claim 10 on page 4, 4 in claim 11 on page 4, 6 in claim 12 on page 4, 7 in claim 13 on page 4, 8 in claim 14 on page 4. There is insufficient antecedent basis for this limitation in the claim.
For purposes of examination, the Examiner will interpret “the device” as “the semiconductor, insulated trench gate switching device”.
Claims 1, 5, 8, and 12 recite the limitation "the trenches" in lines 16 and 18 in claim 1 on page 1, 14 and 15 in claim 5 on page 2, 7 and 10 in claim 8 on page 3, and 6 in claim 12 on page 4. There is insufficient antecedent basis for this limitation in the claim.
For purposes of examination, the Examiner will interpret “the trenches” as “the first trenches”
Claims 1 and 8 recite the limitation "the gates" in lines 22 and 23 on page 1 and 1 on page 2 in claim 1 and 14-16 on page 3 in claim 8. There is insufficient antecedent basis for this limitation in the claim.
For purposes of examination, the Examiner will interpret “the gates” as “the vertical gates”
The balance of claims are rejected for being dependent upon an already rejected claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-8, and 10-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Moore (US 20220238698 A1).
Claim 1, Moore discloses a method of forming a semiconductor, insulated trench gate switching device (vertical switch in Annotated Fig. 15, [0109]) comprising:
forming a first semiconductor layer (n- drift layer 106, hereinafter first semiconductor layer 106, [0109], Annotated Fig. 15) of a first conductivity type (first semiconductor layer 106 is n-type, [0109], Annotated Fig. 15) over a substrate (substrate 104, [0097], Annotated Fig. 15) to form a drift layer (first semiconductor layer 106 is a n- drift layer, [0109]; first semiconductor layer 106 is formed, [0109]);
epitaxially growing a second semiconductor layer (p-body region 26, hereinafter second semiconductor layer 26, is formed epitaxially [0081]; second semiconductor layer 26, is formed, [0109], Annotated Fig. 15) of a second conductivity type (second semiconductor layer 26 is p-type, [0081], Annotated Fig. 15) on the first semiconductor layer 106 (second semiconductor layer 26 is on the first semiconductor layer 106, Annotated Fig. 15) to form a first body layer (second semiconductor layer 26 is a p-body region and may be a continuous layer, [0081], Annotated Fig. 15), the second semiconductor layer 26 having a first dopant concentration (second semiconductor layer 26 may have a uniform doping concentration, [0112]);
forming a third semiconductor layer of the second conductivity type (p+ body contact regions 44, hereinafter third semiconductor layer 44, is p-type, [0111]) over the second semiconductor layer 26 (third semiconductor layer 44 is on the second semiconductor layer 26, Annotated Fig. 15) to form an enhanced body layer (second semiconductor layer 26 can be used in combination with a more heavily doped third semiconductor layer 44, [0113]), the third semiconductor layer 44 having a second dopant concentration higher than the first dopant concentration (second semiconductor layer 26 can be used in combination with a more heavily doped third semiconductor layer 44, [0113]);
forming a fourth semiconductor layer of the first conductivity type (n+ source layer 46, hereinafter fourth semiconductor layer 46, is n-type, [0083], Fig. 5) over the third semiconductor layer 44 (n-type dopants are implanted and diffused into the top surface of the third semiconductor layer 44 to form fourth semiconductor layer 46, [0083], Fig. 5) to form source regions (the fourth semiconductor layer 46 will later be segmented by the trenches to form the source regions 20, [0083] Fig. 5; source regions 20, [0113], Annotated Fig. 15);
forming an array of first trenches (trenches 52, hereinafter first trenches 52, extend into the second semiconductor layer 26, [0085], Annotated Fig. 7) extending at least into the second semiconductor layer 26, the first trenches 52 having sidewalls (sidewalls in Annotated Fig. 7);
forming a dielectric layer on the sidewalls (gate oxide 54, hereinafter dielectric layer 54, is formed on the exposed surfaces in the first trenches 52, [0086], Annotated Fig. 8; dielectric layer 54, Annotated Fig. 15);
depositing a first conductive material in the first trenches 52 abutting the dielectric layer 54 to form vertical gates (doped polysilicon 16 is deposited to fill the first trenches 52, [0087]; vertical gates, Annotated Figs. 8 and 15);
forming a first electrode contacting the source regions 20 (a layer of metal is deposited to define the source metal 60, hereinafter first electrode 60, [0090]; first electrode 60, Annotated Fig. 15); and
forming a second electrode (anode electrode 103, hereinafter second electrode 103, [0109], Annotated Fig. 15) contacting the substrate 104 (second electrode 103 is formed on the bottom of substrate 104, [0079]),
wherein a top portion of the vertical gates (top portion in Annotated Fig. 15) abuts the enhanced body layer (top portion abuts the third semiconductor layer 44, which is the enhanced body layer, Annotated Fig. 15), and a bottom portion of the vertical gates (bottom portion in Annotated Fig. 15) abuts the first body layer (bottom portion abuts the second semiconductor layer 26, which is the first body layer, Annotated Fig. 15), such that a threshold voltage applied to the vertical gates inverts the first body layer and the enhanced body layer to form a vertical conductive path for current flow (voltage threshold VT when applied inverts the first body layer and the enhanced body layer to form a vertical conductive path for current flow, [0113]).
PNG
media_image1.png
496
818
media_image1.png
Greyscale
Moore Annotated Figure 15
PNG
media_image2.png
222
344
media_image2.png
Greyscale
Moore Figure 5
PNG
media_image3.png
250
338
media_image3.png
Greyscale
Moore Annotated Figure 7
PNG
media_image4.png
244
366
media_image4.png
Greyscale
Moore Annotated Figure 8
Claim 3, Moore discloses the method of claim 1 wherein forming the enhanced body layer comprises implanting dopants of the second conductivity type into a surface of the first body layer and diffusing the dopants (p-type dopants are implanted and diffused into the top surface of the second semiconductor layer 26 to form third semiconductor layer 44, [0082], Fig. 5).
Claim 4, Moore discloses the method of claim 1 wherein forming the enhanced body layer comprises varying a dopant concentration while epitaxially growing the second semiconductor layer 26 (the doping of the second semiconductor layer 26 may be during the epitaxial growth [0081]; It is possible to grow a second semiconductor layer with a vertical variation in dopant atom concentration throughout the epitaxial layer, [0112]).
Claim 5, Moore discloses the method of claim 1 wherein forming the first trenches 52 comprises terminating the first trenches within the first body layer (trenches 52, hereinafter first trenches 52, terminate within the second semiconductor layer 26, [0085], Annotated Fig. 7).
Claim 6, Moore discloses the method of claim 1 wherein the substrate 104 is of the second conductivity type (substrate 104 is a p++ substrate, [0109]).
Claim 7, Moore discloses the method of claim 1 wherein the method forms a npnp layered device that is switched on and off by applying voltage to the vertical gates (a vertical npnp structure is formed where a sufficiently positive gate voltage initiates the turn on of the npnp structure, [0109]).
Claim 8, Moore discloses a semiconductor, insulated trench gate switching device (vertical switch in Annotated Fig. 15, [0109]) comprising:
a first semiconductor layer (n- drift layer 106, hereinafter first semiconductor layer 106, [0109], Annotated Fig. 15) of a first conductivity type (first semiconductor layer 106 is n-type, [0109], Annotated Fig. 15) over a substrate (substrate 104, [0097], Annotated Fig. 15), the first semiconductor layer 106 being a drift layer (first semiconductor layer 106 is a n- drift layer, [0109]);
an epitaxially grown second semiconductor layer (p-body region 26, hereinafter second semiconductor layer 26, is formed epitaxially [0081]; second semiconductor layer 26, [0109], Annotated Fig. 15) of a second conductivity type (second semiconductor layer 26 is p-type, [0081], Annotated Fig. 15) on the first semiconductor layer 106 (second semiconductor layer 26 is on the first semiconductor layer 106, Annotated Fig. 15), the second semiconductor layer 26 being a first body layer (second semiconductor layer 26 is a p-body region and may be a continuous layer, [0081], Annotated Fig. 15), the second semiconductor layer 26 having a first dopant concentration (second semiconductor layer 26 may have a uniform doping concentration, [0112]);
a third semiconductor layer of the second conductivity type (p+ body contact regions 44, hereinafter third semiconductor layer 44, is p-type, [0111]) over the second semiconductor layer 26 (third semiconductor layer 44 is on the second semiconductor layer 26, Annotated Fig. 15), the third semiconductor layer 44 being an enhanced body layer (second semiconductor layer 26 can be used in combination with a more heavily doped third semiconductor layer 44, [0113]), the third semiconductor layer 44 having a second dopant concentration higher than the first dopant concentration (second semiconductor layer 26 can be used in combination with a more heavily doped third semiconductor layer 44, [0113]);
a fourth semiconductor layer of the first conductivity type (n+ source layer 46, hereinafter fourth semiconductor layer 46, is n-type, [0083], Fig. 5) over the third semiconductor layer 44 (n-type dopants are implanted and diffused into the top surface of the third semiconductor layer 44 to form fourth semiconductor layer 46, [0083], Fig. 5), the fourth semiconductor layer 46 being source regions (the fourth semiconductor layer 46 will later be segmented by the trenches to form the source regions 20, [0083] Fig. 5; source regions 20, [0113], Annotated Fig. 15);
an array of first trenches (trenches 52, hereinafter first trenches 52, extend into the second semiconductor layer 26, [0085], Annotated Fig. 7) in at least the second semiconductor layer 26, the first trenches 52 having sidewalls (sidewalls in Annotated Fig. 7);
a dielectric layer on the sidewalls (gate oxide 54, hereinafter dielectric layer 54, is formed on the exposed surfaces in the first trenches 52, [0086], Annotated Fig. 8; dielectric layer 54, Annotated Fig. 15);
a first conductive material in the first trenches 52 abutting the dielectric layer 54 forming vertical gates (doped polysilicon 16 is deposited to fill the first trenches 52, [0087]; vertical gates, Annotated Figs. 8 and 15);
a first electrode contacting the source regions 20 (a layer of metal is deposited to define the source metal 60, hereinafter first electrode 60, [0090]; first electrode 60, Annotated Fig. 15); and
a second electrode (anode electrode 103, hereinafter second electrode 103, [0109], Annotated Fig. 15) contacting the substrate 104 (second electrode 103 is formed on the bottom of substrate 104, [0079]),
wherein a top portion of the vertical gates (top portion in Annotated Fig. 15) abuts the enhanced body layer (top portion abuts the third semiconductor layer 44, which is the enhanced body layer, Annotated Fig. 15), and a bottom portion of the vertical gates (bottom portion in Annotated Fig. 15) abuts the first body layer (bottom portion abuts the second semiconductor layer 26, which is the first body layer, Annotated Fig. 15), such that a threshold voltage applied to the vertical gates inverts the first body layer and the enhanced body layer to form a vertical conductive path for current flow (voltage threshold VT when applied inverts the first body layer and the enhanced body layer to form a vertical conductive path for current flow, [0113]).
Claim 10, Moore discloses the semiconductor, insulated trench gate switching device of claim 8 wherein the enhanced body layer is formed by implanting dopants of the second conductivity type into a surface of the first body layer and diffusing the dopants (p-type dopants are implanted and diffused into the top surface of the second semiconductor layer 26 to form third semiconductor layer 44, [0082], Fig. 5).
Claim 11, Moore discloses the semiconductor, insulated trench gate switching device of claim 8 wherein the enhanced body layer is formed by varying a dopant concentration while epitaxially growing the second semiconductor layer 26 (the doping of the second semiconductor layer 26 may be during the epitaxial growth [0081]; It is possible to grow a second semiconductor layer with a vertical variation in dopant atom concentration throughout the epitaxial layer, [0112]).
Claim 12, Moore discloses the semiconductor, insulated trench gate switching device of claim 8 wherein the first trenches 52 terminate within the first body layer (trenches 52, hereinafter first trenches 52, terminate within the second semiconductor layer 26, [0085], Annotated Fig. 7).
Claim 13, Moore discloses the semiconductor, insulated trench gate switching device of claim 8 wherein the substrate 104 is of the second conductivity type (substrate 104 is a p++ substrate, [0109]).
Claim 14, Moore discloses the semiconductor, insulated trench gate switching device of claim 8 wherein the semiconductor, insulated trench gate switching device is a npnp layered device that is switched on and off by applying voltage to the vertical gates (a vertical npnp structure is formed where a sufficiently positive gate voltage initiates the turn on of the npnp structure, [0109]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Moore.
Claim 2, Moore discloses the method of claim 1 wherein the first trenches 52 and source regions 20 are formed in an active area (active area in Annotated Fig. 15) of the semiconductor, insulated trench gate switching device that conducts current (active area encloses the first trenches 52, source regions 20, electrodes, vertical gates, and doped regions and is therefore the area in the semiconductor, insulated trench gate switching device that conducts current, Annotated Fig. 15), the semiconductor, insulated trench gate switching device also comprising:
a termination area (termination area in Annotated Fig. 15) of the semiconductor, insulated trench gate switching device between the active area and outer edges of the semiconductor, insulated trench gate switching device (termination area is in between the active area and outer edges as shown in Annotated Fig. 15), wherein there is no enhanced body layer or source region in the termination area (third semiconductor layer 44 and source region 20 are not enclosed in the termination area, Annotated Fig. 15).
Moore does not explicitly disclose the method of claim 1 also comprising:
forming second trenches in a termination area of the semiconductor, insulated trench gate switching device between the active area and outer edges of the semiconductor, insulated trench gate switching device, the second trenches being filled with the first conductive material and extending into the first semiconductor layer 106, wherein there is no enhanced body layer or source region 20 in the termination area.
However, in a different method embodiment, Moore discloses:
forming second trenches (deep trenches 212, hereinafter second trenches 212, in the termination area, [0120], Annotated Fig. 20) in a termination area (termination area in Annotated Figs. 20 and 21) of a semiconductor, insulated trench gate switching device (semiconductor, insulated trench gate switching device shown in Annotated Fig. 21) between the active area (active area in Annotated Figs. 20 and 21) and outer edges (outer edges in Annotated Figs. 20 and 21) of the semiconductor, insulated trench gate switching device, the second trenches 212 being filled with the first conductive material (polysilicon 216 is deposited in the second trenches 212, the same material deposited in the shallow trenches 210, [0121], Annotated Fig. 21; polysilicon 16 is deposited to fill the first trenches 52, [0087]) and extending into the first semiconductor layer 106 (second trenches 212 extend into and terminate in the first semiconductor layer 106, [0120], Annotated Fig. 20), wherein there is no enhanced body layer or source region 20 in the termination area (termination area contains no source region 20 or third semiconductor layer 44, Annotated Figs. 20 and 21).
As disclosed in Moore, the deep trenches in the termination region create isolated p-regions, which act as field limiting rings to spread the electric field to increase the breakdown voltage in the termination region when the device is off. Thus, breakdown will first occur in the active region, which is better equipped to handle the high currents during breakdown due to the proximity of the metal electrodes ([0123]). Therefore, the addition of the deep trenches in the termination region ensures the device can control current flow and operate reliably under both normal and faulty conditions.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by Moore by forming deep trenches in the termination region in the invention disclosed by Moore in order to ensures the device can control current flow and operate reliably under both normal and faulty conditions.
PNG
media_image5.png
242
842
media_image5.png
Greyscale
Moore Annotated Figure 20
PNG
media_image6.png
242
822
media_image6.png
Greyscale
Moore Annotated Figure 21
Claim 9, Moore discloses the semiconductor, insulated trench gate switching device of claim 8 wherein the first trenches 52 and source regions 20 are formed in an active area (active area in Annotated Fig. 15) of the semiconductor, insulated trench gate switching device that conducts current (active area encloses the first trenches 52, source regions 20, electrodes, vertical gates, and doped regions and is therefore the area in the semiconductor, insulated trench gate switching device that conducts current, Annotated Fig. 15), the semiconductor, insulated trench gate switching device also comprising:
Moore does not explicitly disclose the semiconductor, insulated trench gate switching device of claim 8 also comprising:
second trenches in a termination area of the semiconductor, insulated trench gate switching device between the active area and outer edges of the semiconductor, insulated trench gate switching device, the second trenches being filled with the first conductive material and extending into the first semiconductor layer 106, wherein there is no enhanced body layer or source region 20 in the termination area.
However, in a different device embodiment, Moore discloses:
second trenches (deep trenches 212, hereinafter second trenches 212, in the termination area, [0120], Annotated Fig. 20) in a termination area (termination area in Annotated Figs. 20 and 21) of the semiconductor, insulated trench gate switching device (semiconductor, insulated trench gate switching device shown in Annotated Fig. 21) between the active area (active area in Annotated Figs. 20 and 21) and outer edges (outer edges in Annotated Figs. 20 and 21) of the semiconductor, insulated trench gate switching device, the second trenches 212 being filled with the first conductive material (polysilicon 216 is deposited in the second trenches 212, the same material deposited in the shallow trenches 210, [0121], Annotated Fig. 21; polysilicon 16 is deposited to fill the first trenches 52, [0087]) and extending into the first semiconductor layer 106 (second trenches 212 extend into and terminate in the first semiconductor layer 106, [0120], Annotated Fig. 20), wherein there is no enhanced body layer or source region 20 in the termination area (termination area contains no source region 20 or third semiconductor layer 44, Annotated Figs. 20 and 21).
As disclosed in Moore, the deep trenches in the termination region create isolated p-regions, which act as field limiting rings to spread the electric field to increase the breakdown voltage in the termination region when the device is off. Thus, breakdown will first occur in the active region, which is better equipped to handle the high currents during breakdown due to the proximity of the metal electrodes ([0123]). Therefore, the addition of the deep trenches in the termination region ensures the device can control current flow and operate reliably under both normal and faulty conditions.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by Moore by forming deep trenches in the termination region in the invention disclosed by Moore in order to ensures the device can control current flow and operate reliably under both normal and faulty conditions.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
LAU (US 20220399460 A1) discloses a closely related method (method 500, [0054]-[0058]) and a closely related device (MOSFET 100, [0025]-[0062], Fig. 1B) to claims 1 and 8 respectively.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL M VANYO whose telephone number is (571)270-3088. The examiner can normally be reached 9am-12pm, 1pm-4pm EST Monday-Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL M VANYO/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
