DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is a response to the communication filed August 19, 2024.
Claims 1-20 are presented for examination.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following is suggested: --A Memory System Including a Memory Controller for Performing a Post-Package Repair Operation--.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 13 and 17-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Byun, US 2019/0258538 [hereinafter, Byun].
As per claim 13:
Byun teaches a memory device [e.g., memory device 300; figure 12] comprising: a memory cell region including a plurality of normal rows and a plurality of redundancy rows [e.g., storage areas 311-320; see also figure 3 for rows and columns configuration; figure 8 for normal rows and redundant rows]; a repair control circuit configured to selectively activate a plurality of repair control signals according to a result of comparing an input address with a plurality of failure candidate addresses [see para. 0094, “when a defective memory cell occurs in at least one of eh plurality of memory chips 310 …a post package repair on the defective memory cell may be initiated”], and deactivate an activated repair control signal of the plurality of repair control signals according to a mapping release signal [see figure 8, step S25, “terminate post package repair mode”]; a row control circuit configured to select a row corresponding to the input address or a redundancy address, from the memory cell region, according to the activated repair control signal [see para. 0095 and figure 8, steps S23-S24; defective row is mapped to a redundant row]; and a data input and output (input/output) circuit configured to provide, to a memory controller, first data read from the memory cell region, and second data provided from the memory controller to the memory cell region when entering an individual chip mode [see para. 0093 and figure 12, DQGs lines for data input/output; see also para. 0094, the post package repair is performed while the memory device 300 is normally operated; therefore, the defective chip must have been in an individual chip mode during the post package repair operation].
As per claim 17:
The further claimed limitation of “a mode setting circuit configured to generate a repair operation signal indicating a post-package repair operation, or the mapping release signal, by checking some bits of the input address according to a mode setting command, and determine entry into the individual chip mode by checking a logic level of a data input after a set time from an input of a write command according to the repair operation signal” is also implicitly teaches by Byun [see figure 8, steps S20 and S25, entering and exit post package repair mode is disclosed and that the post package repair operation can be perform at the runtime of the memory device; see also para. 0094, the memory device may be able to operate normally, while the post package repair is in progress].
As per claim 18:
Byun also teaches the further claimed limitation of “wherein the row control circuit selects, as the selected row, one of the plurality of normal rows, which corresponds to the input address, and selects one of the plurality of redundancy rows, which corresponds to the redundancy address, according to the activated repair control signal” [see figure 8, steps S23 and S24; defective row and redundant row are selected for mapping/replacing].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Byun in view of Cho, US 2017/0148528 [hereinafter, Cho].
Byun teaches a memory device as mentioned above.
Byun, however, does not explicitly disclose that the repair control circuit stores the input address as one of the plurality of failure candidate addresses in the individual chip mode during a post-package repair operation”.
Cho teaches a similar memory device having a failure log for logging addresses of the failure memory cells [see para. 0025].
It would have been obvious to one having ordinary skill in the art to configure the Byun storage controller for logging the addresses of the failure memory cells, as taught by Cho. It would have been obvious because it is necessary for the system to know which address or addresses requiring post package repair.
As per claim 16:
The claimed limitation of “storing failure addresses” is also rejected for the same reasons as set forth for that in claim 15. The further claimed limitation of “a repair circuit configured to selectively activate the plurality of repair control signals according to the result of comparing the input address with the plurality of candidate addresses, respectively, and deactivate an activated repair control signal of the plurality of repair control signals according to the mapping release signal. Would also follow necessarily when the teaching of Cho is incorporated into that of the Byun in the manner mentioned above. This is because Byun discloses entering and terminating post package repair mode [see figure 8, steps S20 and S25 and that the system need to know which address to be activated for repairing responsive to a correction/repair request].
Claims 5-8 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Byun et al. US 2019/0258538 [hereinafter, Byun] in view of Choi et al., US 2025/0174297 [hereinafter, Choi]
As per claim 5:
Byun teaches a memory system [e.g., figure 12] comprising: a plurality of memory chips [i.e., memory chips 311-318; see also para. 0090], configured to read data from a defective row corresponding to a failure address [see para. 0094, when the defective memory cell occurs …a post package repair on the defective memory cell may be initiated]; and a memory controller [e.g., memory controller 330] configured to receive the read data from the plurality of memory chips [para. 0092, the controller … may read data from the memory chips], target chip selected from the plurality of memory chips performs mapping the failure address to a redundancy address [para. 0095 and figure 8, steps S23-S24; defective row is mapped to a redundant row], see para. 0050, when the post package repair is completed … the defective marking is released]
Byun, however, does not disclose that the post package repair includes the operations of generating, by the controller, the error-corrected data responsive to the received errored read data from the defective row and then writing the error corrected data to the redundant row.
Choi teaches a similar memory system in which performs post package repair and error correction on defective data, in which the controller generates the error corrected data and then stored the error corrected data in the redundant storage location. By doing so the recovery is possible during a runtime of the storage device even if the error that cannot be corrected by ECC are detected in the data read from the memory. Thus, the performance and lifespan of the storage device may be improved [see para. 0159].
It would have been obvious to one having ordinary skill in the art prior to the effective filing date of the claimed invention to configure the Byun storage controller to generate the error-corrected data responsive to the received errored read data from the defective row and then writing the error corrected data to the redundant row, as taught by Byun. The improvement in storage device performance and lifespan would be the motivation for doing so in the Byun system.
As per claim 6:
Both Byun and Choi systems map the defective address to a redundant address, as mentioned above [see Choi, para. 0158 and Byun, figure 8, step S24]. The further claimed limitation of “wherein the memory controller provides, to the plurality of memory chips, a command to instruct a post-package repair operation and the failure address, and controls the target chip to enter an individual chip mode” Would follow necessarily when the teaching of Choi is incorporated into that of the Byun in the above-mentioned manner. This is because both of the Choi and Byun system perform the post package repair operation during the runtime of the storage device (i.e., the target chip must have been entered an individual chip mode) [see again Byun, para. 0052 and Choi, para. 0159].
As per claim 7:
It would have been a common sense not to write the error corrected data into the target chip when there is no error in the read data.
As per claim 8:
The further claimed limitation of “wherein the memory controller communicates with a host using a compute express link (CXL) type interface” would follow necessarily when the Choi teaching is incorporated into that of the Byun. This is because the choi system also use CXL type interface between the host system and the memory sub-system [see para. 0081].
As per claim 14:
Byun teaches a memory device as mentioned in the rejection of claim 13 above.
Byun, however, does not explicitly taches that the second data is an error corrected data generated by the controller.
Choi teaches a similar memory system in which performs post package repair and error correction on defective data, in which the controller generates the error corrected data and then stored the error corrected data in the redundant storage location. By doing so the recovery is possible during a runtime of the storage device even if the error that cannot be corrected by ECC are detected in the data read from the memory. Thus, the performance and lifespan of the storage device may be improved [see para. 0159].
It would have been obvious to one having ordinary skill in the art prior to the effective filing date of the claimed invention to configure the Byun storage controller to generate the error-corrected data responsive to the received errored read data from the defective row and then writing the error corrected data to the redundant row, as taught by Choi. The improvement in storage device performance and lifespan would be the motivation for doing so in the Byun system.
Claim(s) 1-4, 9-12 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Byun in view of Choi as applied to claims 5-8 above, and further in view of Chang et. al., US 2010/0281342 [hereinafter, Chang].
For claim 1 and 9:
The claimed steps are basically carried out by the storage controller and storage sub-system of the claim 5; except for the further claimed limitation of performing the data error correction on a column by column of the defective row.
Chang teaches a similar storage system that perform error correction on data of a page on segment by segment basis [i.e., column by column of a row; see figures 4 and 5].
It would have been obvious to one having ordinary skill in the art prior to the effective filing date of the claimed invention to configure the Byun-Choi system to perform the error correction of the defective row on a column by column basis, as taught by Chang. It would have been obvious because it is no more than a matter of design choice and/or the environment being used [i.e., the configuration of the system being used].
For claims 2-3 and 10:
The further claimed limitations encompass the same scope of that in claim 6. Accordingly, the claims are also rejected for the same reasons as set forth claim 6.
For claims 3 and 11:
The further claimed limitations encompass the same scope of that in claim 7. Accordingly, the claims are also rejected for the same reasons as set forth claim 7.
As for claim 12:
The further claimed limitation encompasses the same scope of that in claim 8. Accordingly, the claim is also rejected for the same reasons as set forth claim 8.
For claims 19-20:
The further claimed limitations are taught by Byun through the operation of terminating post package repair mode [see Byun figure 8, step S25 and figure 11, step S37].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ku et al., US 2024/0079078, teaches storing failure addresses [see para. 0040].
Ayyapureddi, US 2024/0322553, teaches defective rows and columns may be mapped to the redundant rows and columns [see para. 0020].
Park et al., US 2023/0195327, teaches a memory controller for generating corrected data by correcting the read data at a failed address [see para. 0046].
Lim et al., US 2021/0375379, teaches a memory device having normal memory row and spare rows for use in post package repair [see para. 0009].
Ware et al., US 2021/0133061, teaches a memory device having storage cells dedicated for storing failure address information associated with defective storage locations [see para. 0016].
Wieduwilt et al., US 2020/0335175, teaches a memory device with normal memory row and redundant memory rows that may be used in post package repair [see para. 0036].
.
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/HIEP T NGUYEN/ Primary Examiner, Art Unit 2137
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