DETAILED ACTION
This is in response to the application filed on August 19, 2024 in which claims 1 – 21 are presented for examination.
Status of Claims
Claims 1 – 21 are pending, of which claims 1, 10, and 16 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 8/19/2024 and 11/5/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4 – 6, 9 – 11, 13 – 16, 20, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Anderson et al., U.S. Patent 9,092,180 (hereinafter referred to as Anderson) (from Applicant’s IDS) in view of Oberman, “Floating Point Division and Square Root Algorithms and Implementation in the AMD-K7 Microprocessor” (hereinafter referred to as Oberman), further in view of Hammarlund et al., U.S. Patent Application 2003/0126406 (hereinafter referred to as Hammarlund) (from Applicant’s IDS).
Referring to claim 1, Anderson discloses “A method comprising: receiving a first instruction” (Fig. 2b fetching in-flight instructions 202); “storing, in a first register, a first indicator that execution of the first instruction has not yet completed” (column 21 lines 3 – 9 profile data with latency and whether instructions were retired or not. Column 12 lines 56 – 63 latency registers), “wherein the first indicator specifies an expected time for completion of the execution of the first instruction” (column 7 lines 11-13 instructions scheduled according to measured latencies and column 27 lines 20-21 scheduling and predicting the latency of memory access instructions. Column 12 lines 56 – 63 latency registers store a count of cycles, which are later used as an expected time when scheduling and optimizing (as taught at column 24 lines 15 – 24, column 27 lines 16 – 29. As seen at column 28 lines 55 – 64 “it is possible to estimate memory system latency for the load operation”); “executing the first instruction” (Fig. 2b execute the instructions at 240); “receiving a second instruction” (Fig. 2b fetching in-flight instructions 202); “storing, in a second register, a second indicator that execution of the second instruction has not yet completed” (column 21 lines 3 – 9 profile data with latency and whether instructions were retired or not); “and executing the second instruction” (Fig. 2b execute the instructions at 240).
Anderson does not appear to explicitly disclose “determining that the first instruction is not variable latency; determining that the second instruction is variable latency.”
However, Oberman discloses “determining that the first instruction is not variable latency; determining that the second instruction is variable latency” (first paragraph on page 2 teaches division and square root instructions are infrequent, but important. They can degrade system performance. Section 6.2 variable latency of division and square root instructions. It is seen that the infrequent division and square root instructions are of variable latency while other instructions are of not variable latency).
Anderson and Oberman are analogous art because they are from the same field of endeavor, which is instruction latency determinations.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Anderson and Oberman before him or her, to modify the teachings of Anderson to include the teachings of Oberman so that a first instruction is determined to have not variable latency and a second instruction is determined to have variable latency.
The motivation for doing so would have been to provide a means for scheduling and optimizing the instructions for a best performance (as described by Oberman at section 3.3).
Neither Anderson nor Oberman appears to explicitly disclose “wherein the second indicator does not specify an expected time for completion of the execution of the second instruction.”
However, Hammarlund discloses instructions having different and unknown latencies can be accommodated ([0044]). It would have been obvious to combine the teachings of Hammarlund with Anderson/Oberman so that “the second indicator does not specify an expected time for completion of the execution of the second instruction.” In other words, if instruction latency is unknown (as taught by Hammarlund), it would have been obvious to utilize the profile data with latency of Anderson while not specifying an expected completion time.
Anderson, Oberman, and Hammarlund are analogous art because they are from the same field of endeavor, which is instruction latency determinations.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Anderson, Oberman, and Hammarlund before him or her, to modify the teachings of Anderson and Oberman to include the teachings of Hammarlund so that the second indicator does not specify an expected time for completion of the execution of the second instruction.
The motivation for doing so would have been to accommodate both known and unknown latency instructions (as taught by Hammarlund at [0044).
Therefore, it would have been obvious to combine Hammarlund with Anderson and Oberman to obtain the invention as specified in the instant claim.
As per claim 2, Anderson discloses “after the execution of the first instruction, updating the first indicator to specify that execution of the first instruction has completed; and after the execution of the second instruction, updating the second indicator to specify that execution of the second instruction has completed” (column 21 lines 3 – 9 profile data with latency and whether instructions were retired or not).
As per claim 4, Anderson discloses “the second instruction is associated with a
memory access operation” (column 6 lines 48 – 58 the instruction performs a memory operation).
As per claim 5, Oberman discloses “the second instruction is associated with a
mathematical operation” (first paragraph on page 2 teaches division and square root instructions are infrequent, but important. They can degrade system performance. Section 6.2 variable latency of division and square root instructions).
As per claim 6, Oberman discloses “a number of cycles to execute the second
instruction depends on a value of an operand of the second instruction” (4.1.1 operands and rounding errors, determining the minimum number of bits required for the multiplier).
As per claim 9, Anderson discloses “receiving a third instruction; and stalling execution of the third instruction until completion of the execution of the first instruction using the first indicator” (column 2 line 63 - column 3 line 4 stalling instructions, waiting for register dependencies, lack of free physical registers).
Referring to claim 10, Anderson discloses “A device comprising: fetch circuitry configured to receive an instruction; an execution pipeline configured to execute the instruction” (Fig. 2b fetch unit 210 receiving instructions 202 and execution stage 240 with Fig. 2a execution units 241 and ld/st unit 242); “and circuitry coupled to the execution pipeline and the fetch circuitry, wherein the circuitry includes a set of registers” (Column 12 lines 56 – 63 latency registers and Fig. 2b circuitry including counter 510, latencies 283, sample 299. Fig. 3 registers) “and is configured to, based on the instruction:” “cause an indicator to be stored in the set of registers that specifies whether execution of the instruction has completed” (column 21 lines 3 – 9 profile data with latency and whether instructions were retired or not) “such that” “the indicator further specifies an expected time for completion of execution of the instruction” (column 7 lines 11-13 instructions scheduled according to measured latencies and column 27 lines 20-21 scheduling and predicting the latency of memory access instructions. Column 12 lines 56 – 63 latency registers store a count of cycles, which are later used as an expected time when scheduling and optimizing (as taught at column 24 lines 15 – 24, column 27 lines 16 – 29. As seen at column 28 lines 55 – 64 “it is possible to estimate memory system latency for the load operation”).
Anderson does not appear to explicitly disclose circuitry “is configured to, based on the instruction: determine whether the instruction is variable latency” and “when the instruction is not variable latency, the indicator further specifies an expected time for completion of execution of the instruction and, when the instruction is variable latency, the indicator does not specify an expected time for completion of execution of the instruction.”
However, Oberman discloses “determine whether the instruction is variable latency” as well as “when the instruction is not variable latency” and “when the instruction is variable latency” (first paragraph on page 2 teaches division and square root instructions are infrequent, but important. They can degrade system performance. Section 6.2 variable latency of division and square root instructions. It is seen that the infrequent division and square root instructions are of variable latency while other instructions are of not variable latency).
Anderson and Oberman are analogous art because they are from the same field of endeavor, which is instruction latency determinations.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Anderson and Oberman before him or her, to modify the teachings of Anderson to include the teachings of Oberman so that a first instruction is determined to have not variable latency and a second instruction is determined to have variable latency.
The motivation for doing so would have been to provide a means for scheduling and optimizing the instructions for a best performance (as described by Oberman at section 3.3).
Neither Anderson nor Oberman appears to explicitly disclose “when the instruction is not variable latency, the indicator further specifies an expected time for completion of execution of the instruction and, when the instruction is variable latency, the indicator does not specify an expected time for completion of execution of the instruction.”
However, Hammarlund discloses instructions having different and unknown latencies can be accommodated ([0044]). It would have been obvious to combine the teachings of Hammarlund with Anderson/Oberman so that “when the instruction is not variable latency, the indicator further specifies an expected time for completion of execution of the instruction and, when the instruction is variable latency, the indicator does not specify an expected time for completion of execution of the instruction.” In other words, if instruction latency is unknown (as taught by Hammarlund), it would have been obvious to utilize the profile data with latency of Anderson while not specifying an expected completion time.
Anderson, Oberman, and Hammarlund are analogous art because they are from the same field of endeavor, which is instruction latency determinations.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Anderson, Oberman, and Hammarlund before him or her, to modify the teachings of Anderson and Oberman to include the teachings of Hammarlund so that the second indicator does not specify an expected time for completion of the execution of the second instruction.
The motivation for doing so would have been to accommodate both known and unknown latency instructions (as taught by Hammarlund at [0044).
Therefore, it would have been obvious to combine Hammarlund with Anderson and Oberman to obtain the invention as specified in the instant claim.
Note, claim 11 recites the corresponding limitations of claim 2. Therefore, the rejection of claim 2 applies to claim 11.
Note, claim 13 recites the corresponding limitations of claim 4. Therefore, the rejection of claim 4 applies to claim 13.
Note, claim 14 recites the corresponding limitations of claim 5. Therefore, the rejection of claim 5 applies to claim 14.
Note, claim 15 recites the corresponding limitations of claim 6. Therefore, the rejection of claim 6 applies to claim 15.
Referring to claim 16, claim 1 recites the corresponding limitations as that of claim 16. Therefore, the rejection of claim 1 applies to claim 16.
Further, Oberman discloses “A device comprising: a first register configured to store an intermediate result of an instruction” (sections 3.2.2, 3.2.4, 3.3 intermediate results and “storage registers required to hold intermediate results”).
As above, Anderson, Oberman, and Hammarlund teach the remaining corresponding claim limitations as seen in the features of claim 10 above.
Note, claim 20 recites the corresponding limitations of claim 4. Therefore, the rejection of claim 4 applies to claim 20.
Note, claim 21 recites the corresponding limitations of claim 5. Therefore, the rejection of claim 5 applies to claim 21.
Allowable Subject Matter
Claims 3, 7, 8, 12, and 17 – 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patents 5802386, 7502912, 8214624, 9552196, 12321733 describe predicting instruction latencies.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN G SNYDER whose telephone number is (571)270-1971. The examiner can normally be reached on M-F 8:00am-4:30pm (flexible).
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/STEVEN G SNYDER/Primary Examiner, Art Unit 2184
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