Prosecution Insights
Last updated: October 25, 2026
Application No. 18/808,342

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Non-Final OA §DP
Filed
Aug 19, 2024
Priority
Mar 05, 2021 — JP 2021-035045 +1 more
Examiner
RAHMAN, KHATIB A
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Kabushiki Kaisha Toshiba
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
436 granted / 478 resolved
+23.2% vs TC avg
Minimal +5% lift
Without
With
+4.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
26 currently pending
Career history
501
Total Applications
across all art units

Statute-Specific Performance

§103
49.0%
+9.0% vs TC avg
§102
27.3%
-12.7% vs TC avg
§112
18.6%
-21.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 478 resolved cases

Office Action

§DP
DETAILED ACTION Notice of Pre-AIA or AIA Status Double Patenting A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957). The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l) (1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Claim 1 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1 of US patent US 12,094,968 B2 (hereinafter called ‘968) in view of Seimieniec (US 2016/0322489 A1) Pertaining to claim 1, all of the limitations of claim 1 are found in claim 1 of ‘968 except the control electrode provided between the semiconductor part and the second electrode, the semiconductor part including a trench having a depth enough to extend into the first semiconductor layer from the front surface side, the control electrode being provided inside the trench, the third electrode provided inside the trench and the fourth insulating film extending along an inner surface of the trench But Seimieniec teaches, PNG media_image1.png 664 742 media_image1.png Greyscale a control electrode (gate electrode 155, para [0046], see FIG. 3B above) provided between a semiconductor part (including n type 121, 110 & 115, para [0038] )and a second electrode (310, para [0067]), the semiconductor part including a trench (5) having a depth enough to extend into a first semiconductor layer (121) from the front surface side (as seen) , the control electrode being provided inside the trench (as seen), a third electrode (165, para [0049]) provided inside the trench a fourth insulating film (161a, para [0049]) extending along an inner surface of the trench It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify claim 1 of ‘968, such that the control electrode provided between the semiconductor part and the second electrode, the semiconductor part including a trench having a depth enough to extend into the first semiconductor layer from the front surface side, the control electrode being provided inside the trench, the third electrode provided inside the trench and the fourth insulating film extending along an inner surface of the trench, according to teaching of Seimieniec above, in order to form an insulted gate bipolar transistor (IGBT), as thought by Seimieniec(see para [0029]). Instant Application US 12,094,968 B2 1. A semiconductor device, comprising: a semiconductor part including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a third semiconductor layer of the first conductivity type; a first electrode provided on a back surface of the semiconductor part; a second electrode provided at a front surface side of the semiconductor part, the first semiconductor layer extending between the first electrode and the second electrode, the second semiconductor layer being provided between the first semiconductor layer and the second electrode, the third semiconductor layer being provided between the second semiconductor layer and the second electrode; a control electrode provided between the semiconductor part and the second electrode, the semiconductor part including a trench having a depth enough to extend into the first semiconductor layer from the front surface side, the control electrode being provided inside the trench, the control electrode including a first control portion and a second control portion arranged in a first direction, the first direction being directed along a boundary between the first semiconductor layer and the second semiconductor layer, the control electrode further including a connection portion, the first and second control portions being joined together at the connection portion; a first insulating film provided between the second semiconductor layer of the semiconductor part and the first control portion or the second control portion of the control electrode; a second insulating film provided between the first control portion and the second control portion of the control electrode, the second insulating film covering the first and second control portions; a third insulating film including first to third portions, the first portion being provided between the first control portion and the second electrode, the second portion being provided between the second control portion and the second electrode, and the third portion being provided between the first portion and the second portion, the third portion extending between the first control portion and the second control portion, the second insulating film being provided between the control electrode and the third insulating film; a third electrode provided inside the trench, the third electrode extending in a second direction, the second direction being directed from the first electrode toward the second electrode, the third electrode being provided between the first electrode and the third portion of the third insulating film and between the first electrode and the connection portion of the control electrode; a fourth insulating film provided between the first semiconductor layer and the third electrode, the fourth insulating film extending along an inner surface of the trench, the first and second control portions of the control electrode being provided between the second electrode and the fourth insulating film; a fifth insulating film provided between the third electrode and the third portion of the third insulating film and between the third electrode and the connection portion of the control electrode; and a sixth insulating film provided between the fifth insulating film and the connection portion of the control electrode, the sixth insulating film including a different material from a material of the fifth insulating film. 1. A semiconductor device, comprising: a semiconductor part including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a third semiconductor layer of the first conductivity type; a first electrode provided on a back surface of the semiconductor part; a second electrode provided at a front surface side of the semiconductor part, the first semiconductor layer extending between the first electrode and the second electrode, the second semiconductor layer being provided between the first semiconductor layer and the second electrode, the third semiconductor layer being provided between the second semiconductor layer and the second electrode; a control electrode inside the semiconductor part, the control electrode including a first control portion and a second control portion arranged in a first direction, the first direction being directed along a boundary between the first electrode and the semiconductor part, the control electrode further including a connection portion, the first and second control portions being joined together at the connection portion; a first insulating film provided between the second semiconductor layer of the semiconductor part and the first control portion or the second control portion of the control electrode; a second insulating film provided between the first control portion and the second control portion of the control electrode, the second insulating film covering the first and second control portions; a third insulating film including first to third portions, the first portion being provided between the first control portion and the second electrode, the second portion being provided between the second control portion and the second electrode, and the third portion being provided between the first portion and the second portion, the third portion extending between the first control portion and the second control portion, the second insulating film being provided between the control electrode and the third insulating film; a third electrode extending in a second direction, the second direction being directed from the first electrode toward the second electrode, the third electrode being provided between the first electrode and the third portion of the third insulating film and between the first electrode and the connection portion of the control electrode; a fourth insulating film provided between the first semiconductor layer and the third electrode, the first and second control portions of the control electrode being provided between the second electrode and the fourth insulating film; a fifth insulating film provided between the third electrode and the third portion of the third insulating film and between the third electrode and the connection portion of the control electrode; and a sixth insulating film provided between the fifth insulating film and the connection portion of the control electrode, the sixth insulating film including a different material from a material of the fifth insulating film. Allowable Subject Matter Claim 1 would be allowable if rewritten to overcome the double patenting rejection(s), set forth in this Office action. With respect to claim 1, the prior art of record does not appear to teach, suggest, or provide motivation for combination to following limitation: “and a sixth insulating film provided between the fifth insulating film and the connection portion of the control electrode, the sixth insulating film including a different material from a material of the fifth insulating film” Regarding Claim 1, Seimieniec (US 2016/0322489 A1) teaches, PNG media_image1.png 664 742 media_image1.png Greyscale A semiconductor device (Fig. 3B), comprising: a semiconductor part including a first semiconductor layer of a first conductivity type (n type 121, para [0038]), a second semiconductor layer of a second conductivity type (p type 110, para [0038]), and a third semiconductor layer of the first conductivity type (n type 115, para [0038]); a first electrode (320, para [0033]) provided on a back surface of the semiconductor part; a second electrode (310, para [0033]) provided at a front surface side of the semiconductor part, the first semiconductor layer (121) extending between the first electrode (320) and the second electrode (310) (as seen in FIG. 3B above), the second semiconductor layer (110) being provided between the first semiconductor layer (121) and the second electrode (310) , the third semiconductor layer (115) being provided between the second semiconductor layer (110) and the second electrode(310) (as seen); a control electrode (155, para [0046]) provided between the semiconductor part and the second electrode (as seen), the semiconductor part including a trench (5) having a depth enough to extend into the first semiconductor layer from the front surface side (as seen) , the control electrode being provided inside the trench (as seen), the control electrode including a first control portion (as marked) and a second control portion (as marked) arranged in a first direction, the first direction being directed along a boundary between the first semiconductor layer and the second semiconductor layer, the control electrode further including a connection portion (as marked), the first and second control portions being joined together at the connection portion (as seen); a first insulating film (151 as marked, para [0046]) provided between the second semiconductor layer of the semiconductor part and the first control portion or the second control portion of the control electrode (as seen); a second insulating film (145, para [0074]) provided between the first control portion and the second control portion of the control electrode, the second insulating film covering the first and second control portions (covering on a side as seen); a third insulating film (210, para [0070]) including first to third portions (as marked), the first portion being provided between the first control portion and the second electrode (as seen) , the second portion being provided between the second control portion and the second electrode (as seen), and the third portion being provided between the first portion and the second portion (as seen), the third portion extending between the first control portion and the second control portion (as seen), the second insulating film being provided between the control electrode and the third insulating film (in an oblique direction 145 is between 155 and 210); a third electrode (165, para [0049]) provided inside the trench, the third electrode extending in a second direction (vertical direction of FIG. 3B above) , the second direction being directed from the first electrode toward the second electrode (as seen), the third electrode being provided between the first electrode and the third portion of the third insulating film (as seen) and between the first electrode and the connection portion of the control electrode (as seen); a fourth insulating film (161a, para [0049]) provided between the first semiconductor layer and the third electrode (as seen), the fourth insulating film extending along an inner surface of the trench (as seen), the first and second control portions of the control electrode being provided between the second electrode and the fourth insulating film (as seen) , a fifth insulating film (161b, para [0054]) provided between the third electrode and the third portion of the third insulating film (161b in between lower portion of 165 and the third portion of 210 in a side view) and between the third electrode and the connection portion of the control electrode (161b between lower portion of 165 and the connection portion of 155 in a side view). But Seimieniec fails to teach, and a sixth insulating film provided between the fifth insulating film and the connection portion of the control electrode, the sixth insulating film including a different material from a material of the fifth insulating film. The other cited arts, either alone or in combination, fails to cure deficiencies of Seimieniec. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHATIB A RAHMAN whose telephone number is (571)270-0494. The examiner can normally be reached on MON-FRI 8:00 am- 5:00 pm (Arizona). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Steven Loke, can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /K.A.R/Examiner, Art Unit 2818 /STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Aug 19, 2024
Application Filed
Oct 01, 2026
Non-Final Rejection mailed — §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
96%
With Interview (+4.9%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 478 resolved cases by this examiner. Grant probability derived from career allowance rate.

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