Prosecution Insights
Last updated: October 26, 2026
Application No. 18/808,418

GLITCH DETECTION REDUNDANCY

Final Rejection §102
Filed
Aug 19, 2024
Priority
Jun 02, 2022 — continuation of 12/068,050
Examiner
TRAN, ANTHAN
Art Unit
2825
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology Inc.
OA Round
2 (Final)
83%
Grant Probability
Favorable
3-4
OA Rounds
1m
Est. Remaining
85%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
650 granted / 783 resolved
+15.0% vs TC avg
Minimal +2% lift
Without
With
+2.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
17 currently pending
Career history
811
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
52.4%
+12.4% vs TC avg
§102
35.4%
-4.6% vs TC avg
§112
4.5%
-35.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 783 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment Applicant’s response filed on 07/27/2026 in which claims 1, 3-4, 9, 16 were amended, claims 2, 10, 18 were canceled, and claims 21-22 are added has been entered of record. Election/Restrictions Newly submitted claim 22 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: Claim 22 is independent and comprises distinguished limitations of “subsequent to transmitting the indication of the glitch attack to the at least one of the plurality of processing units in addition to the processing unit to which the one of the plurality of glitch detectors corresponds, transmitting, via the at least one processing unit in addition to the processing unit to which the one of the plurality of glitch detectors corresponds, a glitch attack confirmation signal; and wherein the method includes, responsive to detecting the indication of the glitch attack, updating a status register, wherein the status register comprises a plurality of bits corresponding to respective statuses of the plurality of glitch detectors.” Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claim 22 is withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03. To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention. Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 21 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lyon et al. (US Pat. 4,545,013). Regarding claim 21, Fig. 1 and Fig. 2 of Lyon discloses an apparatus, comprising: a plurality of processing units [12, 22a to 22n, Fig. 1]; a plurality of glitch detectors [within 138, Fig. 2] that are configured to detect an indication of a glitch attack on the apparatus [col. 11, lines 28 to 37]; and a connection matrix configured to provide respective signals from the plurality of glitch detectors to at least two of the plurality of processing units [as discloses in col. 11, lines 28 to 37, signals from glitch detectors are sent to the processing units. Therefore, a connection matrix is inherent], wherein the connection matrix is configured to provide respective signals from the plurality of glitch detectors to all of the plurality of processing units [as discloses in col. 11, lines 28 to 37, signals from detectors are applied to the processing units]. Allowable Subject Matter Claims 1, 3-9, 11-17, and 19-20 are allowed. The following is an examiner’s statement of reasons for allowance: Regarding claims 1, 3-9, the prior art does not teach or suggest either alone or in combination an apparatus, comprising: a connection matrix configured to provide respective signals from the plurality of glitch detectors to at least two of the plurality of processing units, wherein the plurality of processing units each include at least one local glitch detector corresponding thereto. Regarding claims 9, 11-15, the prior art does not teach or suggest either alone or in combination a method comprising: subsequent to transmitting the indication of the glitch attack to the at least one of the plurality of processing units in addition to the processing unit to which the one of the plurality of glitch detectors corresponds, transmitting, via the at least one processing unit in addition to the processing unit to which the one of the plurality of glitch detectors corresponds, a glitch attack confirmation signal;wherein detecting the indication of the glitch attack further comprises detecting a deviation in a clock signal, a deviation in a supply voltage signal, or both. Regarding claims 16, 19-20, the prior art does not teach or suggest either alone or in combination an apparatus comprising: responsive to receiving the indication of the detected glitch attack, transmit signaling indicative of the detected glitch attack to the at least two of the plurality of processing units; wherein the plurality of glitch detectors comprises at least one voltage glitch detector and at least one clock signal glitch detector. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANTHAN TRAN/Primary Examiner, Art Unit 2825
Read full office action

Prosecution Timeline

Aug 19, 2024
Application Filed
May 04, 2026
Non-Final Rejection mailed — §102
Jul 21, 2026
Interview Requested
Jul 27, 2026
Response Filed
Jul 27, 2026
Applicant Interview (Telephonic)
Jul 30, 2026
Examiner Interview Summary
Oct 14, 2026
Final Rejection mailed — §102
Oct 15, 2026
Interview Requested

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
83%
Grant Probability
85%
With Interview (+2.4%)
2y 3m (~1m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 783 resolved cases by this examiner. Grant probability derived from career allowance rate.

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