Notice of Pre-AIA or AIA Status
This office action is in response to an Amendment/Request For Reconsideration-After Non-Final Rejection filed 11/21/2025 for application 18/808,523 filed 8/19/2024 that is a continuation of 17/445,479 filed 8/19/2021 by Micron Technology, Inc..
Claims 1, 8, and 15 have been amended. No claims have been cancelled. No claims are new. Thus, claims 1-20 have been examined.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: a sequencer component in claims1-7.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-13, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over
Kim (KIM US 2022/0171570 A1) in view of Shaeffer (Shaeffer et al., US 2013/0227183 A1) and Allen (Allen et al., US 2010/0153593 A1).
Regarding claim 1, Kim teaches A system comprising: one or more memory devices; (Kim [Abstract] discloses the invention is directed to a memory system that includes a memory device, including a plurality of memory dies.) and a sequencer component, (Kim [Abstract] and [0005] discloses a controller that includes a processor and striping engine that receives write commands and output data chunks to the memory device where providing the output data chunks is an example of providing a sequence of data and the controller is an example of a sequencer component.) operatively coupled to the one or more memory devices, (Kim [0003] discloses one or more memory devices, and Kim [0005] and Fig. 1. Kim [Abstract] discloses the controller is coupled to the memory device.)
the sequencer component to perform operations comprising: in response to receiving a die command from a requestor, (Kim [0030] discloses the controller receives requests from the host for read and program (i.e. write) commands.) populating one of: a plurality of read partition command queues or a plurality of write partition command queues (Kim [0075] discloses the controller queues a command to the device. Kim [0098] discloses there may be a write queue that is populated with write commands. ) with a partition of the die command based on a corresponding command type, (Kim [0101] discloses the system may select to route the command to a write queue or a garbage collection queue based on the command type. Consistent with paras [0013] that discloses a partition may be a set of pages and [0032] that discloses a block is a set of pages, a partition of the die command may be one or more pages. Kim [0031] discloses the write commands may contain a logical block address. Thus Kim is populating a write queue with a block of data (one or more pages) based on a determination that the command is a write command.)
wherein each partition of the die command representing a portion of the die command is assigned a partition number associated with their position within the die command after being split, (consistent with para [0040] of the instant application the partition number for a die command may be an address and the partition number associated with their position within the die command may be an address relative to an earlier die command when the original die command is broken into a plurality of sub commands. Kim [0058]-[0060] discloses the write command may be broken down into separate writes using a striping algorithm. The system writes 16 pages of data, by writing to 4 die sequentially, and writing 4 pages within a die to separate planes in the die in parallel. Thus Each of the 16 write commands that make up the stripe are to a die/plane/page address (i.e. partition number) relative to the die/plane/page address of the first request. Kim Fig. 7 and para [0102] discloses the system may receive a single write command and slice the write command into a plurality of host write commands that may be related to one logical address, such as logical address LA1, LA2, and LA3 queued sequentially in host queue HQ. Thus the solution assigns a die/plane/page address (partition number) associated with (relative to) their position within the stripped write die command and each write command represents a portion of the single host die command that has been split.)
wherein a first partition of the die command representing a starting position is assigned a starting partition number (Kim Fig. 7 and para [0102] discloses the system may receive a single write command and slice the write command into a plurality of host write commands that may be related to one logical address, such as logical address LA1, LA2, and LA3 queued sequentially in host queue HQ, where LA1 relates to a first partition (address) representing a starting position assigned to the first write command and is assigned to the starting partition number.)
and each subsequent partition is assigned a respective partition number based on the starting partition number and a total number of partition commands (Kim Fig. 7 and para [0102] discloses the system may receive a single write command and slice the write command into a plurality of host write commands that may be related to one logical address, such as logical address LA1, LA2, and LA3 queued sequentially in host queue HQ. Kim [0105] discloses that the physical addresses associated with the logical addresses may be based on the queued order information and an upper address which determines the chunk. Thus subsequent addresses (partitions numbers) are assigned respective to LA1, and thus are assigned based on the starting partition number of LA1 and a total number of partition commands (three in this case).)
However, Kim does not explicitly teach populating one of: a plurality of read partition command queues or a plurality of write partition command queues … and wherein the plurality of read partition command queues and the plurality of write partition command queues are based on a predetermined mapping sequence and a predetermined partition command queue limit.
Shaeffer, of a similar field of endeavor, further discloses populating one of: a plurality of read partition command queues or a plurality of write partition command queues (Shaeffer Fig. 2 and para [0028] discloses the system may have a plurality of read queues (205-1 and 205-2) and a plurality of write queues (210-1 and 210-2))
… and wherein the plurality of read partition command queues and the plurality of write partition command queues are based on a predetermined mapping sequence (Shaeffer Fig. 2 and para [0028] discloses that each queue may be dedicated to data that corresponds to physical addresses mapped to sub-banks. The sub-banks are static in size, thus suggesting the predetermined mapping sequence would be determined during the initialization of the system.)
Kim and Shaeffer are in a similar field of endeavor as both relate to scheduling requests to a memory. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the multiple queues of Kim that are dedicated to servicing a set of sub-banks that correspond to known physical addresses as taught by Shaeffer into the solution of Kim that queues requests to a plurality of memory devices. Thus combining prior art elements according to known methods to yield predictable results (to simplify the queue logic at the target memory device given queues are dedicated to a particular I/O circuit targeting a particular memory device with the targeted sub-banks, thus the memory device that receives the queued data may assume it is the target of the request.)
The motivation to combine Shaeffer into Kim for claims 2-7 are the same as set forth in claim 1 above.
However, the combination does not explicitly disclose suggests and a predetermined partition command queue limit.
Allen, of a similar field of endeavor, further discloses and a predetermined partition command queue limit. (Examiner notes that consistent with paragraph [0042] of the instant application, the predetermined partition command queue limit may indicate the number of partition commands that can be mapped to each partition command queue. Allen Fig. 4 and paras [0030], and [0043]-[0047] discloses that the queues are based on a predetermined partition command queue limit.).
Kim, Shaeffer, and Allen are in a similar field of endeavor as all relate to managing sending data to memory devices using queues. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the maximum queue length as taught by Allen into the solution of Kim and Schaeffer. Thus combining prior art elements according to known methods (queue data to a memory device using the solution of Kim in view of Shaeffer with the maximum queue length of Allen) to yield predictable results (to balance the cpu usage of the memory controller when inserting data into a queue when using algorithms such as the elevator algorithm that is known to result in greater processing efficiencies at the memory device, but requires additional CPU power to do the insertion. See Allen [0002]).
The motivation to combine Allen into the solution of Kim and Shaeffer for claims 2-7 are the same as set forth in claim 1 above.
Regarding claim 2, The combination of Kim, Shaeffer, and Allen teaches all of the limitations of claim 1 above. Kim further teaches wherein the die command is one of a read command or write command. (Kim [0030] discloses the host may provide read, program (i.e. write), and erase operations of the memory device 150.)
Regarding claim 3, The combination of Kim, Shaeffer, and Allen teaches all of the limitations of claim 1 above. Kim further teaches wherein the predetermined mapping sequence is one of a first mapping sequence, a second mapping sequence, or a third mapping sequence, (Kim [0088] discloses that the destination of the write command is determined based on a stored lookup table, which maps the logical address to the location on the die in which to write the data. See also Kim Fig. 13 and supported paras [0148] and [0156 that suggest the lookup table is created in advance of the queueing of the write command. Examiner notes that this limitation is met when one of the three options (the first, second or third mapping sequence) is disclosed. Examiner has provided prior art for the first option and the second option immediately below.)
wherein the first mapping sequence corresponds to populating one of: the plurality of read partition command queues or the plurality of write partition command queues with a partition of the die command one by one, (Examiner notes that the instant application does not contain an explicit definition for mapping commands one by one in each partition command queue and interprets this claim limitation to indicate that each partition command contains one subcommand from the original command. Kim [0055] discloses that one subpage (i.e. sliced write command or partition command) may include one or more clusters. When the cluster size is 8KB (the same as the page size), Kim Fig. 8A would map cluster 1 to a single sliced write command to plane 1 of die 1, cluster 2 to a single sliced write command to plane 2 of die 1, etc., and they would be processed in consecutive order. Thus this example is an example of mapping the plurality of partition commands one by one in each partition command queue of the plurality of partition command queues in the solution of Kim, Shaeffer, and Allen.)
wherein the second mapping sequence corresponds to populating one of: the plurality of read partition command queues or the plurality of write partition command queues with a partition of the die command two by two, (Kim [0055] discloses that one subpage (i.e. sliced write command or partition command) may include one or more clusters. In the solution shown in figure 8A, the system is mapping clusters 1 and 2 to a single sliced write command to plane 1 of die 1, and clusters 3 and 4 to a single sliced write command to plane 2 of die 1, which is an example of mapping a plurality of partition commands two by two in each partition command queue of the plurality of partition command queues in the solution of Kim, Shaeffer, and Allen.)
and wherein the third mapping sequence corresponds to populating one of: the plurality of read partition command queues or the plurality of write partition command queues with a partition of the die command four by four. (Examiner notes that the claim limitation is met when either the first, second, or third mapping sequences map the partition commands and Examiner has provided prior art for the one by one and two by two sequences in the claim limitations above.)
Regarding claim 4, The combination of Kim, Shaeffer, and Allen teaches all of the limitations of claim 1 above.
Allen further teaches wherein a number of partition commands that can be populated in each read partition command queue of the plurality of read partition command queues is limited to a predetermined partition command queue limit. (Examiner notes that consistent with paragraph [0042] of the instant application, the predetermined partition command queue limit may indicate the number of partition commands that can be mapped to each partition command queue. Allen Fig. 4 and paras [0030], and [0043]-[0047] discloses that the queues are based on a predetermined partition command queue limit. Thus Allen would apply the predetermined partition command queue limit to all of the command queues of the solution of Kim in view of Shaeffer to balance the CPU utilization and memory processing efficiencies of all queues requests, including the plurality of read command queues).
The motivation to combine Allen into the existing solution is the same as set forth in claim 1 above.
Regarding claim 5, The combination of Kim, Shaeffer, and Allen teaches all of the limitations of claim 1 above.
Allen further teaches wherein a number of partition commands that can be populated in each write partition command queue of the plurality of write partition command queues is limited to a predetermined partition command queue limit. Examiner notes that consistent with paragraph [0042] of the instant application, the predetermined partition command queue limit may indicate the number of partition commands that can be mapped to each partition command queue. Allen Fig. 4 and paras [0030], and [0043]-[0047] discloses that the queues are based on a predetermined partition command queue limit. Thus Allen would apply the predetermined partition command queue limit to all of the command queues of the solution of Kim in view of Shaeffer to balance the CPU utilization and memory processing efficiencies of all queues requests, including the plurality of write command queues).
The motivation to combine Allen into the existing solution is the same as set forth in claim 1 above.
Regarding claim 6, The combination of Kim, Shaeffer, and Allen teaches all of the limitations of claim 1 above. Kim further teaches wherein receiving the die command comprises: … and splitting the die command into a plurality of die commands. (Kim [0102] discloses that the Host Interface I/F 132 in the controller as detailed in Kim Fig. 6 may slice the write command into a plurality of host write commands and may queue the sliced host write commands into the host queue HQ where each of the write commands may be a write command for one data chunk and may be related to one logical address. Thus each sliced host write command is an example of a sub-operation of the die command created by splitting the host write command.)
Allen further discloses storing the die command in a die command queue; (Allen Fig. 2 and para [0031] discloses that host requests may be received from host CPU 205 and placed in a queue on the host system, which is an example of a die command queue as it is sending die commands in the solution of Kim, Shaeffer, and Allen.)
The motivation to combine Allen into the existing combination is the same as set forth in claim 1 above.
Regarding claim 8, Kim teaches A method comprising: (Kim [Title] discloses that the inventive concepts are directed to a memory system and method thereof.)
The remainder of claim 8 recites limitations described in claim 1 above and thus is rejected based on the teaching and rationale described in claim 1 above.
Regarding claim 9, The combination of Kim, Shaeffer, and Allen teaches all of the limitations of claim 8 above.
The remainder of claim 9 recites limitations described in claim 2 above and thus is rejected based on the teaching and rationale described in claim 2 above.
Regarding claim 10, The combination of Kim, Shaeffer, and Allen teaches all of the limitations of claim 8 above.
The remainder of claim 10 recites limitations described in claim 3 above and thus is rejected based on the teaching and rationale described in claim 3 above.
Regarding claim 11, The combination of Kim, Shaeffer, and Allen teaches all of the limitations of claim 8 above.
The remainder of claim 11 recites limitations described in claim 4 above and thus is rejected based on the teaching and rationale described in claim 4 above.
Regarding claim 12, The combination of Kim, Shaeffer, and Allen teaches all of the limitations of claim 8 above.
The remainder of claim 12 recites limitations described in claim 5 above and thus is rejected based on the teaching and rationale described in claim 5 above.
Regarding claim 13, The combination of Kim, Shaeffer, and Allen teaches all of the limitations of claim 8 above.
The remainder of claim 13 recites limitations described in claim 6 above and thus is rejected based on the teaching and rationale described in claim 6 above.
Regarding claim 15, Kim teaches A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: (Kim [0173] discloses a processor executing code or instructions. Kim [0026] discloses the solution is integrated into a single semiconductor device. Kim [0024] discloses that the memory system contains nonvolatile storage devices. Thus the solution of Kim is executing store instructions read from non-transitory computer-readable storage medium that cause a processor to perform the inventive steps of the application. )
The remainder of claim 15 recites limitations described in claim 1 above and thus is rejected based on the teaching and rationale described in claim 1 above.
Regarding claim 16, The combination of Kim, Shaeffer, and Allen teaches all of the limitations of claim 15 above.
The remainder of claim 16 recites limitations described in claim 2 above and thus is rejected based on the teaching and rationale described in claim 2 above.
Regarding claim 17, The combination of Kim, Shaeffer, and Allen teaches all of the limitations of claim 15 above.
The remainder of claim 17 recites limitations described in claim 3 above and thus is rejected based on the teaching and rationale described in claim 3 above.
Regarding claim 18, The combination of Kim, Shaeffer, and Allen teaches all of the limitations of claim 15 above.
The remainder of claim 18 recites limitations described in claim 4 above and thus is rejected based on the teaching and rationale described in claim 4 above.
Regarding claim 19, The combination of Kim, Shaeffer, and Allen teaches all of the limitations of claim 15 above.
The remainder of claim 19 recites limitations described in claim 5 above and thus is rejected based on the teaching and rationale described in claim 5 above.
Regarding claim 20, The combination of Kim, Shaeffer, and Allen teaches all of the limitations of claim 15 above.
The remainder of claim 20 recites limitations described in claim 6 above and thus is rejected based on the teaching and rationale described in claim 6 above.
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over
Kim (KIM US 2022/0171570 A1) in view of Shaeffer (Shaeffer et al., US 2013/0227183 A1) and Allen (Allen et al., US 2010/0153593 A1) as detailed in claims 6 and 15 above, and further in view of Frayer (Frayer et. al., US 2015/0364218 A1).
Regarding claim 7, The combination of Kim, Shaeffer, and Allen teaches all of the limitations of claim 6 above.
However, the combination does not explicitly teach wherein the die command is split into five or ten partition commands based on one of the one or more memory devices.
Frayer, of a similar field of endeavor, further teaches wherein the die command is split into five or ten partition commands based on one of the one or more memory devices. (Frayer Figs. 3a-3b and supporting paragraphs [0085]-[0091] discloses there may be 5 die and 2 planes. Thus Fig. 8 of Kim in view of Shaeffer, Allen, and Frayer’s example of 5 die and 2 planes per die would build a strip containing 10 write commands since each of the 5 die and 2 planes operate independently and the stripes are designed to break the sliced write data to maximize the parallel writing of the data.)
Kim, Shaeffer, Allen, and Fayer are all in a similar field of endeavor as all are directed to efficiently writing data to flash memory. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the mapping technique of Kim, Shaeffer, and Allen into a system that contains 5 die and 2 planes as taught by Fayer. Thus combining prior art elements (such as the die/plane configuration described by Fayer into the solution of Kim, Shaeffer, and Allen that breaks large commands into smaller commands) according to known methods (the die plane configuration taught by Fayer) to yield predictable results (support a variety of known hardware configurations such as 5 die and 2 planes as taught by Fayer, into a the solution of Kim, Shaeffer, and Allen that support queueing data to a memory device of a variety of configurations) One would be motivated to do so in order to support a variety of die/plane configurations, including all known configurations of dies and planes.
Regarding claim 14, The combination of Kim, Shaeffer, and Allen teaches all of the limitations of claim 13 above.
The remainder of claim 14 recites limitations described in claim 7 above and thus is rejected based on the teaching and rationale described in claim 7 above,
Response to Remarks
Examiner thanks applicant for their claim amendments and remarks of 11/21/2005. They have been fully considered.
Response to Double Patenting Rejection
Examiner notes the Terminal Disclaimer filed 3/4/2026 resolves the double patent issue.
Response to Rejections under 35 U.S.C. 103
Applicant argues on page 9 of their remarks ‘Kim does not disclose “a first partition of the die command representing a starting position is assigned a starting partition number and each subsequent partition is assigned a respective partition number based on the starting partition number and a total number of partitions commands.”
Examiner respectfully disagrees. As noted in the office action above, consistent with para [0040] of the instant application the partition number for a die command may be an address and the partition number associated with their position within the die command may be an address relative to an earlier die command when the original die command is broken into a plurality of sub commands.
Kim Fig. 7 and para [0102] discloses the system may receive a single write command and slice the write command into a plurality of host write commands that may be related to one logical address, such as logical address LA1, LA2, and LA3 queued sequentially in host queue HQ. Thus Kim may receive a single write command from a host, break it down into three separate write commands going to LA1, LA2, and LA3 as shown below in Fig. 7:
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Kim [0105] further clarifies the stripe may be identified by the lower addresses of the physical addresses of Figure 4 and additionally discloses the striping engine may determine a lower address of the physical address based on the queued order information. Thus the address of LA2 may be a subsequent physical address to LA1, and an physical address of LA3 may be a subsequent address of LA2.
Thus Kim discloses a starting partition number (physical address of LA1) and each subsequent partition is assigned a respective partition number (a physical address greater than the physical address of the previous write chunk) based on the starting partition number and a total number of partitions commands (since the relative physical address depends on how many chunks the data was broken into).
Applicants arguments to independent claims 8 and 15 all rely upon arguments similar to those presented for claim 1 and thus are rejected based on similar rationale as those presented in claim 1 above.
Applicants arguments to dependent claims 2-7, 9-14, and 16-20 all rely upon perceived errors in their respective base claims and thus are addressed in the arguments to the base claims above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JANICE M. GIROUARD whose telephone number is (469)295-9131. The examiner can normally be reached M-F 9:30 - 7:30.
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/JANICE M. GIROUARD/Primary Examiner, Art Unit 2138