Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities: ¶ [0043] and [0045] refer to “neuromorphic synthesizer 120.” However, fig. 1 labels element 120 as “neuromorphic simulator 120.” The names used for element 120 should agree in the specification and the drawings.
Appropriate correction is required.
Claim Objections
Claims 1-9 are objected to because of the following informalities:
Claim 1 recites “A neuromorphic-processing system comprising, comprising,” repeating the word “comprising.” Claims 2-9 are objected to as being dependent on an objected base claim.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 of U.S. Patent No. 11,270,198. Although the claims at issue are not identical, they are not patentably distinct from each other because Claim 1 of the Patent recites all of the limitations of claims 1 and 2 of the present application. Claims 2-8 of the Patent are essentially identical to claims 3-9 of the present application, respectively. Similarly, Claim 9 of the Patent recites all of the limitations of claims 10 and 11 of the present application; and Claims 10-13 of the Patent are essentially identical to claims 12-15 of the present application, respectively. And Claim 14 of the Patent recites all of the limitations of claims 16 and 17 of the present application; and Claims 14-17 of the Patent are essentially identical to claims 17-20 of the present application, respectively.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 7, 9, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Herrero Abelanas et al. (U.S. 2016/0179434, hereinafter “Herrero”).
Regarding Claim 1, Herrero teaches a neuromorphic-processing system (figs. 12a and 12b; ¶ [0095] – [0096] and [0103]) comprising, comprising:
a special-purpose host processor operable as a stand-alone host processor (figs. 12a and 12b, Processor 1200; ¶ [0066] and [0102] - [0103]);
a neuromorphic co-processor including an artificial neural network (figs. 12a and 13, neuromorphic accelerator 1230; ¶ [0095] – [0096], [0103], and [0111]); and
a communications interface between the host processor and the co-processor configured to transmit information therebetween, wherein the co-processor is configured to enhance special-purpose processing of the host processor with the artificial neural network (figs. 12a and 13; ¶ [0102] – [0104]—uncore 1210 is a communication interface).
Regarding Claim 7, Herrero teaches the artificial neural network is disposed in an analog multiplier array of a plurality of two-quadrant multipliers in a memory sector of the neuromorphic-processing system (fig. 13; ¶ [0105]).
Regarding Claim 9, Herrero teaches wherein the host processor and the co-processor are embodied in a single monolithic integrated circuit, a stacked die assembly, a multi-chip module, or separate integrated circuits of separate modules (fig. 6; ¶ [0067] and [0081]), and
wherein neuromorphic-processing system is configured to operate on battery power (¶ [0111]).
Regarding Claim 16, Herrero teaches a method of a neuromorphic-processing system having a special-purpose host processor and a neuromorphic co-processor (figs. 12a and 12b; ¶ [0003], [0095] – [0096], and [0103]), comprising:
enhancing special-purpose processing of the host processor with an artificial neural network of the co-processor (figs. 12a and 13, neuromorphic accelerator 1230; ¶ [0095] – [0096], [0103], and [0111]),
wherein the host processor is operable as a stand-alone host processor (figs. 12a and 12b, Processor 1200; ¶ [0066] and [0102] - [0103]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Herrero, as applied to claim 1, above, in view of Fitz et al. (U.S. 2016/0309267, hereinafter “Fitz”).
Regarding Claims 8 and 20, Herrero teaches wherein synaptic weights of the artificial neural network are stored in firmware of the neuromorphic co-processor (fig. 28; ¶ [0156] – [0158]—the containers are firmware that stores synaptic weights for the ANN),
but does not specifically teach wherein the firmware is configured for cloud-based updates to update the synaptic weights of the artificial neural network.
However, Fitz teaches cloud-based updates to update synaptic weights of an artificial neural network (fig. 1; ¶ [0029]).
All of the claimed elements were known in Herrero and Fitz and could have been combined by known methods with no change in their respective functions. It therefore would have been obvious to a person of ordinary skill in the art at the time of filing of the applicant’s invention to combine the cloud-based updates to synaptic weights of Fitz with the firmware and synaptic weights of Herrero to yield the predictable result of the firmware being configured for cloud-based updates to update the synaptic weights of the artificial neural network. One would be motivated to make this combination for the purpose of enabling the use of more advanced and computation-intensive learning and processing to determine neural network weights than can be performed in the host processor and neuromorphic co-processor.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Herrero in view of Kyles et al. (U.S. 2011/0170560, hereinafter “Kyles”).
Regarding Claim 10, Herrero teaches a neuromorphic processor (figs. 12a and 12b; ¶ [0095] – [0096] and [0103]), comprising:
a plurality of interface circuits (fig. 12a; ¶ [0102]—uncore 1210 comprises a communication bus structure or fabric, which includes a plurality of interface signals),
wherein the signals are received from a communications interface between the neuromorphic processor and a special-purpose host processor(figs. 12a and 13; ¶ [0102] – [0104]); and
a multi-layered artificial neural network configured to receive the signals from the interface circuits, wherein the neuromorphic processor is configured to enhance special-purpose processing of the host processor with the artificial neural network(figs. 12a and 13; ¶ [0102] – [0104]—uncore 1210 is a communication interface).
Herrero does not specifically teach the plurality of interface circuits including a demultiplexer configured to demultiplex serial signals into parallel signals,
wherein the serial signals are received from a serial communications interface; and
the multi-layered artificial neural network configured to receive the parallel signals from the interface circuits.
However, Kyles teaches:
A plurality of interface circuits including a demultiplexer configured to demultiplex serial signals into parallel signals (figs. 3 and 7; ¶ [0041] – [0043] and [0067]),
wherein the serial signals are received from a serial communications interface (fig. 7; ¶ [0028] and [0067]—serial communications input signal S on an interface line); and
a network is configured to receive the parallel signals from the interface circuits (¶ [0032]).
All of the claimed elements were known in Herrero and Kyles and could have been combined by known methods with no change in their respective functions. It therefore would have been obvious to a person of ordinary skill in the art at the time of filing of the applicant’s invention to combine the demultiplexer and serial communications of Kyles with the interface circuits and neural network of Herrero to yield the predictable result of a plurality of interface circuits including a demultiplexer configured to demultiplex serial signals into parallel signals, wherein the serial signals are received from a serial communications interface between the neuromorphic processor and a special-purpose host processor; and a multi-layered artificial neural network configured to receive the parallel signals from the interface circuits, wherein the neuromorphic processor is configured to enhance special-purpose processing of the host processor with the artificial neural network. One would be motivated to make this combination for the purpose of saving chip area and thus reducing costs by reducing the number of data lines required to transmit and receive communication signals.
Allowable Subject Matter
Claims 2-6, 11-15, and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 2, none of the prior art of record teaches “wherein the host processor is a hearing-aid processor configured to transmit frequency elements or signal spectrum information to the co-processor in the form of Fourier transforms over a serial communications interface as the communications interface, and wherein the co-processor further includes a demultiplexer configured to demultiplex serial signals from the serial communications interface into parallel signals for a plurality of inputs of the artificial neural network.” Park (U.S. 2013/0337786) teaches a mobile user device with a processor and audio enhancement coprocessor that alters frequency ranges to improve audio for hearing-impaired users, but does not use a neural network, so the host processor is not configured to transmit frequency elements or signal spectrum information to the co-processor in the form of Fourier transforms over a serial communications interface as the communications interface. Chen, Yu-Jui, et al. (“Neuromorphic pitch based noise reduction for monosyllable hearing aid system application,” IEEE Transactions on Circuits and Systems I: Regular Papers 61.2 (2014): 463-475) teaches a neuromorphic processor and algorithm for noise reduction and speech enhancement in a hearing-aid, but it does not include a host processor configured as in the present claim.
Regarding Claim 11, it recites limitations similar to those of the first limitation of claim 2, and it is similarly not taught by the prior art of record.
Regarding Claim 17, it recites limitations similar to those of claim 2, so it too is not taught by the prior art of record.
Regarding Claims 3-6, 12-15, and 18-19, they contain allowable subject matter by virtue of their dependence on claims 2, 11, and 17, respectively.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. This art includes:
Gutala et al. (U.S. 2019/00120116) teaches a coprocessor/accelerator in a package with memory that comprises programmable logic that can implement a convolutional neural network or other functions
Selinger et al. (U.S. 2018/0307912) teaches a processor coupled to neural network accelerators/video processing units, which can be neuromorphic
Kogawa et al. (U.S. 2016/0173151) teaches a system that demultiplexes a serial signal into parallel signals for video processing
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAL W SCHNEE whose telephone number is (571) 270-1918. The examiner can normally be reached M-F 7:30 a.m. - 6:00 p.m.
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/HAL SCHNEE/Primary Examiner, Art Unit 2129
