Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/28/2026 has been entered.
Response to Arguments
Claims 1, 6, and 13 had been amended, and claim 20 had been added. Claims 1-20 are currently pending.
Applicant’s arguments, filed 08/28/2026, and in light of Applicant’s amendments to claims 1, 6 and 13 have been fully considered but are moot in view of the new rejection (see infra).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 6, 9, 10, 13, 16-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Dawson et al. (US 20180278868 A1, hereinafter “Dawson”), in view of Zuo et al. (US 20210027200 A1, hereinafter “Zuo”).
Regarding claim 1, Dawson teaches a stacked light receiving sensor (Figs. 1&5C: a three stacked structures image sensor) comprising:
a first substrate including a pixel array section, wherein the pixel array section includes a plurality of pixels arranged two-dimensionally in a matrix (Fig. 1, [0039]: top structure 100 is an array of photodetectors or detection pixels);
a second substrate including an analog circuit, wherein the analog circuit is configured to read a pixel signal from the pixel array section (Figs. 1&5C, [0041]: middle structure 200 provides a reconfigurable analog interface between the top structure 100 photodetectors);
and a third substrate including a digital signal processor, wherein the digital signal processor is configured to process, , data based on the pixel signal (Figs. 1&5C, [0044]: bottom structure 300 includes more advanced image processing functions, typically grouped as Tier 1 interconnected functions such as digital registers 310, signal processors 312, configurable logic control 314 and configurable routing periphery 316), and transmit an output to an application processor, the output based on the processing of the data Fig. 1, [0044]: he bottom structure 300, connected to a host computer system 50),
wherein each of the first substrate, the second substrate, and the third substrate is a single semiconductor substrate, the first substrate is stacked on the second substrate, and the second substrate is stacked on the third substrate such that no other substrate is disposed between the second substrate and the third substrate (as illustrated by Figs. 1&5C: each of the top structure 100, the middle structure 200 and the bottom structure 300 is a single structure and are layout out in stacking direction configuration).
Dawson does not teach a computational model and transmit an output to an application processor, the output based on the processing of the data with the computational model.
Zuo discloses a computational model (Figs. 2C,7&11, [0044], [0058]&[0102]-[0105]: an artificial intelligence processing module 120. The artificial intelligence operation may include face recognition, iris recognition, natural language processing, language recognition and the like. Examiner notes that AI processing module provides the physical computing engine to run a neural network computing models) and transmit an output to an application processor, the output based on the processing of the data with the computational model (Figs. 2C,7&11, [0058]&[0102]-[0105]: a sensor module and the artificial intelligence processing module are configured in respective independent chips, and the respective independent chips are connected to each other through a metal wire on a connecting. the sensor module includes at least one sensing unit 710 and an analog signal processing circuit 720. The intelligent sensor device includes a communication apparatus 1150 and an output apparatus 1140 such as a display screen).
Considering the teaching of Yokoyama to form in the bottom structure 300 (claimed “third layer”) a more advanced image processing functions, in view of Zuo’s teaching to integrate the image sensor and the artificial intelligence processing module in a monolithic integration manner or a modular integration manner (Figs. 2&7). The artificial intelligence operation may include face recognition, iris recognition, natural language processing, language recognition and the like ([0044]), in order to provide a self-sufficient and standalone artificial intelligence (AI) devices requiring no support from any backend servers. The resulting combination of which would be predictable by applying the court recognized rational of applying a known technique to a known device (method, or product) ready for improvement to yield predictable results.
Therefore, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a computational model and transmit an output to an application processor, the output based on the processing of the data with the computational model as taught by Zuo into Dawson three stacked structures image sensor. The suggestion/ motivation for doing so would be to enhance intelligence level of sensors and provide an intelligent sensor system architecture that solve a problem of low transmission rate and large transmission delay (Zuo: [0002]&[0008]).
Regarding claim 3, Dawson and Zuo combination teaches the stacked light receiving sensor according to claim 1, wherein the second substrate is coupled to the third substrate with a Through Silicon Via (TSV) (Figs. 1&5C, [0069]: the bottom (digital) structure 300 is attached via a ball array 16 to the middle structure 200 as shown in FIG. 5C to the output channels 17 (Vias) of the middle structure 200.).
Regarding claim 6, claim 6 has been analyzed and rejected with regard to claims 1 and 2 and in accordance with Dawson's further teaching on: signal processing system comprising: a light receiving sensor (Figs. 1&5C, [0039]: The top structure 100 is an array of photodetectors or detection pixels. In examples, the photodetectors are capable of sensing in the ultraviolet to visible (UV-VIS) and to LWIR range of the electromagnetic spectrum, although other spectral bands or narrower bands are possible. The detectors can be APDs (Avalanche Photo Diodes) also.).
Regarding claim 9, claim 9 has been analyzed with regard to claim 3 and is rejected for the same reasons of obviousness as used above.
Regarding claim 10, Dawson and Zuo combination teaches the signal processing system according to claim 6, in addition Dawson discloses further comprising: an imaging apparatus (Figs. 1&5C, [0038]: a multispectral imaging system 1000, DFPA (digital focal plane array), in the form of an integrated circuit of three structures each of which is implemented on a chip.), wherein the application processor is included in the imaging apparatus (Figs. 1&5C, [0044]: The bottom structure 300 of the imaging system 1000, includes more advanced image processing functions).
Regarding claim 13, Method claim 13 is drawn to the method of using the corresponding apparatus claimed in either claim 1 or claim 6. Therefore, method claim 13, corresponds to apparatus claims 1 or 6, is rejected for the same reasons of obviousness as used above.
Regarding claim 16, Method claims 16 is drawn to the method of using the corresponding apparatus claimed in claim 3. Therefore, method claim 16, corresponds to apparatus claim 3, is rejected for the same reasons of obviousness as used above.
Regarding claim 17, Method claim 17 is drawn to the method of using the corresponding apparatus claimed in claim 10. Therefore, method claim 17, corresponds to apparatus claim 10, is rejected for the same reasons of obviousness as used above.
Regarding claim 20, Dawson and Zuo combination teaches the stacked light receiving sensor according to claim 1, in addition Zuo discloses wherein the computational model is a neural network computing model (Figs. 2C,7&11, [0044], [0058]&[0102]-[0105]: The artificial intelligence operation may include face recognition, iris recognition, natural language processing, language recognition and the like. Examiner notes that AI processing module provides the physical computing engine to run a neural network computing models).
Claims 2, 7-8 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over the Dawson and Zuo combination as applied above, in view WANG et al. (US 20190065910 A1, hereinafter “WANG”).
Regarding claim 2, Dawson and Zuo combination teaches the stacked light receiving sensor according to claim 1, except wherein the digital signal processor is further configured to transmit image data to a communication terminal, and the output includes metadata associated with the image data.
However, WANG discloses wherein the digital signal processor is further configured to transmit image data to a communication terminal, and the output includes metadata associated with the image data (Figs. 2&6, [0020]-[0024]: RNN 50 provides a fusion of the content from the metadata extraction database 48 and the CNN output layer 40 to create metadata that contains object classification, prediction of angle (direction) of each classified object, prediction of the location of objects that may not be moving in a linear manner, prediction of the relative velocity of each classified object. the image and the combination of data including object location and object relative velocity from the processor 52 is provided to a display device 62 to display the image).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the digital signal processor is further configured to transmit image data to a communication terminal, and the output includes metadata associated with the image data as taught by WANG into Dawson and Zuo combination. The suggestion/ motivation for doing so would be to increase the detection quality of the images and the speed at which the objects are recognized and classified (WANG: [0004]-[0005]).
Regarding claim 7, claim 7 has been analyzed with regard to claim 2 and is rejected for the same reasons of obviousness as used above.
Regarding claim 8, claim 8 has been analyzed with regard to claim 2 and is rejected for the same reasons of obviousness as used above.
Regarding claims 14 and 15, Method claims 14 and 15 are drawn to the method of using the corresponding apparatus claimed in claim 2. Therefore, method claims 14 and 15, corresponds to apparatus claim 2, are rejected for the same reasons of obviousness as used above.
Claims 4, 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over the Dawson and Zuo combination as applied above, in view of Liu; Xinqiao (US 20190056264 A1, hereinafter “Liu”).
Regarding claim 4, Dawson and Zuo combination teaches the stacked light receiving sensor according to claim 1, in addition Dawson discloses elements of the middle structure 200 includes comparator COMP; and the bottom structure 300 is a digital circuit that provides counters, shift registers (Figs. 1&5C, [0069]). Nevertheless, the combination does not teach wherein the analog circuit includes a comparator and a counter.
However, Liu discloses wherein the analog circuit includes a comparator and a counter (Fig. 4, [0045]-[0047]: a circuit 342 in a second substrate 340 comprising a comparator 410 and a counter 418 in combination function as a single-slope analog-to-digital converter (ADC)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the analog circuit includes a comparator and a counter as taught by Liu into Dawson and Zuo combination. The suggestion/ motivation for doing so would be to produce an integrated analog-to-digital converter (ADC).
Regarding claim 11, Dawson and Zuo combination teaches the signal processing system according to claim 6, in addition Dawson discloses elements of the middle structure 200 includes comparator COMP; and the bottom structure 300 is a digital circuit that provides counters, shift registers (Figs. 1&5C, [0069]). Nevertheless, the combination does not teach wherein the analog circuit includes a comparator and a counter.
However, Liu discloses wherein the analog circuit includes a comparator and a counter (Fig. 4, [0045]-[0047]: a circuit 342 in a second substrate 340 comprising a comparator 410 and a counter 418 in combination function as a single-slope analog-to-digital converter (ADC)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the analog circuit includes a comparator and a counter as taught by Liu into Dawson and Zuo combination. The suggestion/ motivation for doing so would be to produce an integrated analog-to-digital converter (ADC).
Regarding claim 18, Method claim 18 is drawn to the method of using the corresponding apparatus claimed in claim 4. Therefore, method claim 18, corresponds to apparatus claim 4, is rejected for the same reasons of obviousness as used above.
Claims 5, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over the Dawson and Zuo combination as applied above, in view of Himebaugh et al. (US 20160328642 A1, hereinafter “Himebaugh”).
Regarding claim 5, Dawson and Zuo combination teaches the stacked light receiving sensor according to claim 1, except wherein the analog circuit further includes a digital-to-analog converter.
However, Himebaugh discloses wherein the analog circuit further includes a digital-to-analog converter (Fig. 4, [0036]: sensors 102, 104 can include analog sensors 104 and/or digital sensors 106. Outputs of the digital sensors 104 may be sent to the analog neural network 106 via a digital-to-analog converter (DAC) 110.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the analog circuit further includes a digital-to-analog converter as taught by Himebaugh into Dawson and Zuo combination. The suggestion/ motivation for doing so would be to allow transmitting analog neural network via a digital-to-analog converter (DAC) (Himebaugh: [0036]).
Regarding claim 12, Dawson and Zuo combination teaches the signal processing system according to claim 6, except wherein the analog circuit further includes a digital-to-analog converter.
However, Himebaugh discloses wherein the analog circuit further includes a digital-to-analog converter (Fig. 4, [0036]: sensors 102, 104 can include analog sensors 104 and/or digital sensors 106. Outputs of the digital sensors 104 may be sent to the analog neural network 106 via a digital-to-analog converter (DAC) 110.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the analog circuit further includes a digital-to-analog converter as taught by Himebaugh into Dawson and Zuo combination. The suggestion/ motivation for doing so would be to allow transmitting analog neural network via a digital-to-analog converter (DAC) (Himebaugh: [0036]).
Regarding claim 19, Method claim 19 is drawn to the method of using the corresponding apparatus claimed in claim 5. Therefore, method claim 19, corresponds to apparatus claim 5, is rejected for the same reasons of obviousness as used above.
Contact
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/ABDELAAZIZ TISSIRE/ Primary Examiner, Art Unit 2638
