DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant's arguments filed 29 June 2026 have been fully considered but they are not persuasive.
Applicant argues neither Mizuno nor Nishisaka disclose selecting 28 µm ≤ tc ≤ 34 µm together with 0.4 µm ≤ td ≤ 0.5 µm and 0.4 µm ≤ te ≤ 0.5 µm in a body having T < 0.5 mm. Applicant further argues Mizuno's cover-thickness disclosure is an upper-limit teaching tied to a different solution and thus Mizuno does not direct the skilled artisan to geometric co-optimization of cover thickness, dielectric-layer thickness, and internal-electrode thickness. Applicant notes that Mizuno discloses an upper limit of 30 µm but does not teach the claimed lower bound of 28 µm, nor does it provide a reason to select the narrow claimed window while also maintaining td and te within 0.4-0.5 µm.
The examiner finds applicants arguments to be unpersuasive. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Furthermore, the fact that the inventor has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985). The references as combined clearly disclose all features of the claim as currently presented. Mizuno does not have to disclose every value of the claimed range to read on the claim, but only needs to disclose one value within said range. Mizuno clearly discloses an embodiment wherein the values of tc, te, and td all fall within the claimed range.
Applicant further argues combining Lee discloses side margin portions formed on exposed sides of the internal electrodes whereas Mizuno does not teach said feature and focuses on metal material used for the internal electrodes and thus combining Lee with Mizuno would require a fundamental redesign of the capacitor structure. Applicant further argues neither reference discloses the relationship between tc, td, te, and wm because Lee and Mizuno dimensions are related to different design objectives. Applicant argues the Office action fails to provide a clear articulated reasoning that would draw one of ordinary skill in the art to the claimed invention.
The examiner finds applicants arguments to be unpersuasive. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Furthermore, the fact that the inventor has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985). Furthermore, both references are analogues as both references are drawn to multilayer ceramic capacitors. The previous rejection and the below rejections clearly point out where the limitations of the claimed invention are taught in the references and further provide a clear motivation as to why one of ordinary skill in the art would make such a combination
Applicant argues one of ordinary skill in the art would not combine the teachings Park with Mizuno and Nishisaka as Park is concerned with a different structure to optimize volume efficiency. Applicant states that making such a change would require additional non-trivial changes to the internal electrode layout and body dimensions and the cited references do not teach said changes nor has the Office action provided a reason why one of ordinary skill in the art would transplant Park’s L1 constraint into Mizuno.
The examiner finds applicants arguments to be unpersuasive. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Furthermore, all references are analogues as all references are drawn to multilayer ceramic capacitors. The previous rejection and the below rejections clearly point out where the limitations of the claimed invention are taught in the references and further provide a clear motivation as to why one of ordinary skill in the art would make such a combination
Applicant argues related to Mizuno and Sakashita are the same as those related to Mizuno and Nishisaka and have thus been addressed above.
Lastly, in response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2 & 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mizuno et al. (US 2016/0225525) in view of Nishisaka et al. (US 2013/0200749).
In regards to claim 1,
Mizuno ‘525 discloses a multilayer electronic component comprising:
a body (101 – fig. 1-2; [0050]) having a first surface and a second surface opposing each other in a first direction, a third surface and a fourth surface connected to the first surface and the second surface and opposing each other in a second direction, and a fifth surface and a sixth surface connected to the first to fourth surfaces and opposing each other in a third direction (fig. 1-2), the body including a capacitance formation portion including a dielectric layer (1011 – fig. 3; [0051]) and an internal electrode (102-103 – fig. 3; [0050]) disposed alternately with the dielectric layer in the first direction, and a cover portion (1012 – fig. 3; [0051]) disposed on both surfaces of the capacitance formation portion in the first direction; and
an external electrode (104-105 – fig. 2; [0050]) disposed on the third surface and the fourth surface,
wherein, when a maximum size of the multilayer electronic component in the second direction is L, a maximum size of the multilayer electronic component in the third direction is W, a maximum size of the multilayer electronic component in the first direction is T, an average size of the cover portion in the first direction is tc, an average size of the dielectric layer in the first direction is td, and an average size of the internal electrode in the first direction is te, 0.75 mm ≤ L ≤ 1.25 mm ([0090] – L =1.0mm), 0.25 mm ≤ W ≤ 0.75 mm ([0090] – W= 0.5 mm), 28 μm ≤ tc ≤ 34 μm (fig. 8; [0091]), 0.4 μm ≤ td ≤ 0.5 μm ([0091]), and 0.4 μm ≤ te ≤ 0.5 μm ([0091]) are satisfied. Mizuno ‘525 fails to disclose T < 0.5 mm.
Nishisaka ‘749 discloses T < 0.5 mm ([0051] & [0077]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the capacitor of Mizuno ‘525 to have a thickness as taught by Nishisaka ‘749 to obtain a thin capacitor that can be used in smaller electronics. Furthermore, a change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
In regards to claim 2,
Mizuno ‘525 as modified by Nishisaka ‘749 further discloses wherein T < W is satisfied ([0051] of Nishisaka ‘749).
In regards to claim 9,
Mizuno ‘525 as modified by Nishisaka ‘749 further discloses wherein 0.056 ≤ tc/T ≤ 0.67 is satisfied (table 1 of Mizuno ‘525 & [0051] of Nishisaka ‘749).
Claim(s) 3-4, 7-8, & 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mizuno ‘525 as modified by Nishisaka ‘749 as applied to claim 1 above, and further in view of Lee et al. (US 2021/0074479).
In regards to claim 3,
Mizuno ‘525 as modified by Nishisaka ‘749 further discloses wherein the internal electrode includes a first internal electrode (102) and a second internal electrode (103) alternately disposed in the first direction with the dielectric layer interposed therebetween,
the first internal electrode is disposed to be exposed from the third surface,
the second internal electrode is disposed to be exposed from the fourth surface, and
a side margin portion is disposed on the fifth surface and the sixth surface. Mizuno ‘525 as modified by Nishisaka ‘749 fails to disclose the first internal electrode extending to the fifth surface and the sixth surface, the second internal electrode extending to the fifth surface and the sixth surface, and a side margin portion is disposed on the fifth surface and the sixth surface.
Lee ‘479 discloses wherein the internal electrode includes a first internal electrode (121 – fig. 3; [0026]) and a second internal electrode (122 – fig. 3; [0026]) alternately disposed in the first direction with the dielectric layer interposed therebetween,
the first internal electrode is disposed to be exposed from the third surface and extending to the fifth surface and the sixth surface (fig. 3),
the second internal electrode is disposed to be exposed from the fourth surface and extending to the fifth surface and the sixth surface (fig. 3), and
a side margin portion (112 & 113 – fig. 2; [0035]) is disposed on the fifth surface and the sixth surface.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the capacitor of Mizuno ‘525 as modified by Nishisaka ‘749 such that the internal electrodes are exposed to sides surfaces during lamination and side margins are formed on the sides of the stack as taught by Lee ‘479 to obtain a capacitor that can be miniaturized and has good volume efficiency.
In regards to claim 4,
Mizuno ‘525 as modified by Nishisaka ‘749 and Lee ‘479 further discloses wherein, when an average size of the side margin portion in the third direction is wm, 13 μm ≤ wm ≤ 21 μm is satisfied ([0037] of Lee ‘479). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists, in re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); in re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed, Cir. 1990)
In regards to claim 7,
Mizuno ‘525 as modified by Nishisaka ‘749 and Lee ‘479 further discloses wherein a ratio of a minimum size of the side margin portion in the third direction to a maximum size of the side margin portion in the third direction is in a range from 0.9 to 1.0 (fig. 4 of Lee ‘479 – layers shown to have uniform thickness).
In regards to claim 8,
Mizuno ‘525 as modified by Nishisaka ‘749 and Lee ‘479 further discloses wherein a ratio (tc/wm) of average size (tc) of the cover portion in the first direction to average size (wm) of the side margin portion in the third direction is in a range from 2.0 to 2.25 (table 1 of Mizuno ‘525 & [0037] of Lee ‘479 – when wm is 14 or 15 μm).
In regards to claim 10,
Mizuno ‘525 as modified by Nishisaka ‘749 and Lee ‘479 further discloses wherein 0.028 ≤ wm/T ≤ 0.38 is satisfied ([0051] of Nishisaka ‘749 & [0037] of Lee ‘479 – when wm is 13 or 14 or 15 μm).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mizuno ‘525 as modified by Nishisaka ‘749 as applied to claim 1 above, and further in view of Park et al. (US 2014/0174806).
In regards to claim 5,
Mizuno ‘525 as modified by Nishisaka ‘749 further discloses wherein the internal electrode includes a first internal electrode (102) and a second internal electrode (103) alternately disposed in the first direction with the dielectric layer interposed therebetween,
the first internal electrode is disposed to be exposed from third surface and spaced apart from the fourth surface, and the second internal electrode is disposed to be exposed from the fourth surface and spaced apart from the third surface (fig. 2), and
when an average distance in the second direction between the third surface and the second internal electrode is L1 (fig. 2). Mizuno ‘525 as modified by Nishisaka ‘749 fails to disclose 30 μm ≤ L1 ≤ 50 μm is satisfied.
Park ‘806 discloses 30 μm ≤ L1 ≤ 50 μm is satisfied ([0064] & table 2).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the capacitor of Mizuno ‘525 as modified by Nishisaka ‘749 to have an L1 value as taught by Park ‘806 to obtain a capacitor with good volume efficiency and delamination prevention. Furthermore, a change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mizuno ‘525 as modified by Nishisaka ‘749 as applied to claim 1 above, and further in view of Mizuno (US 2022/028510).
In regards to claim 6,
Mizuno ‘525 as modified by Nishisaka ‘749 fails to disclose wherein a capacitance of the multilayer electronic component is 12 μF or more.
Mizuno ‘100 discloses wherein a capacitance of the multilayer electronic component is 12 μF or more (table 1) and further discloses capacitance is a design choice ([0056).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to design the capacitor of Mizuno ‘525 as modified by Nishisaka ‘749 to have a capacitance of 12 μF or more as taught by Mizuno ‘100 to obtain a capacitor with a desired capacitance for its intended use.
Claim(s) 1-2 & 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mizuno ‘525 in view of Sakashita et al. (US 2004/0217445).
In regards to claim 1,
Mizuno ‘525 discloses a multilayer electronic component comprising:
a body (101 – fig. 1-2; [0050]) having a first surface and a second surface opposing each other in a first direction, a third surface and a fourth surface connected to the first surface and the second surface and opposing each other in a second direction, and a fifth surface and a sixth surface connected to the first to fourth surfaces and opposing each other in a third direction (fig. 1-2), the body including a capacitance formation portion including a dielectric layer (1011 – fig. 3; [0051]) and an internal electrode (102-103 – fig. 3; [0050]) disposed alternately with the dielectric layer in the first direction, and a cover portion (1012 – fig. 3; [0051]) disposed on both surfaces of the capacitance formation portion in the first direction; and
an external electrode (104-105 – fig. 2; [0050]) disposed on the third surface and the fourth surface,
wherein, when a maximum size of the multilayer electronic component in the second direction is L, a maximum size of the multilayer electronic component in the third direction is W, a maximum size of the multilayer electronic component in the first direction is T, an average size of the cover portion in the first direction is tc, an average size of the dielectric layer in the first direction is td, and an average size of the internal electrode in the first direction is te, 0.75 mm ≤ L ≤ 1.25 mm ([0090] – L =1.0mm), 0.25 mm ≤ W ≤ 0.75 mm ([0090] – W= 0.5 mm), 28 μm ≤ tc ≤ 34 μm (fig. 8; [0091]), 0.4 μm ≤ td ≤ 0.5 μm ([0091]), and 0.4 μm ≤ te ≤ 0.5 μm ([0091]) are satisfied. Mizuno ‘525 fails to disclose T < 0.5 mm.
Sakashita ‘445 discloses T < 0.5 mm ([0110]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the capacitor of Mizuno ‘525 to have a thickness as taught by Sakashita ‘445 to obtain a thin capacitor that can be used in smaller electronics. Furthermore, a change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
In regards to claim 2,
Mizuno ‘525 as modified by Sakashita ‘445 further discloses wherein T < W is satisfied ([0090] of Mizuno ‘525 & [0110] of Sakashita ‘445).
In regards to claim 11,
Mizuno ‘525 as modified by Sakashita ‘445 further discloses wherein 0.70 ≤ T/W < 0.85 is satisfied ([0090] of Mizuno ‘525 & [0110] of Sakashita ‘445).
Claim(s) 12-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mizuno ‘525 in view of Nishisaka ‘749 and Lee ‘479.
In regards to claim 12,
Mizuno ‘525 discloses a multilayer electronic component comprising:
a body (101 – fig. 1-2; [0050]) including a capacitance formation portion including a dielectric layer (1011 – fig. 3; [0051]) and internal electrodes (102-103 – fig. 3; [0050]) disposed alternately with the dielectric layer in a thickness direction, and a cover portion disposed (1012 – fig. 3; [0051]) on opposing surfaces of the capacitance formation portion in the thickness direction; and
external electrodes (104-105 – fig. 2; [0050]) disposed on length-wise opposing surfaces,
wherein a thickness T of the multilayer electronic component, an average size, tc (table 1), of the cover portion in the thickness direction (fig. 2), 28 μm ≤ tc ≤ 34 μm (fig. 8; [0091]). Mizuno ‘525 fails to disclose side margin portions disposed on width-wise opposing surfaces, and an average size, wm, of the side margin portion in the width direction satisfying the following relationships: 0.056 ≤ tc/T ≤ 0.67; 0.028 ≤ wm/T ≤ 0.38.
Nishisaka ‘749 discloses T < 0.5 mm ([0051] & [0077]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the capacitor of Mizuno ‘525 to have a thickness as taught by Nishisaka ‘749 thus obtaining 0.056 ≤ tc/T ≤ 0.67 to obtain a thin capacitor that can be used in smaller electronics. Furthermore, a change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Lee ‘479 discloses side margin portions (112 & 113 – fig. 2; [0035]) disposed on width-wise opposing surfaces, an average size, wm ([0037]), of the side margin portion in the width direction.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the capacitor of Mizuno ‘525 as modified by Nishisaka ‘749 such that the internal electrodes are exposed to sides surfaces during lamination and side margins are formed on the sides of the stack as taught by Lee ‘479 thus obtaining (0.028 ≤ wm/T ≤ 0.38) to obtain a capacitor that can be miniaturized and has good volume efficiency.
In regards to claim 13,
Mizuno ‘525 as modified by Nishisaka ‘749 and Lee ‘479 further discloses wherein T less than 0.5 mm ([0051] of Nishisaka ‘749), and
a ratio of a minimum size of the side margin portion in the width direction to a maximum size of the side margin portion in the width direction is in a range from 0.9 to 1.0 (fig. 4 of Lee ‘479 – layers shown to have uniform thickness).
In regards to claim 14,
Mizuno ‘525 as modified by Nishisaka ‘749 and Lee ‘479 further discloses wherein tc/wm is in a range from 2.0 to 2.25 (table 1 of Mizuno ‘525 & [0037] of Lee ‘479 – when wm is 14 or 15 μm).
In regards to claim 15,
Mizuno ‘525 as modified by Nishisaka ‘749 and Lee ‘479 further discloses wherein length L of the multilayer electronic component satisfies 0.75 mm ≤ L ≤ 1.25 mm ([0090] of Mizuno ‘525), width W of the multilayer electronic component satisfies 0.25 mm ≤ W ≤ 0.75 mm ([0090] of Mizuno ‘525).
In regards to claim 16,
Mizuno ‘525 as modified by Nishisaka ‘749 and Lee ‘479 further discloses wherein average size (te) of the internal electrodes in the thickness direction satisfies 0.4 μm ≤ te ≤ 0.5 μm ([0091] of Mizuno ‘525), and
average size (td) of the dielectric layer in the thickness direction satisfies 0.4 μm ≤ td ≤ 0.5 μm ([0091] of Mizuno ‘525).
In regards to claim 17,
Mizuno ‘525 as modified by Nishisaka ‘749 and Lee ‘479 further discloses wherein the average size of the side margin portion in the width direction satisfies 13 μm ≤ wm ≤ 21 μm ([0037] of Lee ‘479). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists, in re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); in re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed, Cir. 1990).
Claim(s) 12 & 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mizuno ‘525 in view of Sakashita ‘445 and Lee ‘479.
In regards to claim 12,
Mizuno ‘525 discloses a multilayer electronic component comprising:
a body (101 – fig. 1-2; [0050]) including a capacitance formation portion including a dielectric layer (1011 – fig. 3; [0051]) and internal electrodes (102-103 – fig. 3; [0050]) disposed alternately with the dielectric layer in a thickness direction, and a cover portion disposed (1012 – fig. 3; [0051]) on opposing surfaces of the capacitance formation portion in the thickness direction; and
external electrodes (104-105 – fig. 2; [0050]) disposed on length-wise opposing surfaces,
wherein a thickness T of the multilayer electronic component, an average size, tc (table 1), of the cover portion in the thickness direction (fig. 2), 28 μm ≤ tc ≤ 34 μm (fig. 8; [0091]). Mizuno ‘525 fails to disclose side margin portions disposed on width-wise opposing surfaces, and an average size, wm, of the side margin portion in the width direction satisfying the following relationships: 0.056 ≤ tc/T ≤ 0.67; 0.028 ≤ wm/T ≤ 0.38.
Sakashita ‘445 discloses T < 0.5 mm ([0110]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the capacitor of Mizuno ‘525 to have a thickness as taught by Sakashita ‘445 thus obtaining 0.056 ≤ tc/T ≤ 0.67 to obtain a thin capacitor that can be used in smaller electronics. Furthermore, a change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Lee ‘479 discloses side margin portions (112 & 113 – fig. 2; [0035]) disposed on width-wise opposing surfaces, an average size, wm ([0037]), of the side margin portion in the width direction.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the capacitor of Mizuno ‘525 as modified by Sakashita ‘445 such that the internal electrodes are exposed to sides surfaces during lamination and side margins are formed on the sides of the stack as taught by Lee ‘479 thus obtaining (0.028 ≤ wm/T ≤ 0.38) to obtain a capacitor that can be miniaturized and has good volume efficiency.
In regards to claim 18,
Mizuno ‘525 as modified by Sakashita ‘445 further discloses wherein 0.70 ≤ T/W < 0.85 is satisfied ([0090] of Mizuno ‘525 & [0110] of Sakashita ‘445).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIMOTHY J DOLE can be reached at (571)272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David M Sinclair/Primary Examiner, Art Unit 2847
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