DETAILED ACTION
This action is responsive to the application filed 19 Aug 2024 and the Information Disclosure Statement filed 19 Aug 2024. Claims 1-20 are pending. Claims 1, 7 and 13 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 19 Aug 2024 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Application Title
The Examiner proposes the below Application Title change in accordance with MPEP 606.01 and MPEP 1302.04(a) to improve the descriptive nature of the title. The Applicant can suggest an alternative title if desired. The Application Title should be changed to the following:
“UNBALANCED PROGRAMMED DATA STATES USING CODEWORDS IN MEMORY”
No action is required by the applicant. The title has already been entered via the Bib Data sheet. If an allowance is processed, the Examiner will change the name as part of the Examiner’s Amendment process.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 10 and 14 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Specifically, claims 10 and 14 require: “to program to the first data state by applying a balancing algorithm to data that was encoded according to the selected data coding table.” It is not discussed in the specification how data that has been “translated” by a codeword to be unbalanced in a “first data state” was then “balanced” using a balancing algorithm. Each example in the specification was used to generate unbalanced codewords based on input data.
Allowable Subject Matter
Claims 9, 10, 14, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections – 35 USC § 102
<p id=“Normal Para”>The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
<p id=“Normal Para”>In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 – 8, 11 – 13, and 15 – 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Varanasi, et al, U.S. Patent Application Publication 2013/0311714 (“Varanasi”).
Regarding claim 1, Varanasi teaches:
An apparatus, comprising: a memory having a group of memory cells; and a controller, (Varanasi, fig 1, “[0017] FIG. 1 is a functional block diagram of an apparatus in the form of a computing system 100… the memory device 104, e.g., a solid state drive (SSD), thumb drive, etc., can include a physical host interface 106, a controller 108, e.g., processor, control circuitry, etc., and memory 110, e.g., arrangement of one or more memory cells.”; a memory with memory cells and a controller).
wherein the controller includes a number of data coding tables and is configured to: determine, using the number of data coding tables, a quantity of the memory cells of the group to program to a first data state; (Varanasi, fig 4, 5, “[0045] It may initially seem counterintuitive to store more bits as a way to increase endurance over that achieved by storing fewer bits. However, the mapping examples in FIGS. 4 and 5 will illustrate examples of the efficiency achievable by the apparatus… FIG. 4 shows a first table (on the left) including the possible bit combinations for 3 bits of input data (e.g., the m-bit dataword), and a second table ( on the right) including the possible combinations for 4 bits of encoded data (e.g., n-bit codeword).”; two coding tables which map desired stored information into data).
program the determined quantity of the memory cells of the group to the first data state; and (Varanasi, fig 4, 5, “[0045] FIG. 4 shows a first table (on the left) including the possible bit combinations for 3 bits of input data (e.g., the m-bit dataword), and a second table ( on the right) including the possible combinations for 4 bits of encoded data (e.g., n-bit codeword).”; that three bits of information are translated into four storage bits using the coding table, that the coding table has 4 bits with a specific ratio of stored “first state” and “second state” bits to represent the 3 bits on information; in this case the “determined quantity” is the number of “ones”).
program a remaining quantity of the memory cells of the group to a second data state. (Varanasi, fig 4, 5, “[0047] In each of those cases, the 4-bit combination has a quantity of 0’s that is greater than or equal to the quantity of 1 ‘s. In each such case, while the most significant “O” bit uses an additional portion of available SLC memory, the additional bit should not cause additional wear to the memory since an additional memory cell is not programmed to a data state that is expected to be more detrimental.”; that storing the balanced incoming data of 3 bits of information, the memory array can store an unbalanced number of zeros and ones; in the case of fig 4, the ratio is 22 zeros (second data state) and 10 ones (first data state)).
Regarding claim 2, Varanasi teaches The apparatus of claim 1, wherein the determined quantity of memory cells is less than half of the memory cells of the group. (Varanasi, fig 4, 5, “[0047] In each of those cases, the 4-bit combination has a quantity of 0’s that is greater than or equal to the quantity of 1 ‘s. In each such case, while the most significant “O” bit uses an additional portion of available SLC memory, the additional bit should not cause additional wear to the memory since an additional memory cell is not programmed to a data state that is expected to be more detrimental.”; that storing the balanced incoming data of 3 bits of information, the memory array can store an unbalanced number of zeros and ones; in the case of fig 4, the ratio is 22 zeros and 10 ones; in this case the “determined quantity” is used to store the “ones”).
Regarding claim 3, Varanasi teaches The apparatus of claim 1, wherein the determined quantity of memory cells comprises a percentage range of the memory cells of the group. (Varanasi, fig 4, 5, “[0047] In each of those cases, the 4-bit combination has a quantity of 0’s that is greater than or equal to the quantity of 1 ‘s. In each such case, while the most significant “O” bit uses an additional portion of available SLC memory, the additional bit should not cause additional wear to the memory since an additional memory cell is not programmed to a data state that is expected to be more detrimental.”; that storing the balanced incoming data of 3 bits of information, the memory array can store an unbalanced number of zeros and ones; in the case of fig 4, the ratio is 22 zeros and 10 ones; in this case the “percentage range” is 22:10, or 10/32 = 31% of the data is stored in the “ones” state; choosing fig 5 table would result in a different determined state).
Regarding claim 4, Varanasi teaches The apparatus of claim 1, wherein each of the number of data coding tables code a first quantity of data bits to data state values programmable to a second quantity of memory cells of the group. (Varanasi, fig 4, 5, “[0045] It may initially seem counterintuitive to store more bits as a way to increase endurance over that achieved by storing fewer bits. However, the mapping examples in FIGS. 4 and 5 will illustrate examples of the efficiency achievable by the apparatus… FIG. 4 shows a first table (on the left) including the possible bit combinations for 3 bits of input data (e.g., the m-bit dataword), and a second table ( on the right) including the possible combinations for 4 bits of encoded data (e.g., n-bit codeword).”; two coding tables which map desired stored information into data; fig 4 maps 3 information bits into 4 memory storage bits).
Regarding claim 5, Varanasi teaches The apparatus of claim 4, wherein the first quantity is smaller than the second quantity. (Varanasi, fig 4, 5, “[0045] It may initially seem counterintuitive to store more bits as a way to increase endurance over that achieved by storing fewer bits. However, the mapping examples in FIGS. 4 and 5 will illustrate examples of the efficiency achievable by the apparatus… FIG. 4 shows a first table (on the left) including the possible bit combinations for 3 bits of input data (e.g., the m-bit dataword), and a second table ( on the right) including the possible combinations for 4 bits of encoded data (e.g., n-bit codeword).”; two coding tables which map desired stored information into data; fig 4 maps 3 information bits ( a smaller number) into 4 memory storage bits (a larger number)).
Regarding claim 6, Varanasi teaches The apparatus of claim 4, wherein: each of the number of data coding tables includes a plurality of fields; and the data bits coded by each respective data coding table are included in only a subset of the plurality of fields of that respective data coding table. (Varanasi, fig 4, 5, “[0048] The last of the input 3-bit combinations (i.e., “111”) is shown in FIG. 4 being mapped to the next available 4-bit combination that has a quantity of O’s that is greater than or equal to the quantity of!’ s, as indicated at 456.”; that the coding table only uses 8 differently coded memory storage words (a subset) of the available 16 combinations for storage of the information bits).
Regarding claim 7, Varanasi teaches:
A method of operating memory, comprising: (Varanasi, fig 1, “[0017] FIG. 1 is a functional block diagram of an apparatus in the form of a computing system 100… the memory device 104, e.g., a solid state drive (SSD), thumb drive, etc., can include a physical host interface 106, a controller 108, e.g., processor, control circuitry, etc., and memory 110, e.g., arrangement of one or more memory cells.”; a memory with memory cells and a controller).
determining, using a single data coding table included in a memory controller, a quantity of memory cells of a group of memory cells to program to a first data state; (Varanasi, fig 4, 5, “[0045] It may initially seem counterintuitive to store more bits as a way to increase endurance over that achieved by storing fewer bits. However, the mapping examples in FIGS. 4 and 5 will illustrate examples of the efficiency achievable by the apparatus… FIG. 4 shows a first table (on the left) including the possible bit combinations for 3 bits of input data (e.g., the m-bit dataword), and a second table ( on the right) including the possible combinations for 4 bits of encoded data (e.g., n-bit codeword).”; two coding tables which map desired stored information into data; in this case, the word “comprised” in claim 7 also includes using two tables).
programming the determined quantity of the memory cells of the group to the first data state; and (Varanasi, fig 4, 5, “[0045] FIG. 4 shows a first table (on the left) including the possible bit combinations for 3 bits of input data (e.g., the m-bit dataword), and a second table ( on the right) including the possible combinations for 4 bits of encoded data (e.g., n-bit codeword).”; that three bits of information are translated into four storage bits using the coding table, that the coding table has 4 bits with a specific ratio of stored “first state” and “second state” bits to represent the 3 bits on information; in this case the “determined quantity” is the number of “zeroes”).
programming a remaining quantity of the memory cells of the group to a second data state. (Varanasi, fig 4, 5, “[0047] In each of those cases, the 4-bit combination has a quantity of 0’s that is greater than or equal to the quantity of 1 ‘s. In each such case, while the most significant “O” bit uses an additional portion of available SLC memory, the additional bit should not cause additional wear to the memory since an additional memory cell is not programmed to a data state that is expected to be more detrimental.”; that storing the balanced incoming data of 3 bits of information, the memory array can store an unbalanced number of zeros and ones; in the case of fig 4, the ratio is 22 zeros (first data state) and 10 ones (second data state)).
Regarding claim 8, Varanasi teaches The method of claim 7, wherein the determined quantity of memory cells is greater than half of the memory cells of the group. (Varanasi, fig 4, 5, “[0047] In each of those cases, the 4-bit combination has a quantity of 0’s that is greater than or equal to the quantity of 1 ‘s. In each such case, while the most significant “O” bit uses an additional portion of available SLC memory, the additional bit should not cause additional wear to the memory since an additional memory cell is not programmed to a data state that is expected to be more detrimental.”; that storing the balanced incoming data of 3 bits of information, the memory array can store an unbalanced number of zeros and ones; in the case of fig 4, the ratio is 22 zeros and 10 ones; in this case the “determined quantity” is used to store the “zeroes”).
Regarding claim 11, Varanasi teaches The method of claim 7, wherein different combinations of data bits of the single data coding table are coded to different data state values programmable to the memory cells of the group. (Varanasi, fig 4, 5, “[0047] In each of those cases, the 4-bit combination has a quantity of 0’s that is greater than or equal to the quantity of 1 ‘s. In each such case, while the most significant “O” bit uses an additional portion of available SLC memory, the additional bit should not cause additional wear to the memory since an additional memory cell is not programmed to a data state that is expected to be more detrimental.”; that storing the balanced incoming data of 3 bits of information, the memory array can store an unbalanced number of zeros and ones; in the case of fig 4, the ratio is 22 zeros and 10 ones; in this case the “percentage range” is 22:10, or 10/32 = 31% of the data is stored in the “ones” state; choosing fig 5 table would result in a different determined state).
Regarding claim 12, Varanasi teaches The method of claim 11, wherein the different combinations of the data bits correspond to a greater number of data state values corresponding to the first data state than the second data state. (Varanasi, fig 4, 5, “[0047] In each of those cases, the 4-bit combination has a quantity of 0’s that is greater than or equal to the quantity of 1 ‘s. In each such case, while the most significant “O” bit uses an additional portion of available SLC memory, the additional bit should not cause additional wear to the memory since an additional memory cell is not programmed to a data state that is expected to be more detrimental.”; that storing the balanced incoming data of 3 bits of information, the memory array can store an unbalanced number of zeros and ones; in the case of fig 4, the ratio is 22 zeros and 10 ones; in this case the “percentage range” is 22:10, or 10/32 = 31% of the data is stored in the “ones” state; choosing fig 5 table would result in a different determined state).
Regarding claim 13, Varanasi teaches:
An apparatus, comprising: a memory having a group of memory cells; and a controller, (Varanasi, fig 1, “[0017] FIG. 1 is a functional block diagram of an apparatus in the form of a computing system 100… the memory device 104, e.g., a solid state drive (SSD), thumb drive, etc., can include a physical host interface 106, a controller 108, e.g., processor, control circuitry, etc., and memory 110, e.g., arrangement of one or more memory cells.”; a memory with memory cells and a controller).
wherein the controller includes a plurality of data coding tables and is configured to: select one of the plurality of data coding tables; (Varanasi, fig 4, 5, “[0045] It may initially seem counterintuitive to store more bits as a way to increase endurance over that achieved by storing fewer bits. However, the mapping examples in FIGS. 4 and 5 will illustrate examples of the efficiency achievable by the apparatus… FIG. 4 shows a first table (on the left) including the possible bit combinations for 3 bits of input data (e.g., the m-bit dataword), and a second table ( on the right) including the possible combinations for 4 bits of encoded data (e.g., n-bit codeword).”; two coding tables which map desired stored information into data).
determine, using the selected data coding table, a quantity of the memory cells of the group to program to a first data state; (Varanasi, fig 4, 5, “[0047] In each of those cases, the 4-bit combination has a quantity of 0’s that is greater than or equal to the quantity of 1 ‘s. In each such case, while the most significant “O” bit uses an additional portion of available SLC memory, the additional bit should not cause additional wear to the memory since an additional memory cell is not programmed to a data state that is expected to be more detrimental.”; that storing the balanced incoming data of 3 bits of information, the memory array can store an unbalanced number of zeros and ones; in the case of fig 4, the ratio is 22 zeros and 10 ones; in this case the “percentage range” is 22:10, or 10/32 = 31% of the data is stored in the “ones” state; choosing fig 5 table would result in a different determined state).
program the determined quantity of the memory cells of the group to the first data state; and (Varanasi, fig 4, 5, “[0045] FIG. 4 shows a first table (on the left) including the possible bit combinations for 3 bits of input data (e.g., the m-bit dataword), and a second table ( on the right) including the possible combinations for 4 bits of encoded data (e.g., n-bit codeword).”; that three bits of information are translated into four storage bits using the coding table, that the coding table has 4 bits with a specific ratio of stored “first state” and “second state” bits to represent the 3 bits on information; in this case the “determined quantity” is the number of “ones”).
program a remaining quantity of the memory cells of the group to a second data state. (Varanasi, fig 4, 5, “[0047] In each of those cases, the 4-bit combination has a quantity of 0’s that is greater than or equal to the quantity of 1 ‘s. In each such case, while the most significant “O” bit uses an additional portion of available SLC memory, the additional bit should not cause additional wear to the memory since an additional memory cell is not programmed to a data state that is expected to be more detrimental.”; that storing the balanced incoming data of 3 bits of information, the memory array can store an unbalanced number of zeros and ones; in the case of fig 4, the ratio is 22 zeros (second data state) and 10 ones (first data state)).
Regarding claim 15, Varanasi teaches The apparatus of claim 13, wherein the determined quantity of memory cells comprises greater than a particular percentage of the memory cells of the group. (Varanasi, fig 4, 5, “[0047] In each of those cases, the 4-bit combination has a quantity of 0’s that is greater than or equal to the quantity of 1 ‘s. In each such case, while the most significant “O” bit uses an additional portion of available SLC memory, the additional bit should not cause additional wear to the memory since an additional memory cell is not programmed to a data state that is expected to be more detrimental.”; that storing the balanced incoming data of 3 bits of information, the memory array can store an unbalanced number of zeros and ones; in the case of fig 4, the ratio is 22 zeros and 10 ones; in this case the “percentage range” is 22:10, or 10/32 = 31% of the data is stored in the “ones” state; choosing fig 5 table would result in a different determined state and the user can “determine” to use one percentage or the other).
Regarding claim 16, Varanasi teaches The apparatus of claim 13, wherein the plurality of data coding tables comprises three data coding tables. (Varanasi, fig 4, 5, “[0047] In each of those cases, the 4-bit combination has a quantity of 0’s that is greater than or equal to the quantity of 1 ‘s. In each such case, while the most significant “O” bit uses an additional portion of available SLC memory, the additional bit should not cause additional wear to the memory since an additional memory cell is not programmed to a data state that is expected to be more detrimental. [0044] For example, m may be 16 (or some other non-zero, positive integer quantity) and n may be 17 ( or some other non-zero, positive integer quantity greater than m).”; that storing the balanced incoming data of 3 bits of information can be coded into 4 or 5 bit codewords; that another coding table can code 16 bits into 17 bits (or any combination where m<n)).
Regarding claim 17, Varanasi teaches:
The apparatus of claim 13, wherein: one of the plurality of data coding tables codes three data bits to data state values programmable to four memory cells of the group; and (Varanasi, fig 4, 5, “[0048] The last of the input 3-bit combinations (i.e., “111”) is shown in FIG. 4 being mapped to the next available 4-bit combination that has a quantity of O’s that is greater than or equal to the quantity of!’ s, as indicated at 456.”; that the coding table only uses 8 differently coded memory storage words (a subset) of the available 16 combinations for storage of the information bits).
another one of the plurality of data coding tables codes four data bits to data state values programmable to five memory cells of the group. (Varanasi, fig 4, 5, “[0044] FIG. 4 illustrates mapping 3 bits of data to a 4-bit index in accordance with one or more embodiments of the present disclosure. According to one or more embodiments of the present disclosure, the quantity n is greater than the quantity m. For example, in a binary environment, the n-digit codeword actually stored in the memory device has more bits than the input m-digit dataword. However, embodiments of the present disclosure are not limited to any particular value form and/or n. That is, m may be greater than or less than the values used in the example illustrated in this disclosure. For example, m may be 16 (or some other non-zero, positive integer quantity) and n may be 17 ( or some other non-zero, positive integer quantity greater than m).”; that the coding tables can comprise any value of m from 3 to 15 and any value of m from 4 to 16).
Regarding claim 18, Varanasi teaches The apparatus of claim 13, wherein the controller is configured to select the one of the plurality of data coding tables based on a characteristic of the memory. (Varanasi, fig 3, 4, 5, “[0033] However, embodiments of the present disclosure are not so limited, and it will be appreciated that the apparatuses and methods of the present disclosure can be adapted to a different mapping of data states to physical conditions of a memory cell by seeking to lessen the use of data states that are more detrimental to wear of the memory cell. [0044] According to one or more embodiments of the present disclosure, the quantity n is greater than the quantity m. … That is, m may be greater than or less than the values used in the example illustrated in this disclosure. For example, m may be 16 (or some other non-zero, positive integer quantity) and n may be 17 ( or some other non-zero, positive integer quantity greater than m).”; that as physical conditions change in a memory, different mapping of data states can be used. Paragraph 0044 uses 16 bits encoded to 17 bits which would be closer to 1:1 ration than the 3 bits into 4 bits shown in figure 4).
Regarding claim 19, Varanasi teaches The apparatus of claim 18, wherein the controller is configured to select a different one of the plurality of data coding tables in response to a change in the characteristic of the memory. (Varanasi, fig 3, 4, 5, “[0033] However, embodiments of the present disclosure are not so limited, and it will be appreciated that the apparatuses and methods of the present disclosure can be adapted to a different mapping of data states to physical conditions of a memory cell by seeking to lessen the use of data states that are more detrimental to wear of the memory cell. [0044] According to one or more embodiments of the present disclosure, the quantity n is greater than the quantity m. … That is, m may be greater than or less than the values used in the example illustrated in this disclosure. For example, m may be 16 (or some other non-zero, positive integer quantity) and n may be 17 ( or some other non-zero, positive integer quantity greater than m).”; that as physical conditions change in a memory, different mapping of data states can be used that are less “detrimental” to a memory cell. Paragraph 0044 uses 16 bits encoded to 17 bits which would be closer to 1:1 ration than the 3 bits into 4 bits shown in figure 4).
Conclusion
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825