Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/19/2024 is being considered by the examiner.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Japan on October 13, 2023. It is noted, however, that applicant has not filed a certified copy of the JP2023-177487 application as required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1, lines 1-2, it is not clear whether the information processing device and plurality of calculation bases is within the computing system or the computing system including the plurality of calculation bases is within the information processing device. Similar problems exist in claims 5 and 9.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CHIU (U.S. Publication No. 2020/0242724 A1), hereafter referred to as CHIU’724.
Referring to claim 1, CHIU’724 as claimed, an information processing device (see Figs. 4-6) included in a first calculation base of a plurality of calculation bases (various arrangements of the GPUs, CPUs, see Figs. 4-6 and paras. [0035], [0036], and [0040]), in a computer system that includes the plurality of calculation bases each that includes a first processor, an interconnect switch that conforms to an interconnect standard (switch, see Figs. 4-6 and paras. [0035], [0036], and [0040]; also note: Quick Path Interconnect, see para. [0012]), and a plurality of devices coupled to the first processor via the interconnect switch (the GPUs communicate with switch(es) and the switch(es) perform data interaction with CPU, see paras. [0025], [0036], and [0040]), the information processing device comprising: a memory (memory such as storage device 300, see Fig. 1 and para. [0018]); and a second processor (at least two CPUs, see paras. [0012], [0019], [0033], [0036]) coupled to the memory and configured to: in a case of detecting a processing delay with respect to a processing target in a first device of the plurality of devices included in the first calculation base and where each usage status of the plurality of devices included in the first calculation base satisfies a predefined remote load distribution condition (factors such as the request for resource usage, completion time, and cost; if there is a time limit, the calculation needs to be completed as soon as possible, see paras. [0023] and [0031]), cause a second device of unused devices of the plurality of devices, the second device being included in a second calculation base of the plurality of calculation bases, a connection delay of the second calculation base being less than a predetermined value, to process the processing target, based on each usage status of the plurality of devices included in each of the plurality of calculation bases and each connection delay of a communication path from the first calculation base to each of the plurality of calculation bases (each group of joint bodies exchange data with the CPUs, thus the bandwidth of the switch can be maximized; calculates the quantity of GPUs required and arranges the GPUs to maximize the GPU transmissions, see paras. [0023], [0038], [0040], [0043], [0046] and Figs. 4-6).
As to claim 2, CHIU’724 also discloses the first calculation base is configured to: generate a device control packet used to control the second device, based on a packet that conforms to the interconnect standard, and control the plurality of devices, wherein the second processor requests the first calculation base to issue the device control packet, and wherein the first calculation base sets the second device to be in an operable state, based on the device control packet generated by the first calculation base (the arranging module arranges a relationship in the arrangement between the GPUs and the switch(es), and a relationship in relation to the CPUs, according to the usage of GPUs and the reset arrangement principle, so as to arrange the GPU resources for optimal acceleration, see paras. [0024]-[0026], [0033], [0035], [0036], and [0040]).
As to claim 3, CHIU’724 also discloses a device of the plurality of devices is a field programmable gate array (FPGA) (FPGA, see para. [0019]), and wherein the first calculation base sets logical arrangement of the FPGA according to the device control packet (the arranging module arranges a relationship in the arrangement between the GPUs and the switch(es), and a relationship in relation to the CPUs, according to the usage of GPUs and the reset arrangement principle, so as to arrange the GPU resources for optimal acceleration, see paras. [0024]-[0026], [0033], [0035], [0036], [0040], and Figs. 4-6).
As to claim 4, CHIU’724 also discloses wherein the second device is included in a third calculation base of the plurality of calculation bases, the third calculation base satisfying a condition that preset selection restriction information indicates, among the calculation bases of which the connection delay is less than the predetermined value (each group of joint bodies exchange data with the CPUs, thus the bandwidth of the switch can be maximized; calculates the quantity of GPUs required and arranges the GPUs to maximize the GPU transmissions, see paras. [0023], [0038], [0040], [0043], [0046] and Figs. 4-6).
Note claims 5 and 9 recite similar limitations of claim 1. Therefore they are rejected based on the same reason accordingly.
Note claims 6 and 10 recite similar limitations of claim 2. Therefore they are rejected based on the same reason accordingly.
Note claims 7 and 11 recite similar limitations of claim 3. Therefore they are rejected based on the same reason accordingly.
Note claims 8 and 12 recite similar limitations of claim 4. Therefore they are rejected based on the same reason accordingly.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
SHIMIZU (U.S. Publication No. 2024/0037056 A1) discloses an information processing apparatus storing a connection control program capable of sharing, among a plurality of information processing apparatuses PCIe devices disposed inside the respective information processing apparatuses.
Torno et al. (U.S. Patent No. 11,609,871 B1) discloses integrated circuit device with crossbar to monitor bandwidth usage at different channels and selectively route traffic between masters and different channels based on the monitored bandwidth usage.
Frey et al. (U.S. Publication No. 2009/0083471 A1) discloses a method for providing accelerator support in a bus protocol.
Gupte et al. (U.S. Publication No. 2022/0035684 A1) discloses dynamic load balancing of operations for real-time deep learning analytics.
Dwivedi et al. (U.S. Publication No. 2024/0378094 A1) discloses profiling and performance monitoring of distributed computational pipelines.
Vembu et al. (U.S. Publication No. 2020/0285480 A1) discloses a scheduling mechanism that accounts for barrier usage during scheduling of a thread group across multiprocessors within a graphics processor.
Diard (U.S. Publication No. 2005/0041031 A1) discloses adaptive load balancing in a multi-processor graphics processing system that renders different portions of a frame.
Miller et al. (U.S. Publication No. 2009/0109230 A1) discloses methods for load balancing between multiple processing units.
Sprangle et al. (U.S. Publication No. 2011/0157195 A1) discloses sharing resources between a CPU and a GPU.
Zhao et al. (U.S. Publication No. 2019/0324856 A1) discloses optimization of checkpoint operations for deep learning computing.
Hierman et al. (U.S. Publication No. 2022/0229677 A1) discloses performance modelling of graphics processing computing architectures.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Contact Information
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/TITUS WONG/Primary Examiner, Art Unit 2181