DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/24/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claims 1,4-6, 8-9, 12 and 14-16 have been considered but are moot because the new ground of rejection does not rely on the previous reference specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 5, 8, 9 , 12 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Zarganis et al. U.S. Patent 7,259,969 (hereinafter D1) in view of Fagrenius et al. U.S. Pub. 2005/0254224 (hereinafter D2).
Regarding claim 1, D1 teaches an electronic device comprising:
a housing (74; figure 11);
a circuit board (14; figure 11) disposed inside the housing;
a first electric element (15; figure 11) disposed on the circuit board (14); and
a shielding member (10; figure 11) attached on a surface to the circuit board by an adhesive material (16; see column 14, lines 39-45), the shielding member (10) having a shielding space (space inside 10) formed therein in which the first electric element (15) is disposed,
wherein the shielding member (10) includes a plate (72; figure 11) and a sidewall (sidewall of 10; figure 11) extending from a circumference (see figure 11) of the plate towards the circuit board (14),
wherein the sidewall (sidewall of 10) includes an inside surface (inside surface of 10; figure 11) facing the shielding space, an outside surface (outside surface of 10; figure 11) opposite to the inside surface, and a bottom surface (bottom surface of 10; figure 11) facing the circuit board.
However, D1 does not specifically teach that the sidewall includes at least one protrusion extending toward the circuit board,
wherein the at least one protrusion includes at least one recess formed through the side wall on the bottom surface,
wherein at least part of the adhesive material is received in the at least one recess,
wherein the at least one recess includes a first recess, and wherein when the shielding member is attached to the circuit board, a width of the first recess is decreased toward the circuit board; and
wherein the last one protrusion does not penetrate through the circuit board.
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D2, teaches a similar structure, which suggests a sidewall (14; figure 3) including at least one protrusion (see above annotated figure 4 of D2) extending toward the circuit board (12; figure 4),
wherein the at least one protrusion (see above annotated figure 4 of D2) includes at least one recess (19; figure 4) formed through the side wall (14) on the bottom surface (see figure 4),
wherein an adhesive material (see par[0042]; “solder 18…by dispensing” is interpreted as adhesive) is received in the at least one recess,
wherein the at least one recess includes a first recess (19; figure 4), and wherein a width (width of recess 19) of the first recess is decreased (see figure 4) toward the circuit board (12); and
wherein the last one protrusion does not (see figure 4 of D2) penetrate through the circuit board (12).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the sidewall of D1, such that it would include at least one protrusion extending toward the circuit board, wherein the at least one protrusion includes at least one recess formed through the side wall on the bottom surface, wherein the at least one recess includes a first recess, and wherein, when the shielding member is attached to the circuit board, a width of the first recess is decreased toward the circuit board; wherein the last one protrusion does not penetrate through the circuit board, as suggested by D2, to ensure good/close contact or co-planarity between the shield and the PCB (see column 7, lines 50-59 of D2).
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Regarding claim 4, the modification of D1/D2 would result in the electronic device of claim 1, wherein the sidewall includes a plurality of protrusions (see above annotated figure 4 of D2) extending toward the circuit board (12) and a plurality of recesses (19; figure 4 of D2) formed between (see above annotated figure of D4) the plurality of protrusions, and wherein the plurality of protrusions comprises (see above annotated figure 4 of D2) the at least one protrusion.
Regarding claim 5, the modification of D1/D2 would result in electronic device of claim 4, wherein at least part of the adhesive material (18; figure 4 of D2) is received in the plurality of recesses.
Regarding claim 8, D1/D2 teaches the electronic device of claim 1, wherein the sidewall (side wall of 10; figure 11 of D1) is extended substantially perpendicular (see figure 11 of D1) to the plate.
Regarding claim 9, the modification of D1/D2 would result in the electronic device of claim 4, wherein the plurality of protrusions (see above annotated figure 4 of D2) are spaced apart from each other at a predetermined interval (see above annotated figure 4 of D2) along a circumferential direction (see above figure 4 of D2) of the plate.
Regarding claim 12, D1/D2 teaches the electronic device of claim 1, wherein the adhesive material is conductive (see par[0042] of D2; “solder” is conductive).
Regarding claim 14, as mentioned above, D1/D2 teaches the electronic device of claim 13.
However, D1/D2 does not specifically teach the shielding member contains a metallic material.
D1, discloses the shielding member (10; figure 1 of D1) contains a metallic material (“metal layers 13”; see column 8, lines 30-37).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to further provide the shielding member of D1/D2 with a metallic material/layer, as also suggested by D1, to provide EMI shielding.
Regarding claim 15, the modification of D1/D2 would result in the electronic device of claim 1, wherein the shielding member does not (as modified by figure 4 of D2) extend through the circuit board.
Regarding claim 16, the modification of D1/D2 would result in the electronic device of claim 1, wherein the shielding member is attached to the surface of the circuit board by the adhesive material without (as modified by figure 4 of D2) insertion of any portion of the shielding member into any hole or opening of the circuit board.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Zarganis et al. U.S. Patent 7,259,969 (hereinafter D1) in view of Fagrenius et al. U.S. Pub. 2005/0254224 (hereinafter D2) and in further view of Seidler U.S. Pub. 2003/0136812 (hereinafter D3).
Regarding claim 6, the modification of D1/D2 would result in the electronic device of claim 4.
However, D1/D2 does not specifically teach that at least part of the adhesive covers at least part of the outside surface and at least part of the inside surface.
D3, suggests the use of an solder material (70; figure 9) for holding and covering at least part of the outside surface and at least part of the inside surface (see figure 9) of a sidewall (30; figure 9) to a substrate (100; figure 9).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to further provide at least part of the solder covers at least part of the outside surface and at least part of the inside surface of D1/D2, as suggested by D3 to further secure said shielding member to said circuit board.
D1, further suggests solder and conductive adhesive (see column 4, lines 6-9) maybe used/substituted with each other for fixedly couple a clip to a circuit board (see column 4, lines 6-9).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to further substitute the solder of D1/D2/D3 with an adhesive, as suggested by D1, such that at least part of the adhesive would cover at least part of the outside surface and at least part of the inside surface, to achieve the advantage of bonding dissimilar and heat-sensitive materials together.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNG Q DANG whose telephone number is (571)272-3069. The examiner can normally be reached M-F 10-6PM..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Imani N Hayman can be reached at 571-270-5528. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HUNG Q DANG/Examiner, Art Unit 2841
/IMANI N HAYMAN/Supervisory Patent Examiner, Art Unit 2841
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