DETAILED ACTION
This Office Action is in response to the application 18/808887, filed on 08/19/2024.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per the Preliminary Amendment filed on 08/27/2024, claims 1-20 were canceled; claims 21-40 have been added. Claims 21-40 are pending in this application, claims 21, 28, and 34 are independent.
Priority/Continuity
This application is a continuation of Application No. 17/946518, filed on 09/16/2022, currently US Patent No. 12,067,270.
Information Disclosure Statement
The information disclosure statement (IDS), submitted on 08/19/2024, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claim 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 12,067,270. Although, the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are anticipated by the reference claims.
The following claims are presented side by side for comparison. The comparison shows how the broader the independent claims 21, 28 and 34 of the instant application are anticipated by the reference patent’s claims 1-2, 8-12, 14, and 17. While the independent claims 21 and 28 of the instant application cites, “deleting the row counter,” dependent claims 2 and 12, of the reference patent captures the limitation “deleting the row counter.” While claim independent 34 of the instant application cites, “determining that the CAM is full,” all independent claims 1, 8 and 14, of the reference patent captures the limitation “the CAM is full.” Additionally, while claim independent 34 of the instant application cites, “decrement a plurality of row counters stored in the CAM,” the dependent claim 17, of the reference patent captures the limitation “decrement a plurality of counts of a plurality of row counters stored in the CAM.”
Instant Application 18/808,887
Reference Patent 12,067,270
21. A method, comprising:
receiving a row activation command having a row address at control circuitry of a memory sub-system;
incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system;
determining, at the control circuitry, whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); and
responsive to determining that the first count is greater than the RHT minus the second count, deleting the row counter corresponding to the row address from the CAM.
1. A method, comprising:
receiving a row activation command having a row address at control circuitry of a memory sub-system;
incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system;
determining, at the control circuitry, whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC), wherein the second count is incremented each time the CAM is full; and
responsive to determining that the first count is greater than the RHT minus the second count, issuing a refresh command to the row address.
2. The method of claim 1, further comprising, responsive to determining that the first count is greater than the RHT minus the second count, deleting the row counter corresponding to the row address from the CAM.
28. An apparatus, comprising:
a content addressable memory (CAM); a memory device; and control circuitry coupled to the memory device and configured to:
receive a row activation command having a row address of the memory device;
responsive to determining that a row counter corresponding to the row address is stored in the CAM, increment a first count of the row counter;
determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); and
responsive to determining that the first count is greater than the RHT minus the second count:
issue a refresh command to the row address; and
delete the row counter corresponding to the row address from the CAM.
8. An apparatus, apparatus, comprising: a content addressable memory (CAM);
a memory device; and control circuitry coupled to the memory device and configured to:
receive a row activation command having a row address of the memory device;
responsive to determining that a row counter corresponding to the row address is stored in the CAM, increment a first count of the row counter;
determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC), wherein the CDC stores a quantity of times different row addresses have been unassociated with the CAM once the CAM is full; and
responsive to determining that the first count is greater than the RHT minus the second count, issue a refresh command to the row address.
12. The apparatus of claim 11, wherein the control circuitry is further configured to, responsive to determining that the CAM does not have space to store the row counter, delete any of the plurality of counts that have a zero value to unassociated a particular row corresponding to a deleted count with the CAM.
34. An apparatus, comprising:
a content addressable memory (CAM); a memory device;
control circuitry coupled to the memory device and configured to:
receive a row activation command directed to a row address of the memory device;
determine whether a row counter corresponding to the row address is stored in the CAM;
responsive to determining that the row counter is not stored in the CAM and to determining that the CAM is full:
decrement a plurality of row counters stored in the CAM; and
increment a second count of a CAM decrease counter (CDC);
responsive to determining that the row counter corresponding to the row address is stored in the CAM, determine whether a first count of the row counter is greater than a difference between a row hammer threshold (RHT) and the second count of the CDC; and
responsive to determining that the first count is greater than the difference between the RHT and the second count, issue a refresh command to the row address
14. An apparatus, comprising:
a content addressable memory (CAM); a memory device;
control circuitry coupled to the memory device and configured to:
receive a row activation command directed to a row address of the memory device;
determine whether a row counter corresponding to the row address is stored in the CAM;
responsive to determining that the row counter corresponding to the row address is stored in the CAM, determine whether a first count of the row counter is greater than a difference between a row hammer threshold (RHT) and a second count of a CAM decrease counter (CDC), wherein the CDC stores a quantity of times different row addresses have been unassociated with the CAM once the CAM is full; and
responsive to determining that the first count is greater than the difference between the RHT and the second count, issue a refresh command to the row address.
17. The apparatus of claim 16, wherein the control circuitry is further configured to, responsive to determining that the CAM does not have space to store the row counter, decrement a plurality of counts of a plurality of row counters stored in the CAM.
Claim Objections
Claims 22-27, 29-33 and 35-40, are objected to because of the following informalities:
As to claims 22-27, claims 22-27 cite the limitation “[t]he method of claim 1” in preamble of each claim. It’s believed that it’s a typographical error. Thus, it’s suggested that the aforementioned limitation be further amended as “[t]he method of claim 21;” (emphasis added).
As to claims 22-27, claim 29 cites the limitation “[t]he method of claim 8” in preamble of each claim. It’s believed that it’s a typographical error. Thus, it’s suggested that the aforementioned limitation be further amended as “[t]he method of claim 28”. Claims 30-31 cite the limitation “[t]he method of claim 9” in preamble of each claim. It’s believed that it’s a typographical error. Thus, it’s suggested that the aforementioned limitation be further amended as “[t]he method of claim 29”. Also, claims 32-33 cite the limitation “[t]he method of claim 11” in preamble of each claim. It’s believed that it’s a typographical error. Thus, it’s suggested that the aforementioned limitation be further amended as “[t]he method of claim 31” (emphasis added).
As to claims 35-40, claims 35-36 cite the limitation “[t]he method of claim 14” in preamble of each claim. It’s believed that it’s a typographical error. Thus, it’s suggested that the aforementioned limitation be further amended as “[t]he method of claim 34”. Claim 37 cites the limitation “[t]he method of claim 16” in preamble of each claim. It’s believed that it’s a typographical error. Thus, it’s suggested that the aforementioned limitation be further amended as “[t]he method of claim 36”. Claim 38 cites the limitation “[t]he method of claim 17” in preamble of each claim. It’s believed that it’s a typographical error. Thus, it’s suggested that the aforementioned limitation be further amended as “[t]he method of claim 37”. Also, claims 39-40 cite the limitation “[t]he method of claim 18” in preamble of each claim. It’s believed that it’s a typographical error. Thus, it’s suggested that the aforementioned limitation be further amended as “[t]he method of claim 38” (emphasis added).
Appropriate corrections required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), fourth paragraph:
Subject to the [fifth paragraph of 35 U.S.C. 112 (pre-AIA )], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 22 is rejected under 35 U.S.C. 112(d) or 35 U.S.C. 112 (pre-AIA ), fourth paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
As to claim 22, claim 22 recites the limitations “responsive to determining that the first count is greater than the RHT minus the second count, deleting the row counter corresponding to the row address from the CAM.” However, said limitations are already recited in the parent claim 21 (refer to discussions in the objection section above for claim dependency). As claim 22 fails to further limit the subject matter of the claim upon which it depends, claim 22 is rejected under 35 U.S.C. 112(d) or 35 U.S.C. 112 (pre-AIA ), fourth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the Examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (“Cho,” US 2023/0067144, filed on 03/11/2022), in view of Nale et al (“Nale,” US 2022/0121398, published on 04/21/2022).
As to claim 1, Chu teaches a method (Chu: pars 0008-010, discloses a method and system for managing content-addressable memory (CAM) system efficiently performing a hammer refresh operation), comprising:
receiving a row activation command having a row address at control circuitry of a memory sub-system (Chu: pars 0008-0010; Fig. 1, 6, receiving and performing command protocol for a row hammer management circuit to count each of access addresses associated with accesses to a plurality of memory cell rows of the semiconductor memory device to store counting values therein and for determining a hammer address associated with at least one memory cell row);
incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system (Chu: pars 0009, 0068-0072, the counter increases a counting value corresponding to the target row address);
determining, at the control circuitry, whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC) (Chu: pars 0009, 0068-0072, counting value of the target row address being equal to or greater than first reference number NTH1 [i.e., row hammer threshold] and smaller than the second reference number NTH2 [i.e., minus a second count]); and
responsive to determining that the first count is greater than the RHT minus the second count (Chu: pars 0071-0072, in response to counting value of the target row address being equal to or greater than first reference number, a signal is provided to a scheduler to adjust the hammer address).
Chu does not explicitly teach the limitation, deleting the row counter corresponding to the row address from the CAM.
However, in an analogous art, Nale teaches the limitation, deleting the row counter corresponding to the row address from the CAM (Nale: pars 0016-0017, discloses a memory device with row hammer tracking a managing row address count. Pars 0043-0044, 0055, teaches leaving the row address in address storage until the number of accesses reaches M−1 [i.e., minus a second count], and evicting row address before it reaches M−1 [i.e., deleting row counter]. Indicate not to increment and remove the address when the address is found in address storage [i.e., deleting row counter]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Nale with the method/system of Chu to include the limitation(s), deleting the row counter corresponding to the row address from the CAM, where one would have been motivated for resting the a row activation count of the hammer address of the memory by evicting/removing the row address as a refreshing technique, in completing the teaching of all the limitations as a whole (Nale: pars 0043-0044, 0055).
As to claim 22, the combination of Chu and Nale teaches the method of claim 1,
Nale further teaches further comprising, responsive to determining that the first count is greater than the RHT minus the second count, deleting the row counter corresponding to the row address from the CAM (Nale: pars 0016-0017, discloses a memory device with row hammer tracking a managing row address count. Pars 0043-0044, 0055, teaches leaving the row address in address storage until the number of accesses reaches M−1 [i.e., minus a second count], and evicting row address before it reaches M−1 [i.e., deleting row counter]. Indicate not to increment and remove the address when the address is found in address storage [i.e., deleting row counter]).
As to claim 23, the combination of Chu and Nale teaches the method of claim 1,
Chu and Nale further teaches further comprising initializing a plurality of CDCs including the CDC to 0 prior to receipt of the row activation command (Chu: par 0074, matching signal MAT having zero values).
As to claim 24, the combination of Chu and Nale teaches the method of claim 1,
Chu further teaches wherein incrementing the first count of the row counter includes incrementing the first count of the row counter responsive to determining that the row counter is stored in the CAM (Chu: pars 0007, 0009, 0055, 0068-0072, the counter increases a counting value corresponding to the target row address. Store counting values associated with a hammer address associated with at least one memory cell row of the memory device).
As to claim 25, the combination of Chu and Nale teaches the method of claim 1,
Nale further teaches further comprising setting a size of the CAM based on a frequency target for row activation commands (Nale: pars 0016-0017, 0055, discloses a memory device with row hammer tracking a managing row address count, and resetting count value).
As to claim 26, the combination of Chu and Nale teaches the method of claim 1,
Nale further teaches further comprising setting the size of the CAM based on a frequency target for row activation commands that is less than the RHT (Nale: par 0056-0057 count value is compared to a threshold value for an activation command).
As to claim 27, the combination of Chu and Nale teaches the method of claim 1,
Nale further teaches further comprising setting a size of the CAM based on a maximum quantity of row activations for a particular period (Nale: pars 0016-0017, 0055, managing row address count, and resetting count value).
As to claim 28, Chu teaches an apparatus, comprising: a content addressable memory (CAM); a memory device; and control circuitry coupled to the memory device (Chu: pars 0008-010, discloses a method and system for managing content-addressable memory (CAM) system efficiently performing a hammer refresh operation), and configured to:
receive a row activation command having a row address of the memory device (Chu: pars 0008-0010; Fig. 1, 6, receiving and performing command protocol for a row hammer management circuit to count each of access addresses associated with accesses to a plurality of memory cell rows of the semiconductor memory device to store counting values therein and for determining a hammer address associated with at least one memory cell row);
responsive to determining that a row counter corresponding to the row address is stored in the CAM, increment a first count of the row counter (Chu: pars 0009, 0068-0072, the counter increases a counting value corresponding to the target row address);
determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC) (Chu: pars 0009, 0068-0072, counting value of the target row address being equal to or greater than first reference number NTH1 [i.e., row hammer threshold] and smaller than the second reference number NTH2 [i.e., minus a second count]); and
responsive to determining that the first count is greater than the RHT minus the second count (Chu: pars 0071-0072, in response to counting value of the target row address being equal to or greater than first reference number, a signal is provided to a scheduler to adjust the hammer address).
Chu does not explicitly teach the limitation, issue a refresh command to the row address; and delete the row counter corresponding to the row address from the CAM.
However, in an analogous art, Nale teaches the limitation, issue a refresh command to the row address; and delete the row counter corresponding to the row address from the CAM (Nale: pars 0016-0017, discloses a memory device with row hammer tracking a managing row address count. Pars 0043-0044, 0055, teaches leaving the row address in address storage until the number of accesses reaches M−1 [i.e., minus a second count], and evicting row address before it reaches M−1 [i.e., deleting row counter]. Indicate not to increment and remove the address when the address is found in address storage [i.e., deleting row counter]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Nale with the method/system of Chu to include the limitation(s), issue a refresh command to the row address; and delete the row counter corresponding to the row address from the CAM, where one would have been motivated for resting the a row activation count of the hammer address of the memory by evicting/removing the row address as a refreshing technique, in completing the teaching of all the limitations as a whole (Nale: pars 0043-0044, 0055).
As to claim 29, the combination of Chu and Nale teaches the apparatus of claim 8,
Chu further teaches wherein the control circuitry is further configured to determine whether the CAM has space to store the row counter responsive to determining that the row counter is not stored in the CAM (Chu: pars 0007, 0055, store counting values associated with a hammer address associated with at least one memory cell row of the memory device).
As to claim 30, the combination of Chu and Nale teaches the apparatus of claim 9,
Chu further teaches wherein the control circuitry is further configured to, responsive to determining that the CAM has space to store the row counter, store the row counter in the CAM (Chu: pars 0050, 0055, memory capacity is considered with respect to the refresh time and command).
As to claim 31, the combination of Chu and Nale teaches the apparatus of claim 9,
Nale further teaches wherein the control circuitry is further configured to, responsive to determining that the CAM does not have space to store the row counter, decrement a plurality of counts of the CAM including the first count (Nale: pars 0043-0044, 0055, leaving the row address in address storage until the number of accesses reaches M−1, and evicting row address before it reaches M−1. Indicate not to increment and remove the address when the address is found in address storage).
As to claim 32, the combination of Chu and Nale teaches the apparatus of claim 11,
Nale further teaches wherein the control circuitry is further configured to, responsive to determining that the CAM does not have space to store the row counter, delete any of the plurality of counts that have a zero value to unassociated a particular row corresponding to a deleted count with the CAM (Nale: pars 0043-0044, 0055, leaving the row address in address storage until the number of accesses reaches M−1, and evicting row address before it reaches M−1. Indicate not to increment and remove the address when the address is found in address storage [i.e., deleting row counter]).
As to claim 33, the combination of Chu and Nale teaches the apparatus of claim 11,
Nale further teaches wherein the control circuitry is further configured to, responsive to determining that the CAM does not have space to store the counter, increment the second count of the CDC (Nale: pars 0043-0044, 0055, leaving the row address in address storage until the number of accesses reaches M−1, and evicting row address before it reaches M−1. indicate incrementing by M (e.g., 3 or 4), and then leaving the row address in address storage until the number of accesses reaches M−1).
As to claim 34, Chu teaches an apparatus, comprising: a content addressable memory (CAM); a memory device; control circuitry coupled to the memory device (Chu: pars 0008-010, discloses a method and system for managing content-addressable memory (CAM) system efficiently performing a hammer refresh operation), and configured to:
receive a row activation command directed to a row address of the memory device (Chu: pars 0008-0010; Fig. 1, 6, receiving and performing command protocol for a row hammer management circuit to count each of access addresses associated with accesses to a plurality of memory cell rows of the semiconductor memory device to store counting values therein and for determining a hammer address associated with at least one memory cell row);
determine whether a row counter corresponding to the row address is stored in the CAM (Chu: pars 0007, 0055, store counting values associated with a hammer address associated with at least one memory cell row of the memory device);
responsive to determining that the row counter is not stored in the CAM and to determining that the CAM is full (Chu: pars 0050, 0055, memory capacity is considered with respect to the refresh time and command):
decrement a plurality of row counters stored in the CAM; and increment a second count of a CAM decrease counter (CDC) (Chu: pars 0009, 0068-0072, the counter increases a counting value corresponding to the target row address);
responsive to determining that the row counter corresponding to the row address is stored in the CAM, determine whether a first count of the row counter is greater than a difference between a row hammer threshold (RHT) and the second count of the CDC (Chu: pars 0009, 0068-0072, counting value of the target row address being equal to or greater than first reference number NTH1 [i.e., row hammer threshold] and smaller than the second reference number NTH2 [i.e., minus a second count]); and
responsive to determining that the first count is greater than the difference between the RHT and the second count (Chu: pars 0071-0072, in response to counting value of the target row address being equal to or greater than first reference number, a signal is provided to a scheduler to adjust the hammer address).
Chu does not explicitly teach the limitation, issue a refresh command to the row address.
However, in an analogous art, Nale teaches the limitation, issue a refresh command to the row address (Nale: pars 0016-0017, discloses a memory device with row hammer tracking a managing row address count. Pars 0043-0044, 0055, teaches leaving the row address in address storage until the number of accesses reaches M−1 [i.e., minus a second count], and evicting row address before it reaches M−1 [i.e., deleting row counter]. Indicate not to increment and remove the address when the address is found in address storage [i.e., deleting row counter] as a reset of refresh process).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Nale with the method/system of Chu to include the limitation(s), issue a refresh command to the row address, where one would have been motivated for deleting the row counter corresponding to the row address from the CAM for resting the a row activation count of the hammer address of the memory by evicting/removing the row address as a refreshing technique, in completing the teaching of all the limitations as a whole (Nale: pars 0043-0044, 0055).
As to claim 35, the scope of the claim limitation is similar to the scope of claim 22, and rejected for the same reason set forth above for claim 22.
As to claim 38, the scope of the claim limitation is similar to the scope of claims 23 and 31, in combination, and rejected for the same reason set forth above for claims 23 and 31.
As to claims 36, 37, 39, and 40, the scope of the claim limitation is similar to the scope of claims 29, 31, 32, and 33, respectively, and rejected for the same reason set forth above for claims 29, 31, 32, and 33.
Conclusion
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Jahangir Kabir whose telephone number is (571) 270-3355. The Examiner can normally be reached on 9:00- 5:00 Mon-Thu.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Luu Pham can be reached on (571) 270-5002. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAHANGIR KABIR/ Primary Examiner, Art Unit 2439