DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
This application discloses and claims only subject matter disclosed in prior Application No. 17/323,707, filed 5/18/21, and names the inventor or at least one joint inventor named in the prior application. Accordingly, this application may constitute a continuation or divisional. Should applicant desire to claim the benefit of the filing date of the prior application, attention is directed to 35 U.S.C. 120, 37 CFR 1.78, and MPEP § 211 et seq. The presentation of a benefit claim may result in an additional fee under 37 CFR 1.17(w)(1) or (2) being required, if the earliest filing date for which benefit is claimed under 35 U.S.C. 120, 121, 365(c), or 386(c) and 1.78(d) in the application is more than six years before the actual filing date of the application.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 5-7, 9, 11, 12, 16 and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5, 6,9 and 10 of U.S. Patent No. 12,068,315 B2 (Do et al). Although the claims at issue are not identical, they are not patentably distinct from each other because the claimed subject matter of claims 1, 5-7, 9, 11, 12, 16 and 17 of the instant application may be found in claims 1-3, 5, 6, 9 and 10 of the patent.
Regarding claim 1, Do et al 315’ discloses A semiconductor device comprising: a substrate comprising a first dummy region and a second dummy region spaced apart from the first dummy region; a device isolation layer provided in a trench between the first dummy region and the second dummy region; a first dummy electrode provided on the first dummy region; a second dummy electrode provided on the second dummy region; a power line extending from the first dummy region to the second dummy region, the power line comprising an expanded portion provided on the device isolation layer, a width of the expanded portion being larger than a line width of a remaining portion of the power line; a power delivery network provided on a bottom surface of the substrate; and a through via extending through the substrate and the device isolation layer, and electrically connecting the power delivery network to the expanded portion, wherein the through via and the expanded portion vertically overlap (claim 1, 2 and 6).
Regarding claim 5, Do et al 315’ discloses further comprising a well contact connected to at least one of the first dummy region and the second dummy region, wherein the well contact is connected to the power line (claim 9).
Regarding claim 6, Do et al 315’ discloses further comprising a spacer provided on a side surface of the through via, wherein the spacer comprises a liner, which extends along the side surface of the through via, and a plurality of scallops, which protrude from the liner (claim 5).
Regarding claim 7, Do et al 315’ discloses wherein a thickness of the liner is 10 to 30 times a largest width of the plurality of scallops (claim 5).
Regarding claim 9, Do et al 315’ discloses wherein the width of the expanded portion is 3 to 10 times the line width of the remaining portion of the power line (claim 3).
Regarding claim 11, Do et al 315’ discloses A semiconductor device comprising: a substrate comprising a first dummy region and a second dummy region spaced apart from the first dummy region; a device isolation layer provided in a trench between the first dummy region and the second dummy region; a power line extending from the first dummy region to the second dummy region; a power delivery network provided on a bottom surface of the substrate; a through via extending through the substrate and the device isolation layer, and electrically connecting the power delivery network to the power line; and a spacer provided on a side surface of the through via, wherein the spacer comprises a liner, which extends along the side surface of the through via, and a plurality of scallops, which protrude from the liner (claim 1, 5 and 6).
Regarding claim 12, Do et al 315’ discloses wherein a thickness of the liner is 10 to 30 times a largest width of the plurality of scallops (claim 5).
Regarding claim 16, Do et al 315’ discloses A semiconductor device comprising: a substrate; first power lines and second power lines provided on the substrate, the first power lines and the second power lines being alternately arranged in a first direction and extending in a second direction; first tap cells provided on a first tap cell track of the substrate which extends in the first direction; second tap cells provided on a second tap cell track of the substrate which extends in the first direction; logic cells provided on the substrate between the first tap cell track and the second tap cell track; and a power delivery network provided on a bottom surface of the substrate, wherein the first tap cell track and the second tap cell track are spaced apart from each other in the second direction, wherein each of the first tap cells comprises a first through via which extends through the substrate and electrically connects the power delivery network to a corresponding one of the first power lines, and wherein each of the second tap cells comprises a second through via which extends through the substrate and electrically connects the power delivery network to a corresponding one of the second power lines (claims 1 and 10).
Regarding claim 17, Do et al 315’ discloses wherein each of the first power lines comprises a first expanded portion provided on a first device isolation layer of a corresponding first tap cell, wherein each of the second power lines comprises a second expanded portion provided on a second device isolation layer of a corresponding second tap cell, wherein the first through via is connected to the first expanded portion, and wherein the second through via is connected to the second expanded portion (claim 2).
Allowable Subject Matter
Claims 2-4, 8, 10, 13-15 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art does not disclose nor fairly suggest semiconductor devices comprising: wherein a recess region is formed in a bottom surface of the expanded portion, and wherein an upper portion of the through via is provided in the recess region (claim 2), wherein the first dummy electrode comprises a plurality of first dummy electrodes arranged with a uniform pitch, and wherein the width of the expanded portion is 1.5 to 7 times the uniform pitch between the plurality of first dummy electrodes (claim 4), wherein an angle between a side surface of the through via and the bottom surface of the substrate is range from 85° to 89.5° (claim 8), , wherein the through via is configured to apply a voltage from the power delivery network to the power line (claim 10) all combined and further incorporated into independent claim 1, wherein the power line includes a recess region defined where the through via contacts the power line (claim 13) and wherein an angle between the side surface of the through via and the bottom surface of the substrate is range from 85° to 89.5° (claim 15) combined and further incorporated into independent claim 11 and wherein one of the first tap cells further comprises: a first dummy region comprising a first active pattern; a second dummy region comprising a second active pattern; a device isolation layer provided in a trench between the first dummy region and the second dummy region; a first source/drain pattern provided on the first active pattern; and a second source/drain pattern provided on the second active pattern, and wherein the first through via extends through the device isolation layer (claim 18) and further comprising a device isolation layer, which is provided on the substrate in a trench between active regions which are adjacent to each other, wherein each of the first power lines and the second power lines comprises a buried power line which is buried in the device isolation layer and extends in the second direction (claim 20), combined and further incorporated into independent claim 16, all in the context of their recited apparatuses, along with their depending claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MONICA D HARRISON whose telephone number is (571)272-1959. The examiner can normally be reached M-F 7-4:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MONICA D HARRISON/Primary Examiner, Art Unit 2815
mdh
September 10, 2026
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