Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1, 4-6, 8-21, and 23-24 are pending.
Priority
3. Acknowledgment is made of applicant's claim for foreign priority based on an application filed in South Korea on 8/19/2024. Applicant remarked 1/26/2026 that a new request was sent on 1/22/2026. However, as of the time of this writing no retrieval or filing of the certified copy of the 10-2023-0119213 application has been received, as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 8-13 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Kim (US Patent Application Publication 2020/0184902).
Regarding independent claim 1, Kim discloses a display device (Figure 1 paragraph [0038] describes an organic light emitting display.) comprising:
a display panel (150) including a plurality of pixels (Figure 2 SP) ([0046]-[0048]);
a data driver (Figure 1 140 and/or 180. Figure 6 140a output from 140 and EVDD output from 180) configured to apply, in a sensing mode (Figure 6 and paragraphs [0067]-[0068] describes when switch SASW is turned on, under control of signal SAM, sensing the characteristics of the sub-pixel. Therefore, when SASW is on is interpreted as the sensing mode.), at least one of a first reference data voltage corresponding to a low current sensing point and a second reference data voltage corresponding to a high current sensing point to the display panel (Figure 11 and paragraph [0075] describes EVDD to be varied and require correction depicted in an overcompensation range of about 80% in the sensed value (corresponding to a lower current sensed point) and varied (second value) up to about 115% (corresponding to a higher current sensed point). Additionally, in view of figure 6 DAC 140a output, paragraph [0063] describes DAC to output voltages (plurality) one exampled as black voltage required for compensation. This describes at least two voltages such that one voltage is larger than the other.).
a current sensor (140b) configured to:
in the sensing mode ([0067]-[0068]),
lower a high potential driving voltage (EVDD) supplied to the display panel ([0074]);
sense a first driving current of the display panel (Paragraph [0067] describes SASW to sense characteristics of the pixel based on current, voltage, charge stored in Vsen.) under a lowered driving voltage (Paragraph [0074] describes to have a varied lower EVDD during the sensing mode/operation. Paragraph [0075] describes the first voltage to be varied as shown in figure 11 including a 85% variation up to 115% variation between the two values.) and the first reference data and convert (ADC) the first driving current (output by SASW) into first sensing data (Paragraph [0075] describes the two values (including first and second driving currents) of figure 11 variation are sensed from the charge AQ stored in the capacitor COLED (figure 8) under the varied first voltage EVDD (including first and second reference data) is converted by the ADC (paragraph [0068].); and
sense a second driving current of the display panel under the lowered driving voltage (Paragraph [0074] describes to have a varied lower EVDD during the sensing mode/operation. Paragraph [0075] describes the first voltage to be varied as shown in figure 11 including a 85% variation up to 115% variation between the two values.) and the second reference data voltage and convert (ADC) the second driving current (output by SASW) into second sensing data (Paragraph [0075] describes the two values (including first and second driving currents) of figure 11 variation are sensed from the charge AQ stored in the capacitor COLED (figure 8) under the varied first voltage EVDD (including first and second reference data) is converted by the ADC (paragraph [0068].); and
a controller (160/167 or 120 in figure 7) configured to:
calculate a first compensation factor corresponding to threshold voltage characteristics of a driving transistor and a second compensation factor corresponding to electron mobility characteristics of the driving transistor based on the first sensing data and the second sensing data (Paragraph [0067] describes the sensed characteristics correspond to threshold voltage or mobility of the driving transistor DT by sampling (sensing).);
generate compensation data based on the first compensation factor and the second compensation factor (Figure 7 compensation circuit 160 described in paragraph [069] to generate a compensation value based on the sensed values.); and
compensate image data using the compensation data in a display mode (Paragraph [0070] describes to supply the data driver 130 with the compensated data signal CDATA. Figure 10 and paragraph [0072] describes the display before and after compensation.).
Regarding claim 4, Kim discloses the display device of claim 1, wherein the current sensor is further configured to sense the first driving current and the second driving current corresponding to at least one of the low current sensing point and the high current sensing point based on a preset block basis of the display panel, each block comprising a plurality of pixels (Figure 4 and paragraph [0057] describes VREF1 (figure 6 depicts Vref1 connected to SASW for sensing) connected and shared with four subpixels SP1-SP4 (preset block basis of sensing).).
Regarding claim 8, Kim discloses the display device of claim 1, wherein the controller is configured to calculate the first compensation factor and the second compensation factor based on a preset block basis of the display panel, each block comprising a plurality of pixels (Figure 4 and paragraph [0057] describes VREF1 (figure 6 depicts Vref1 connected to SASW for sensing) connected and shared with four subpixels SP1-SP4 (preset block basis of sensing).), and the controller is configured to store the first compensation factor and the second compensation factor in a memory (Paragraph [0079] describes to obtain sensing values of the OLED/DT and EVDD and to write them to memory as a look up table. Paragraph [0080] describes producing the compensation values from the LUT.).
Regarding claim 9, Kim discloses the display device of claim 8, wherein in the display mode, the controller is configured to generate the compensation data based on the first compensation factor and the second compensation factor stored in the memory (Paragraph [0079] describes to obtain sensing values of the OLED/DT and EVDD and to write them to memory as a look up table. Paragraph [0080] describes producing the compensation values from the LUT.), and is configured to compensate for the image data using the compensation data (Figure 13 S150 and paragraph [0081] describes to apply the compensation.).
Regarding claim 10, Kim discloses the display device of claim 1, wherein the display device operates in the sensing mode for a preset time duration when the display device is powered on or off ([0032]).
Regarding independent claim 11, Kim discloses a method for compensating for degradation of a display device (paragraphs [0032] and [0034]), the method comprising:
in a sensing mode (Figure 6 and paragraphs [0067]-[0068] describes when switch SASW is turned on, under control of signal SAM, sensing the characteristics of the sub-pixel. Therefore, when SASW is on is interpreted as the sensing mode.), applying a first reference data voltage corresponding to a low current sensing point to the display panel (Figure 11 and paragraph [0075] describes EVDD to be varied and require correction depicted in an overcompensation range of about 80% in the sensed value (corresponding to a lower current sensed point) and varied (second value) up to about 115% (corresponding to a higher current sensed point). Additionally, in view of figure 6 DAC 140a output, paragraph [0063] describes DAC to output voltages (plurality) one exampled as black voltage required for compensation. This describes at least two voltages such that one voltage is larger than the other.).
in the sensing mode, applying a first reference data voltage corresponding to a low current sensing point to the display panel (Paragraph [0063] describes the data voltage output part DAC (140a in figure 6) may output a plurality of voltages such as black voltage etc. required for compensation (during the sensing mode) and/or Figure 11 and paragraph [0075] describes EVDD to be varied and require correction depicted in an overcompensation range of about 80% in the sensed value (corresponding to a lower current sensed point).);
sensing a first driving current of the display panel (Paragraph [0067] describes SASW to sense characteristics of the pixel based on current, voltage, charge stored in Vsen.) under a lowered driving voltage (Paragraph [0074] describes to have a varied lower EVDD during the sensing mode/operation. Paragraph [0075] describes the first voltage to be varied as shown in figure 11 including a 85% variation up to 115% variation between the two values.);
converting (Figure 6 ADC) the first driving current (output by SASW) into first sensing data (ADC output) (Paragraphs [0069]-[0070] describes timing controller 120 to supply data driver 130 with the compensated data signal CDATA, calculated from ADC output.);
in the sensing mode (SASW on), applying a second reference data voltage corresponding to a high current sensing point to the display panel (Figure 11 and paragraph [0075] describes EVDD to be varied and require correction depicted in an overcompensation range of about 80% in the sensed value (corresponding to a lower current sensed point) and varied (second value) up to about 115% (corresponding to a higher current sensed point). Additionally, in view of figure 6 DAC 140a output, paragraph [0063] describes DAC to output voltages (plurality) one exampled as black voltage required for compensation. This describes at least two voltages such that one voltage is larger than the other.);
sensing a second driving current of the display panel under the lowered driving voltage (Paragraph [0074] describes to have a varied lower EVDD during the sensing mode/operation. Paragraph [0075] describes the first voltage to be varied as shown in figure 11 including a 85% variation up to 115% variation between the two values.) and the second reference data voltage and convert (ADC) the second driving current (output by SASW) into second sensing data (Paragraph [0075] describes the two values (including first and second driving currents) of figure 11 variation are sensed from the charge AQ stored in the capacitor COLED (figure 8) under the varied first voltage EVDD (including first and second reference data) is converted by the ADC (paragraph [0068].); and
converting (ADC) the second driving current into second sensing data (ADC output at different time corresponding to the other of EVDD variation sensing or other DAC output voltage.);
calculating a first compensation factor corresponding to threshold voltage characteristics of a driving transistor and a second compensation factor corresponding to electron mobility characteristics of the driving transistor based on the first sensing data and the second sensing data (Paragraph [0067] describes the sensed characteristics correspond to threshold voltage or mobility of the driving transistor DT by sampling (sensing).); and
in a display mode, generating compensation data based on the first compensation factor and the second compensation factor, and compensating for image data using the compensation data (Paragraphs [0034] and [0067] describes to compensate for variation in the mobility/threshold voltage of the driving transistor and OLED. Figures 10-11 and paragraphs [0071]-[0073] describes compensating the amount of charge decreased due to degradation depicted in the before and after (display mode) compensation images.).
Regarding claim 12, Kim discloses the method of claim 11, wherein the sensing of the first driving current and the sensing the second driving current are performed on a preset block basis of the display panel, each block comprising a plurality of pixels (Figure 4 and paragraph [0057] describes VREF1 (figure 6 depicts Vref1 connected to SASW for sensing) connected and shared with four subpixels SP1-SP4 (preset block basis of sensing).), at the low current sensing point and at the high current sensing point respectively (Figure 11 and paragraph [0075] describes EVDD to be varied and require correction depicted in an overcompensation range of about 80% in the sensed value (corresponding to a lower current sensed point) and varied (second value) up to about 115% (corresponding to a higher current sensed point). Additionally, in view of figure 6 DAC 140a output, paragraph [0063] describes DAC to output voltages (plurality) one exampled as black voltage required for compensation. This describes at least two voltages such that one voltage is larger than the other.).
Regarding claim 13, Kim discloses the method of claim 12, wherein the calculating of the first compensation factor (Figure 6 167 output) and the second compensation factor (EVDD correction) is performed on the preset block basis of the display panel (Figure 4 and paragraph [0057] describes VREF1 (figure 6 depicts Vref1 connected to SASW for sensing) connected and shared with four subpixels SP1-SP4 (preset block basis of sensing).).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Imai (US Patent Application Publication 2022/0085782) in view of Park (US Patent Application Publication 2022/0139332).
Regarding claim 5, Kim discloses the display device of claim 1, wherein the current sensor includes:
[ ] configured to transmit the high potential driving voltage to the display panel in the display mode and transmit the high potential driving voltage [ ] in the sensing mode (Paragraph [0074]);
[ ] configured to lower the high potential driving voltage transmitted thereto through [ ] to a voltage level where the driving current is capable of being sensed (Paragraph [0074] describes to lower the level of the voltage in the sensing operation.); and
an analog-to-digital converter configured to sense the driving current based on a voltage [ ] and configured to convert the sensed driving current into the sensing data (ADC output).
Kim discloses the method of lowering the driving voltage EVDD during the sensing operation without disclosing how, including a switch and shunt resistor.
Imai discloses a shunt resistor configured to lower the high potential driving voltage (paragraph [0025]).
It would have been obvious to try for one skilled in the art before the effective filing date of the current application to enable Kim’s high potential driving voltage lowered in the sensing mode with the known technique of a shunt resistor to lower the voltage yielding the predictable results of performing the disclosed method of lowering the voltage as disclosed by Imai (paragraph [0025]).
Park discloses a switch (Figure 10 M4+M6) configured to transmit the high potential driving voltage (EVDD_1) to the display panel (150) in the display mode (Figure 9 period before t1 when EVSS is not EVSS_high as described in paragraph [0089].) and transmit a second high potential driving voltage (EVDD_2) [ ] in the sensing mode (Paragraph [0113] describes the sensing mode to include t1-t4, figure 9, when the second lower voltage EVDD_2 is applied.).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Kim-Imai shunt resistor lowered driving voltage with the known technique of a switch configured to transmit the high potential driving voltage to the display panel in the display mode and transmit the high potential driving voltage to the shunt resistor in the sensing mode yielding the predictable results of providing a plurality of generated voltages to the display as disclosed by Park (paragraph [0114]).
6. Claim(s) 6 and 14-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chen et al. (US Patent Application Publication 2021/0012719), herein after referred to as Chen.
Regarding claim 6, Kim discloses the display device of claim 1, wherein each of the plurality of pixels (Figure 6) includes:
a light-emitting element (OLED) comprising an anode electrode and a cathode electrode ([0053]), the light-emitting element being configured to emit light in response to the driving current ([0046]-[0048]);
the driving transistor (DT) comprising a gate electrode and a source electrode, the driving transistor being configured to control the driving current and connected to the anode electrode of the light-emitting element and a high-potential power line (EVDD) ([0052]);
a capacitor (CST) connected to the gate electrode and the source electrode of the driving transistor (Paragraphs [0036] and [0052] describes first/second electrode connections of DT and drain/source are interchangeable.);
[ ];
a second transistor (SW) configured to apply a data voltage (Vdata) corresponding to the image data or the reference data voltage ([0063]) to the gate electrode of the driving transistor (DT) in response to a scan signal (GL1a) ([0052]); and
a third transistor (ST) configured to apply a reference voltage (VREF1) to the source electrode of the driving transistor (DT) in response to a sensing signal (GL1b) ([0054]).
Kim does not specifically disclose a first transistor configured to initialize the gate electrode of the driving transistor in response to an initialization signal.
Chen discloses a first transistor (Figure 1 T2) configured to initialize (VINI) the gate electrode (g) of the driving transistor (T0) in response to an initialization signal (Scan2) ([0050]).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Kim’s pixel circuit with the known technique of a first transistor configured to initialize the gate electrode of the driving transistor in response to an initialization signal yielding the predictable results of resetting the potential of the gate electrode of the driving transistor as disclosed by Chen (paragraph [0050]).
Regarding independent claim 14, Kim discloses a display device (Figure 1 paragraph [0038] describes an organic light emitting display.) comprising:
a display panel (150) including a plurality of pixels (Figure 2 SP) ([0046]-[0048]);
a data driver (Figure 1 140 and/or 180. Figure 6 140a output from 140 and EVDD output from 180) configured to apply, in a sensing mode (Figure 6 and paragraphs [0067]-[0068] describes when switch SASW is turned on, under control of signal SAM, sensing the characteristics of the sub-pixel. Therefore, when SASW is on is interpreted as the sensing mode.), at least one of a first reference data voltage corresponding to a low current sensing point and a second reference data voltage corresponding to a high current sensing point to the display panel (Figure 11 and paragraph [0075] describes EVDD to be varied and require correction depicted in an overcompensation range of about 80% in the sensed value (corresponding to a lower current sensed point) and varied (second value) up to about 115% (corresponding to a higher current sensed point). Additionally, in view of figure 6 DAC 140a output, paragraph [0063] describes DAC to output voltages (plurality) one exampled as black voltage required for compensation. This describes at least two voltages such that one voltage is larger than the other.).
a current sensor (140b) configured to:
in the sensing mode,
lower a high potential driving voltage (EVDD) supplied to the display panel ([0074]);
sense a first driving current of the display panel (Paragraph [0067] describes SASW to sense characteristics of the pixel based on current, voltage, charge stored in Vsen.) under a lowered driving voltage (Paragraph [0074] describes to have a varied lower EVDD during the sensing mode/operation. Paragraph [0075] describes the first voltage to be varied as shown in figure 11 including a 85% variation up to 115% variation between the two values.) and the first reference data and convert (ADC) the first driving current (output by SASW) into first sensing data (Paragraph [0075] describes the two values (including first and second driving currents) of figure 11 variation are sensed from the charge AQ stored in the capacitor COLED (figure 8) under the varied first voltage EVDD (including first and second reference data) is converted by the ADC (paragraph [0068].); and
sense a second driving current of the display panel under the lowered driving voltage (Paragraph [0074] describes to have a varied lower EVDD during the sensing mode/operation. Paragraph [0075] describes the first voltage to be varied as shown in figure 11 including a 85% variation up to 115% variation between the two values.) and the second reference data voltage and convert (ADC) the second driving current (output by SASW) into second sensing data (Paragraph [0075] describes the two values (including first and second driving currents) of figure 11 variation are sensed from the charge AQ stored in the capacitor COLED (figure 8) under the varied first voltage EVDD (including first and second reference data) is converted by the ADC (paragraph [0068].); and
wherein each of the plurality of pixels (Figure 6) includes:
a light-emitting element (OLED) comprising an anode electrode and a cathode electrode ([0053]), the light-emitting element being configured to emit light in response to the driving current ([0046]-[0048]);
a driving transistor (DT) comprising a gate electrode and a source electrode, the driving transistor being configured to control the driving current and connected to the anode electrode of the light-emitting element and a high-potential power line (EVDD) ([0052]);
a capacitor (CST) connected to the gate electrode and the source electrode of the driving transistor (Paragraphs [0036] and [0052] describes first/second electrode connections of DT and drain/source are interchangeable.);
[ ];
a second transistor (SW) configured to apply a data voltage (Vdata) corresponding to the image data or the reference data voltage ([0063]) to the gate electrode of the driving transistor (DT) in response to a scan signal (GL1a) ([0052]); and
a third transistor (ST) configured to apply a reference voltage (VREF1) to the source electrode of the driving transistor (DT) in response to a sensing signal (GL1b) ([0054]).
Kim does not specifically disclose a first transistor configured to initialize the gate electrode of the driving transistor in response to an initialization signal.
Chen discloses a first transistor (Figure 1 T2) configured to initialize (VINI) the gate electrode (g) of the driving transistor (T0) in response to an initialization signal (Scan2) ([0050]).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Kim’s pixel circuit with the known technique of a first transistor configured to initialize the gate electrode of the driving transistor in response to an initialization signal yielding the predictable results of resetting the potential of the gate electrode of the driving transistor as disclosed by Chen (paragraph [0050]).
Regarding claim 15, Kim and Chen discloses the display device of claim 14, wherein in a first initialization period of the sensing mode (Chen: paragraph [0050] to initialize to reset the gate potential before operation/driving (in combination with Kim before sensing).), the second transistor (Kim: Figure 6 SW) is configured to apply the first reference data voltage corresponding to the low current sensing point (Kim: Paragraph [0063] black voltage) to the gate electrode of the driving transistor (DT), and the third transistor (Kim: figure 6 ST) is configured to apply the reference voltage (Kim: figure 6 VREF1) to the source electrode of the driving transistor (Kim: Paragraphs [0036] and [0052] describes first/second electrode connections of DT and drain/source are interchangeable.).
Regarding claim 16, Kim discloses the display device of claim 15, wherein in a first sensing period of the sensing mode, the second transistor (Figure 6 SW) is turned off (via GL1a), the third transistor (ST) is maintained at a turned-on state ([0054]), and the current sensor (140b) is configured to sense a first driving current (Paragraph [0067] describes SASW to sense characteristics of the pixel based on current, voltage, charge stored in Vsen.) while the first reference data voltage is applied (Paragraph [0063] black voltage).
Regarding claim 17, Kim discloses the display device of claim 14, wherein in a second initialization period of the sensing mode, the second transistor (Figure 6 SW) is configured to apply the second reference data voltage corresponding to the high current sensing point to the gate electrode of the driving transistor (Figure 11 and paragraph [0075] describes EVDD to be varied and require correction depicted in an overcompensation range of about 80% in the sensed value (corresponding to a lower current sensed point) and varied (second value) up to about 115% (corresponding to a higher current sensed point).), and the third transistor (Figure 6 ST) is configured to apply the reference voltage (VREF1) to the source electrode of the driving transistor ([0054]).
Regarding claim 18, Kim discloses the display device of claim 17, wherein in a second sensing period of the sensing mode, the second transistor (Figure 6 SW) is turned off (via GL1a), the third transistor (ST) is maintained at a turned-on state ([0054]), and the current sensor (140b) is configured to sense the second driving current while the second reference data voltage is applied (Paragraph [0075] describes a need to control or correct the power supply (first sensed data) or take the variation into account in a compensation operation (second sensed data).).
Regarding claim 19, Kim discloses the display device of claim 14, wherein the display device further comprises a controller (Figure 7 120) configured to:
receive the first sensing data and second sensing data respectively corresponding to the low current sensing point and the high current sensing point from the current sensor (Figure 11 and paragraph [0075] describes EVDD to be varied and require correction depicted in an overcompensation range of about 80% in the sensed value (corresponding to a lower current sensed point) and varied (second value) up to about 115% (corresponding to a higher current sensed point).); and
calculating a first compensation factor corresponding to threshold voltage characteristics of the driving transistor and a second compensation factor corresponding to electron mobility characteristics of the driving transistor (Paragraph [0067] describes the sensed characteristics correspond to threshold voltage or mobility of the driving transistor DT by sampling (sensing).), based on the first sensing data and the second sensing data, respectively (Figure 11 and paragraph [0075] describes EVDD to be varied and require correction depicted in an overcompensation range of about 80% in the sensed value (corresponding to a lower current sensed point) and varied (second value) up to about 115% (corresponding to a higher current sensed point).).
Regarding claim 20, Kim discloses the display device of claim 19, wherein the controller is configured to generate compensation data (Figure 7 CDATA) based on the first compensation factor and the second compensation factor (Paragraphs [0069] and [0075] describes to generate compensation data CDATA based on the sensed values including values regarding the variation of EVDD.), and is configured to compensate for the image data based on the generated compensation data (Figure 13 S150 and paragraph [0081] describes to apply the compensation.).
7. Claim(s) 21 and 23-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Jang et al. (US Patent Application Publication 2024/0355281), herein after referred to as Jang.
Regarding independent claim 21, Kim discloses a display device (Figure 1 paragraph [0038] describes an organic light emitting display.) comprising:
a display area (150) comprising at least one light-emitting element (Figure 1 SP depicted in figure 6 to comprise an OLED.);
a non-display area disposed outside of the display area (Figure 1 area not 150);
at least one thin-film transistor [ ] (Figure 6/7 DT.);
[ ]; and
a data driver (Figure 1 140 and/or 180. Figure 6 140a output from 140 and EVDD output from 180) configured to apply, in a sensing mode (Figure 6 and paragraphs [0067]-[0068] describes when switch SASW is turned on, under control of signal SAM, sensing the characteristics of the sub-pixel. Therefore, when SASW is on is interpreted as the sensing mode.), at least one of a first reference data voltage corresponding to a low current sensing point and a second reference data voltage corresponding to a high current sensing point (Figure 11 and paragraph [0075] describes EVDD to be varied and require correction depicted in an overcompensation range of about 80% in the sensed value (corresponding to a lower current sensed point) and varied (second value) up to about 115% (corresponding to a higher current sensed point). Additionally, in view of figure 6 DAC 140a output, paragraph [0063] describes DAC to output voltages (plurality) one exampled as black voltage required for compensation. This describes at least two voltages such that one voltage is larger than the other.);
a current sensor (140b) configured to, in the sensing mode ([0067]-[0068]), lower a high potential driving voltage (EVDD) supplied to the display panel ([0074]), sense a first driving current and second driving current (Paragraph [0067] describes SASW to sense characteristics of the pixel based on current, voltage, charge stored in Vsen.) corresponding to the first reference data voltage and the second reference data voltage (Paragraph [0074] describes to have a varied lower EVDD during the sensing mode/operation. Paragraph [0075] describes the first voltage to be varied as shown in figure 11 including a 85% variation up to 115% variation between the two values.), respectively, and convert the sensed first and second driving currents into sensing data (Paragraph [0075] describes the two values (including first and second driving currents) of figure 11 variation are sensed from the charge AQ stored in the capacitor COLED (figure 8) under the varied first voltage EVDD (including first and second reference data) is converted by the ADC (paragraph [0068].); and
a controller (Figure 7 120) configured to receive the sensing data, and calculate a compensation factor based on the sensing data (Paragraph [0067] describes the sensed characteristics correspond to threshold voltage or mobility of the driving transistor DT by sampling (sensing).) and compensate image data based on the calculated compensation factor (Figure 7 compensation circuit 160 described in paragraph [069] to generate a compensation value based on the sensed values.),
wherein the at least one thin-film transistor (DT) is configured to drive the at least one light-emitting element (OLED) based on the compensated image data (Paragraphs [0034] and [0067] describes to compensate for variation in the mobility/threshold voltage of the driving transistor and OLED. Figures 10-11 and paragraphs [0071]-[0073] describes compensating the amount of charge decreased due to degradation depicted in the before and after (display mode) compensation images.).
Kim does not specifically disclose an encapsulation layer configured to block foreign substances from reaching the at least one light-emitting element or the at least one thin-film transistor disposed under the display area.
Jang discloses a display device (Figure 1 10) comprising:
a display area (DA) comprising at least one light-emitting element (UPX comprising light emitting element LEL);
a non-display area (NDA) disposed outside of the display area (DA);
at least one thin-film transistor (Figure 8 DT) disposed under the display area (Figure 1 reference pixel area UPX in display area DA. Figure 3 depicts circuit layer 120 disposed under display area DA. Paragraph [0106] describes circuit layer 120 includes pixel driver PXD. Figure 4 depicts UPX to be a part of several PXD areas. Figure depicts PXD to comprise several TFTs including DT. Figure 8 depicts the layer view of DT disposed under the light emitting layer 130 of the display area DA.);
an encapsulation layer configured to block foreign substances from reaching the at least one light-emitting element (Figure 12 encapsulation layer 140 including three layers 141-143 described in paragraph [0112] to block oxygen/moisture (foreign substances) from permeating (reaching) the light emitting layer 130.); and
[ ],
wherein the at least one thin-film transistor (DT) is configured to drive the at least one light-emitting element (LEL) [ ].
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Kim’s display with the known technique of an encapsulation layer configured to block foreign substances from reaching the at least one light-emitting element and the at least one thin-film transistor disposed under the display area yielding the predictable results of blocking oxygen/moisture from permeating the light emitting layer as disclosed by Jang (paragraph [0112]).
Regarding claim 23, Jang discloses the display device of claim 21, wherein the encapsulation layer comprises:
a first encapsulation layer (Figure 12 141) disposed on the at least one light-emitting element (LEL);
a second encapsulation layer (142) disposed on the first encapsulation layer (141) and configured to absorb external forces to the display device ([0112]); and
a third encapsulation layer (143) disposed on the second encapsulation layer (142) and configured to encapsulate the second encapsulation layer (142) by connecting with the first encapsulation layer (141) ([0259]),
wherein the first encapsulation layer (141), the second encapsulation layer (142), and the third encapsulation layer (143) are each disposed in both the display area (DA) and the non-display area (NDA) (Figure 12 depicts gate lines GL depicted to be within display area DA in figure 9. All encapsulation layers 140: 141-143 are depicted over GL (in DA) and at the DAM described in paragraph [0259] to be in the non-display area NDA.).
Regarding claim 24, Jang discloses the display device of claim 23, further comprising at least one dam (Figure 12 DAM) configured to prevent the second encapsulation layer (142) from reaching an edge of the non-display area (paragraph [0259]).
Response to Arguments
8. Applicant's arguments filed 1/26/2026 have been fully considered and relate towards newly amended subject matter. Previous 112 rejections are withdrawn in view of the newly amended subject matter.
Applicant’s arguments are rebutted seriatim. Kim is found to reject the block basis sensing in view of figure 4 that shares a sense line VREF1 between four subpixels. Kim discloses a first voltage EVDD in paragraph [0074] described to have a varied lower EVDD during the sensing mode/operation. Paragraph [0075] describes the first voltage to be varied as shown in figure 11 including a 85% variation up to 115% variation. This describes the first voltage to comprise a low sensing point and a high sensing point between the varied sensed values of the first voltage.
This action is final necessitated by amendment.
Conclusion
9. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER E LEIBY whose telephone number is (571)270-3142. The examiner can normally be reached 11-7.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached at 571-272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER E LEIBY/Primary Examiner, Art Unit 2621
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