The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claim(s) 1-20 has/have been examined.Claim(s) 3, 6-9, 12, 15-18 is/are objected to as containing novel subject matter while being dependent on rejected base claims.
Claim(s) 1, 2, 4, 5, 10, 11, 13, 14, 19, 20 have been rejected.
Novel Subject Matter
Claim(s) 3, 6-9, 12, 15-18 is/are objected to as reciting novel subject matter while being dependent on rejected base claims.
Within claims 3 and 12, within each claim as a whole the examiner deems the novel limitation to be that the system performs correcting an error occurring in data of M vertical sub-blocks respectively in a plurality of even-numbered wordlines of the superblock based on a wordline-dimension check code data stored in M last pages of M vertical sub-blocks in a last even-numbered wordline of the super block.
Within claims 6 and 15, within each claim as a whole the examiner deems the novel limitation to be that when the result of the first layer wordline dimensional error correction corresponding to the first vertical sub-block of the first wordline is a failure result, triggering and activating a second layer error correction operation to perform a second layer vertical-dimension error correction.
Response to Arguments
Applicant's arguments filed March 23, 2026 have been fully considered but are moot in view of the new grounds of rejection. Due to removal of the term, the rejections based on the terms finger-shaped and finger-dimension are withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 5, 10, 11, 13, 14, 19, 20 are rejected under 35 U.S.C. 103 as being unpatentable Sakaue (PG-PUB 2014/0053041).
Regarding claim 1, Sakaue discloses a flash memory controller (paragraphs 21 and 22, the memory controller is flash memory controller), to be coupled between a host device and a flash memory module (paragraph 24), comprising:
an error correction code circuit, for performing a data reading operation upon specific data of a super block in the flash memory module (see abstract, error correction is performed for a storage area); the super block is composed of a plurality of vertical sub-blocks in a vertical direction and a plurality of wordlines in a horizontal direction (see abstract and Figure 6, the frame is divided among multiple columns); when performing the data reading operation, the error correction code circuit
performs a vertical-dimensional error correction operation upon data of a plurality of vertical sub-blocks in a first wordline of the super block to correct an error occurring in the first wordline (see abstract, column parity correction is performed), and
performs a wordline-dimensional error correction operation upon data of a plurality of wordlines in a first
Sakaue does not expressly disclose the flash memory controller wherein the data rows correspond to wordlines of a super block.
Sakaue teaches that a frame of data may be divided into rows and columns (Figure 9 and that the data of a page is written to memory word lines (paragraph 33).
The examiner takes official notice that it is well-known in the art to utilize wordlines to divide data in memory (see, for example, attached reference related to DRAM).
Prior to the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify the flash memory error correction disclosed by Sakaue such that the rows of data in a frame are stored in a memory as wordline units. This modification would have been obvious because, as would be clear to one of ordinary skill in the art, a wordline of data is a unit used in conventional memory addressing.
Regarding claims 2, 4 and 5, Sakaue discloses:
2. (Currently amended): The flash memory controller of claim 1, wherein the wordline-dimensional error correction code operation and the vertical-dimensional
4. (Currently amended): The flash memory controller of claim 1, wherein the error correction code circuit is used to correct an error occurring in data of an even-numbered plurality of vertical sub-blocks of the first wordline according to a portion of vertical-dimensional check code data stored by a last data page of a last even-numberedpage of a last odd-number vertical sub-block in the first wordline of the super block (Figure 9, an error in a first column is corrected using row parity in each row).
5. (Currently amended): The flash memory controller of claim 1, wherein the error correction code circuit performs a first layer error correction operation to execute a first layer vertical-dimensional error correction upon data of the plurality of vertical sub-blocks in the first wordline (abstract and Figure 9, row error correction is performed on data of multiple columns);
when a result of the first layer vertical-dimensional error correction is a failure result, the error correction code circuit performs a first layer wordline-dimensional error correction upon a first vertical sub-block of the first wordline and
records a result of the first layer wordline-dimensional error correction corresponding to the first vertical sub-block of the first wordline (end of claim 8 of the reference, the data of the error column is corrected).
Regarding claims 10, 11, 13 and 14, these claims recite limitations found in claims 1, 2, 4 and 5, respectively, and are respectively rejected on the same grounds as claims 1, 2, 4 and 5.
Regarding claims 19 and 20, these claims recite limitations found in claims 1 and 5, respectively, and are respectively rejected on the same grounds as claims 1 and 5.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
This action is a final rejection and closes the prosecution of this application. Applicant’s reply under 37 CFR 1.113 to this action is limited to an appeal to the Patent Trial and Appeal Board, an amendment complying with the requirements set forth below, or a request for continued examination (RCE) to reopen prosecution where permitted. Please note that the Office also offers initiatives that are available to applicants after the close of prosecution. See https://www.uspto.gov/patents/initiatives/uspto-patent-applications-iniatives-timeline for more information.
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If applicant should desire to file an after-final amendment, entry of the proposed amendment cannot be made as a matter of right unless it merely cancels claims or complies with a formal requirement made in a previous Office action. Amendments touching the merits of the application which otherwise might not be proper may be admitted upon a showing of good and sufficient reasons why they are necessary and why they were not presented earlier.
A reply under 37 CFR 1.113 to a final rejection must include cancellation of or appeal from the rejection of, each rejected claim. The filing of an amendment after final rejection, whether or not it is entered, does not stop the running of the statutory period for reply to the final rejection unless the examiner holds all of the claims to be in condition for allowance.
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The application will become abandoned unless a Notice of Appeal, an after final reply that places the application in condition for allowance, or an RCE has been filed properly within the period for reply, or any extension of this period obtained under either 37 CFR 1.136(a) or (b).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH SCHELL whose telephone number is (571) 272-8186. The examiner can normally be reached on Monday through Friday 9AM-5:00PM (Pacific Time).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached at (571) 272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. The fax phone number for the examiner is 571-273-8186. The examiner may be e-mailed at joseph.schell@uspto.gov though communications via e-mail are not permitted without a written authorization form (see MPEP 502.03).
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JS/JOSEPH O SCHELL/Primary Examiner, Art Unit 2114