DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Packaging Comprising a Plurality of Chips Stacked to Form a Staircase in Various Directions.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 11, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al (US 12237304).
Regarding Claim 1, Park et al discloses
a semiconductor device (semiconductor package [column 3, lines 28-34] shown in Fig 18B) comprising:
a substrate (package substrate 100 [column 3, lines 34-45] Fig 18B);
one or more first substrate pads (second bonding pads BP2 [column 4, lines 1-9] Fig 18B) provided on the substrate (100 Fig 18B);
one or more first chips (first chips 110 [column 4, lines 17-41] Fig 18B) provided on the substrate (100 Fig 18B) and located in a first direction (-D1 direction Fig 19) from the first substrate pads (BP2 Fig 18B), each of the first chips (110 Fig 18B) including one or more first chip pads (power/ground pads 113 [column 4, lines 28-34] Fig 18B) electrically connected to the first substrate pads (BP2 Fig 18B);
one or more second substrate pads (fourth bonding pads BP4 [column 4, lines 1-9] Fig 18B) provided on the substrate (100 Fig 18B); and
one or more second chips (second chips 120 [column 4, lines 43-67] 120 Fig 18B) provided on the first chips (110 Fig 18B) and located in a second direction (D2 direction Fig 19) from the second substrate pads (BP4 Fig 18B), the second direction (D2 direction Fig 19) intersecting the first direction (-D1 direction Fig 19), each of the second chips (120 Fig 18B) including one or more second chip pads (power ground pads 123 [column 4, lines 56-67] Fig 18B) electrically connected to the second substrate pads (BP4 Fig 18B),
wherein each of the second chip pads (123 Fig 18B) is located to overlap (shown in the combination of Fig 18B and Fig 19) with a highest first chip (110 Fig 18B) of the first chips (110 Fig 18B) in planar view (Fig 19).
Regarding Claim 2, Park et al discloses the limitations of claim 1 as explained above. Park et al further discloses
further comprising: one or more third substrate pads (sixth bonding pads BP6 [column 12, lines 20-32] Fig 18B) provided on the substrate (100 Fig 18B); and
one or more third chips (third chips 130 [column 12, lines 1-6] Fig 18B) provided on the second chips (120 Fig 18B) and located in a third direction (D1 direction Fig 19) from the third substrate pads (BP6 Fig 18B),
the third direction (D1 direction Fig 19) intersecting the second direction (D2 direction Fig 19),
each of the third chips (130 Fig 18B) including one or more third chip pads (power/ground pads 133 [column 13, lines 57-61] Fig 18B) electrically connected to the third substrate pads (BP6 Fig 18B), wherein each of the third chip pads (133 Fig 18B) is located to overlap with a highest second chip (120 Fig 18B) of the second chips (120 Fig 18B) in planar view (Fig 19).
Regarding Claim 3, Park et al discloses the limitations of claim 2 as explained above. Park et al further discloses
further comprising: one or more fourth substrate pads (eighth bonding pads BP8 [column 12, lines 54-67] Fig 18B) provided on the substrate (100 Fig 18B); and
one or more fourth chips (fourth chips 140 [column 13, lines 10-61] Fig 18B) provided on the third chips (130 Fig 18B) and located in a fourth direction (-D2 direction Fig 19) from the fourth substrate pads (BP8 Fig 18B), the fourth direction (-D2 direction Fig 19) intersecting the third direction (D1 direction Fig 19), each of the fourth chips (140 Fig 18B) including one or more fourth chip pads (power/ground pads 143 [column 13, lines 10-61] Fig 18B) electrically connected to the fourth substrate pads (BP8 Fig 18B),
wherein each of the fourth chip pads (143 Fig 18B) is located to overlap with a highest third chip (130 Fig 18B) of the third chips (130 Fig 18B) in planar view (Fig 19).
Regarding Claim 4, Park et al discloses the limitations of claim 1 as explained above. Park et al further discloses
further comprising: one or more third chips (third chips 130 [column 12, lines 1-6] Fig 18B) provided on the second chips (120 Fig 18B) and located in the first direction (-D1 direction Fig 19) from the first substrate pads (BP2 Fig 18B), each of the third chips (130 Fig 18B) including one or more third chip pads (133 Fig 18B) electrically connected to the first substrate pads (BP2 Fig 18B), wherein each of the third chip pads (133 Fig 18B) is located to overlap with a highest second chip (120 Fig 18B) of the second chips (120 Fig 18B) in planar view (Fig 19).
Regarding Claim 5, Park et al discloses the limitations of claim 4 as explained above. Park et al further discloses
further comprising: one or more fourth chips (fourth chips 140 [column 11, lines 35-51] Fig 18B) provided on the third chips (130 Fig 18B) and located in the second direction (D2 direction Fig 19) from the second substrate pads (BP4 Fig 18B),
each of the fourth chips (140 Fig 18B) including one or more fourth chip pads (power/ground pads 143 [column 12, lines 34-44] Fig 18B) electrically connected to the second substrate pads (BP4 Fig 18B),
wherein each of the fourth chip pads (143 Fig 18B) is located to overlap a highest third chip (130 Fig 18B) of the third chips (130 Fig 18B) in planar view (Fig 19).
Regarding Claim 11, Park et al discloses the limitations of claim 3 as explained above. Park et al further discloses
wherein the second direction (D2 direction Fig 19) is rotated 90 degrees in a predetermined rotational direction with respect to the first direction (-D1 direction Fig 19),
the third direction (D1 direction Fig 19) is rotated 90 degrees in the predetermined rotational direction with respect to the second direction (D2 direction Fig 19), and
the fourth direction (-D2 direction Fig 19) is rotated 90 degrees in the predetermined rotational direction with respect to the third direction (D1 direction Fig 19).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6-8, 10, 12, 16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (US 12237304) in view of Kuroda (US 2012/0217658).
Regarding Claim 6, Park et al discloses the limitations of claim 1 as explained above. Park et al further discloses
wherein the second chips (second chips 120 [column 4, lines 43-67] 120 Fig 18B) include a plurality of second chips (120 Fig 18B) stacked to form stairsteps in the second direction (D2 direction Fig 19).
Park et al does not disclose
wherein the first chips include a plurality of first chips stacked to form stairsteps in the first direction.
Kuroda, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein the first chips (memory chips 10 [0079] Fig 13) include a plurality of first chips stacked to form stairsteps in the first direction (-D1 direction shown in annotated Fig 13).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Park et al to include wherein the first chips include a plurality of first chips stacked to form stairsteps in the first direction as taught by Kuroda in order to prevent any unusable space from being created due to formation and reducing the area for the layout of the coils so that the power for transmission can be reduced [0027]. Further, a person of ordinary skill in the art would have recognized that improving the arrangement by stacking the IC chips would optimize the functional capability of the device while meeting small size requirements (see MPEP 2143.I(D)).
Regarding Claim 7, the combination of Park et al and Kuroda discloses the limitations of claim 6 as explained above. The combination of Park et al and Kuroda further discloses
wherein the plurality of first chips (first stack of chips 10 shown in annotated Fig 13 Kuroda) are stacked to form the stairsteps only in the first direction (-D1 direction shown in annotated Fig 13 Kuroda), and
the plurality of second chips (second stack of chips 10 shown in annotated Fig 13 Kuroda) are stacked to form the stairsteps in the second direction (D2 direction shown in annotated Fig 13 Kuroda) and in the first direction (-D1 direction shown in annotated Kuroda).
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Regarding Claim 8, Park et al discloses the limitations of claim 2 as explained above. Park et al further discloses
wherein the second chips (second chips 120 [column 4, lines 43-67] 120 Fig 18B) include a plurality of second chips (120 Fig 18B) stacked to form stairsteps in the second direction (D2 direction Fig 19).
Park et al does not disclose
wherein the first chips include a plurality of first chips stacked to form stairsteps in the first direction, and the third chips include a plurality of third chips stacked to form stairsteps in the third direction.
Kuroda, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein the first chips (memory chips 10 [0079] Fig 13) include a plurality of first chips stacked to form stairsteps in the first direction (-D1 direction shown in annotated Fig 13), and the third chips (memory chips 10 [0079] Fig 13) include a plurality of third chips (10 Fig 13) stacked to form stairsteps in the third direction (D1 direction shown in annotated Fig 13).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Park et al to include wherein the first chips include a plurality of first chips stacked to form stairsteps in the first direction, and the third chips include a plurality of third chips stacked to form stairsteps in the third direction as taught by Kuroda in order to prevent any unusable space from being created due to formation and reducing the area for the layout of the coils so that the power for transmission can be reduced [0027]. Further, a person of ordinary skill in the art would have recognized that improving the arrangement by stacking the IC chips would optimize the functional capability of the device while meeting small size requirements (see MPEP 2143.I(D)).
Regarding Claim 9, the combination of Park et al and Kuroda discloses the limitations of claim 8 as explained above. The combination of Park et al and Kuroda further discloses
wherein the plurality of first chips (first stack of chips 10 shown in annotated Fig 13 Kuroda) are stacked to form the stairsteps only in the first direction (-D1 direction shown in annotated Fig 13 Kuroda),
the plurality of second chips (second stack of chips 10 shown in annotated Fig 13 Kuroda) are stacked to form the stairsteps in the second direction (D2 direction shown in annotated Fig 13 Kuroda) and in the first direction (-D1 direction shown in annotated Kuroda), and
the plurality of third chips (third stack of chips 10 shown in annotated Fig 13 Kuroda) are stacked to form the stairsteps in the third direction (D1 direction shown in annotated Fig 13 Kuroda) and in the second direction (D2 direction shown in annotated Fig 13 Kuroda).
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Regarding Claim 10, Park et al discloses the limitations of claim 5 as explained above. Park et al further discloses
the second chips (120 Fig 18B) include a plurality of second chips (120 Fig 18B) stacked to form stairsteps in the second direction (D2 direction Fig 19),
the fourth chips (140 Fig 18B) include a plurality of fourth chips (140 Fig 18B) stacked to form stairsteps in the fourth direction (-D2 direction Fig 19).
Park et al does not disclose
wherein the first chips include a plurality of first chips stacked to form stairsteps in the first direction, and
the third chips include a plurality of third chips stacked to form stairsteps in the third direction.
Kuroda, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein the first chips (memory chips 10 [0079] Fig 13) include a plurality of first chips stacked to form stairsteps in the first direction (-D1 direction shown in annotated Fig 13), and
the third chips (memory chips 10 [0079] Fig 13) include a plurality of third chips (10 Fig 13) stacked to form stairsteps in the third direction (D1 direction shown in annotated Fig 13).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Park et al to include wherein the first chips include a plurality of first chips stacked to form stairsteps in the first direction, and the third chips include a plurality of third chips stacked to form stairsteps in the third direction as taught by Kuroda in order to prevent any unusable space from being created due to formation and reducing the area for the layout of the coils so that the power for transmission can be reduced [0027]. Further, a person of ordinary skill in the art would have recognized that improving the arrangement by stacking the IC chips would optimize the functional capability of the device while meeting small size requirements (see MPEP 2143.I(D)).
Regarding Claim 12, Park et al discloses the limitations of claim 5 as explained above. Park et al does not disclose
wherein the first chips, the second chips, the third chips, and the fourth chips are arranged in a spiral.
Kuroda, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein the first chips (memory chips 10 [0079] Fig 13), the second chips (memory chips 10 [0079] Fig 13), the third chips (memory chips 10 [0079] Fig 13), and the fourth chips (memory chips 10 [0079] Fig 13) are arranged in a spiral (shown in Fig 13).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Park et al to include wherein the first chips, the second chips, the third chips, and the fourth chips are arranged in a spiral as taught by Kuroda in order to prevent any unusable space from being created due to formation and reducing the area for the layout of the coils so that the power for transmission can be reduced [0027]. Further, a person of ordinary skill in the art would have recognized that improving the arrangement by stacking the IC chips would optimize the functional capability of the device while meeting small size requirements (see MPEP 2143.I(D)).
Regarding Claim 16, Park et al discloses the limitations of claim 5 as explained above. Park et al, as applied to claim 5, does not directly disclose
further comprising a control chip including a portion provided under the fourth chips in planar view.
However, in a different embodiment, Park et al discloses
a control chip (controller chip 200 [column 8, lines 1-67] Fig 14B) including a portion provided under the stack of chips in planar view (Fig 19).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Park et al, as applied to claim 5, to include a control chip including a portion provided under the fourth chips in planar view as taught by Park et al in order to input and output a plurality of control signals or date signals [column 8, lines 1-67]. Further, a person of ordinary skill in the art would have recognized that to having a control chip to regulate the flow of data and operations would be advantageous in optimizing the functional capability of the device (see MPEP 2143.I(D)).
Regarding Claim 18, Park et al discloses
a semiconductor device (semiconductor package [column 3, lines 28-34] shown in Fig 18B) comprising:
a substrate (package substrate 100 [column 3, lines 34-45] Fig 18B);
a plurality of first substrate pads (second bonding pads BP2 [column 4, lines 1-9] Fig 18B) provided on the substrate (100 Fig 18B);
a plurality of first chips (first chips 110 [column 4, lines 17-41] Fig 18B) provided on the substrate (100 Fig 18B) and located in a first direction (-D2 direction Fig 19) from the first substrate pads (BP2 Fig 18B), the first chips (110 Fig 18B) being stacked to form stairsteps in the first direction (-D2 direction Fig 19) and electrically connected to the first substrate pads (BP2 Fig 18B);
a plurality of second substrate pads (fourth bonding pads BP4 [column 4, lines 1-9] Fig 18B) provided on the substrate (100 Fig 18B); and
a plurality of second chips (second chips 120 [column 4, lines 43-67] 120 Fig 18B) provided on the first chips (100 Fig 18B) and located in a second direction (D1 direction Fig 19) from the second substrate pads (BP4 Fig 18B), the second direction (D1 direction Fig 19) intersecting the first direction (-D2 direction Fig 19), and the second chips (120 Fig 18B) being electrically connected to the second substrate pads (BP4 Fig 18B).
Park et al does not disclose
the second chips being stacked to form stairsteps in the second direction.
Kuroda, in the related art of semiconductor devices that include semiconductor packaging, discloses
the second chips (memory chips 10 [0079] Fig 13) being stacked to form stairsteps in the second direction (D1 direction shown in annotated Fig 13).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Park et al to include the second chips being stacked to form stairsteps in the second direction as taught by Kuroda in order to prevent any unusable space from being created due to formation and reducing the area for the layout of the coils so that the power for transmission can be reduced [0027]. Further, a person of ordinary skill in the art would have recognized that improving the arrangement by stacking the IC chips would optimize the functional capability of the device while meeting small size requirements (see MPEP 2143.I(D)).
Regarding Claim 19, the combination of Park et al discloses the limitations of claim 18 as explained above. The combination of Park et al and Kuroda further discloses
further comprising:
a plurality of third substrate pads (sixth bonding pads BP6 [column 12, lines 20-32] Fig 18B Park et al) provided on the substrate (100 Fig 18B Park et al); and
a plurality of third chips (third chips 130 [column 12, lines 1-6] Fig 18B Park et al) provided on the second chips (120 Fig 18B Park et al) and located in a third direction (D2 direction Fig 19 Park et al) from the third substrate pads (BP6 Fig 18B Park et al), the third direction (D2 direction Fig 19 Park et al) intersecting the second direction (D1 direction Fig 19 Park et al),
the third chips (130 Fig 18B Park et al) being stacked to form stairsteps in the third direction (D2 direction Fig 19 Park et al) and electrically connected to the third substrate pads (BP6 Fig 18B Park et al).
Regarding Claim 20, the combination of Park et al and Kuroda discloses the limitations of claim 19 as explained above. The combination of Park et al and Kuroda further discloses
further comprising: a plurality of fourth substrate pads (eighth bonding pads BP8 [column 12, lines 33-44] Fig 18B Park et al) provided on the substrate (100 Fig 18B Park et al); and
a plurality of fourth chips (fourth chips 140 [column 11, lines 35-51] Fig 18B Park et al) provided on the third chips (130 Fig 18B Park et al) and located in a fourth direction (-D1 direction Fig 19 Park et al) from the fourth substrate pads (BP8 Fig 18B Park et al), the fourth direction (-D1 direction Fig 19 Park et al) intersecting the third direction (D2 direction Fig 19 Park et al), and electrically connected to the fourth substrate pads (BP8 Fig 18B).
The combination of Park et al and Kuroda, as applied to claim 19, does not directly disclose
the fourth chips being stacked to form stairsteps in the fourth direction.
Kuroda, in the related art of semiconductor devices that include semiconductor packaging, discloses
the third chips (memory chips 10 [0079] Fig 13) being stacked to form stairsteps in the third direction (-D1 direction shown in annotated Fig 13).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Park et al to include the fourth chips being stacked to form stairsteps in the fourth direction as taught by Kuroda in order to prevent any unusable space from being created due to formation and reducing the area for the layout of the coils so that the power for transmission can be reduced [0027]. Further, a person of ordinary skill in the art would have recognized that improving the arrangement by stacking the IC chips would optimize the functional capability of the device while meeting small size requirements (see MPEP 2143.I(D)).
Claim 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (US 12237304) in view of Nakamura et al (US 2019/0221503).
Regarding Claim 13, Park et al discloses the limitations of claim 1 as explained above. Park et al does not directly disclose
wherein when a length of short sides of the second chips is denoted as "a" [mm], a length of long sides of the second chips is denoted as "b" [mm], and a distance between a center line of the second chips parallel to the second direction and an outermost second chip pad of the second chip pads is denoted as "e" [mm], e ≤ b - a/2 - 0.3 holds.
Nakamura et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein a semiconductor chip may have a length of over 3 mm [0024].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Park et al to include wherein a semiconductor chip may have a length of over 3 mm as taught by Nakamura et al in order to lower inductance and mounting with surface mount packages that can reduce parasitic inductance [0034] and because it would have been an obvious matter of design choice to optimize the length of the semiconductor chip since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A). Further, a person of ordinary skill in the art would have recognized that reducing parasitic inductance would be advantageous in improving the functional capability of the device while reducing the risk of unwanted damage due to undesirable electrical effects (see MPEP 2143.I(D)).
The combination of Park et al and Nakamura et al now discloses
wherein when a length of short sides of the second chips is denoted as "a" [mm], a length of long sides of the second chips is denoted as "b" [mm] (Park et al discloses square shape semiconductor chips wherein a = b), and
a distance between a center line of the second chips parallel to the second direction and an outermost second chip pad of the second chip pads is denoted as "e" [mm], e ≤ b - a/2 - 0.3 holds (shown in annotated Fig 18B and Fig 19 Park et al, using the length of 3mm or greater as taught by Nakamura et al).
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Regarding Claim 14, Park et al discloses the limitations of claim 2 as explained above. Park et al does not directly disclose
wherein when a length of short sides of the third chips is denoted as "a" [mm], a length of long sides of the third chips is denoted as "b" [mm], and a distance between a center line of the third chips parallel to the third direction and an outermost third chip pad of the third chip pads is denoted as "e" [mm], e ≤ b - a/2 - 0.3 holds.
Nakamura et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein a semiconductor chip may have a length of over 3 mm [0024].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Park et al to include wherein a semiconductor chip may have a length of over 3 mm as taught by Nakamura et al in order to lower inductance and mounting with surface mount packages that can reduce parasitic inductance [0034] and because it would have been an obvious matter of design choice to optimize the length of the semiconductor chip since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A). Further, a person of ordinary skill in the art would have recognized that reducing parasitic inductance would be advantageous in improving the functional capability of the device while reducing the risk of unwanted damage due to undesirable electrical effects (see MPEP 2143.I(D)).
The combination of Park et al and Nakamura et al now discloses
wherein when a length of short sides of the third chips is denoted as "a" [mm], a length of long sides of the third chips is denoted as "b" [mm], and a distance between a center line of the third chips parallel to the third direction and an outermost third chip pad of the third chip pads is denoted as "e" [mm], e ≤ b - a/2 - 0.3 holds (shown in annotated Fig 18B and Fig 19 Park et al, using the length of 3mm or greater as taught by Nakamura et al).
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Regarding Claim 15, Park et al discloses the limitations of claim 3 as explained above. Park et al does not directly disclose
wherein when a length of short sides of the fourth chips is denoted as "a" [mm], a length of long sides of the fourth chips is denoted as "b" [mm], and a distance between a center line of the fourth chips parallel to the fourth direction and an outermost fourth chip pad of the fourth chip pads is denoted as "e" [mm], e ≤ b - a/2 - 0.3 holds.
Nakamura et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein a semiconductor chip may have a length of over 3 mm [0024].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Park et al to include wherein a semiconductor chip may have a length of over 3 mm as taught by Nakamura et al in order to lower inductance and mounting with surface mount packages that can reduce parasitic inductance [0034] and because it would have been an obvious matter of design choice to optimize the length of the semiconductor chip since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A). Further, a person of ordinary skill in the art would have recognized that reducing parasitic inductance would be advantageous in improving the functional capability of the device while reducing the risk of unwanted damage due to undesirable electrical effects (see MPEP 2143.I(D)).
The combination of Park et al and Nakamura et al now discloses
wherein when a length of short sides of the fourth chips is denoted as "a" [mm], a length of long sides of the fourth chips is denoted as "b" [mm], and a distance between a center line of the fourth chips parallel to the fourth direction and an outermost fourth chip pad of the fourth chip pads is denoted as "e" [mm], e ≤ b - a/2 - 0.3 holds (shown in annotated Fig 18B and Fig 19 Park et al, using the length of 3mm or greater as taught by Nakamura et al).
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Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al (US 12237304) in view of Kim (US 2024/0079400).
Regarding Claim 17, Park et al discloses the limitations of claim 1 as explained above. Park et al does not directly disclose
wherein a thickness of a lowest first chip of the first chips is thicker than thicknesses of other first chips of the first chips.
Kim, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein a thickness of a lowest first chip (controller chip 120 [0047] Fig 7) of the first chips (first group of semiconductor chips 140-1 and controller chip 120 [0047] Fig 7) is thicker than thicknesses of other first chips (140-1 Fig 7) of the first chips (140-1 and 120 Fig 7).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Park et al to include wherein a thickness of a lowest first chip of the first chips is thicker than thicknesses of other first chips of the first chips as taught by Kim in order to have a control chip that includes a control circuit for determining a data processing order [0020] and because it would have been an obvious matter of design choice to optimize the thickness of the semiconductor chips since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A). Further, a person of ordinary skill in the art would have recognized that a control chip may have to handle higher electrical power and often needs extra components which would require a thicker chip (see MPEP 2143.I(D)).
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lopez et al (US 2014/0063744) which discloses a first chip and a second chip [0025]-[0028], and Tay et al (US 2002/0043986) which discloses semiconductor chip packages [0003].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID PAUL SEDOROOK whose telephone number is (571)272-4158. The examiner can normally be reached Monday - Friday 7:30 am -5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached on (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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