DETAILED ACTION
This Action is a response to the filing received 20 August 2024. Claims 1-20 were originally presented. In a Preliminary Amendment filed 20 February 2025, claims 1-20 were canceled and claims 21-40 were newly added. Claims 21-40 remain pending for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 20 August 2024 is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21-30, 32-33 and 36-39 are rejected over claims 1, 3-4, 7-8, 10-11, 14-15, 17 and 20-27 of U.S. Patent No. 11,551,990; claims 21-30, 32-33 and 36-39 are rejected over claims 1, 3-5, 7, 9, 11-13, 15-17, 19-21, 23-24 and 26-32 of U.S. Patent No. 11,742,038; claims 21-33, 36-37 and 39-40 are rejected over claims 21-22, 24-29, 27-36 and 38-40 of U.S. Patent No. 12,068,215; and claims 21, 23, 25-27, 29, 32-33 and 39 are rejected over claims 25, 27-32, 34-37 and 39-44 of U.S. Patent No. 12,080,362. Although the claims at issue are not identical, they are not patentably distinct from each other because with minor variations in language (such as a substitution of “operating condition” data for thermal data, the identified claims recite like subject matter. Tables have been provided below for ease of reference.
Current Application
U.S. 11,551,990
21. (New) A method for providing thermal wear spreading among a plurality of thermal die regions the method comprising:
1. (currently amended) A method for providing thermal wear spreading among a plurality of thermal die regions in an integrated circuit the method comprising:
producing die region wear-out data for a die region in each die of a plurality of dies, the die region wear-out data representing a cumulative amount of time each of the plurality of thermal die regions has spent at a temperature level, based on temperature data from each of the plurality of thermal die regions;
producing die region wear-out data representing a cumulative amount of time each of the plurality of thermal die regions has spent at a temperature level, based on temperature data from each of the plurality of thermal die regions;
3. (currently amended) The method of claim 1, wherein the die region wear-out data is based on temperature data accrued over the life of each respective thermal region of the plurality of thermal die regions.
storing, in persistent memory, the die region wear-out data; and
storing, in persistent memory, the die region wear-out data;
spreading thermal wear among the plurality of thermal die regions using a spreading operation based on operating condition data that overrides a thermal wear spreading operation that is based on the die region wear-out data from the persistent memory that is accumulated over the life of the respective thermal region.
determining if a short term spreading operation based on operating condition data that is not accumulated over a life of a respective thermal region should override a thermal wear spreading operation that is based on the die region wear-out data that is accumulated over the life of the respective thermal region; and when an override condition is met, spreading thermal wear among the plurality of thermal die regions based on operating condition data that is not accumulated over the life of a respective thermal region when an override condition exists
22. (New) The method of claim 21, further comprising wherein spreading thermal wear among the plurality of thermal die regions includes remapping of memory addresses for a die region of memory.
21. (original) The method of claim 1, further comprising wherein spreading thermal wear among the plurality of thermal die regions includes remapping of memory addresses for a die region of memory.
23. (New) The method of claim 21 wherein:
4. (currently amended) The method of claim I wherein:
the temperature level includes a plurality of temperature ranges;
the temperature level includes a plurality of temperature ranges;
the die region wear-out data including data representing a cumulative amount of time each of the plurality of thermal die regions has spent in each of the plurality of temperature ranges; and
the die region wear-out data including data representing a cumulative amount of time each of the plurality of thermal die regions has spent in each of the plurality of temperature ranges; and
producing die region wear-out data includes combining the cumulative amount of time each of the plurality of thermal die regions has spent in each of the plurality of temperature ranges.
generating wear out control data by combining the cumulative amount of time each of the plurality of thermal die regions has spent in each of the plurality of temperature ranges.
24. (New) The method of claim 21, wherein: producing die region wear-out data includes:
24. (currently amended) The method of claim 1, wherein: producing die region wear-out data includes:
categorizing each of the plurality of thermal die regions into a wear-out level based on the die region wear-out data;
categorizing each of the plurality of thermal die regions into a wear-out level based on the die region wear-out data;
ordering threads in a manner indicative of an amount of heat a thread is determined to cause when executing; and
ordering threads in a manner indicative of an amount of heat a thread is determined to cause when executing; and
spreading thermal wear among the plurality of thermal die regions using the die region wear-out data comprises assigning threads such that a thread causing a lower amount of heat is assigned to a die region having a higher wear-out level with respect to another die region.
spreading thermal wear among the plurality of thermal die regions using the die region wear-out data comprises assigning threads such that a thread causing a lower amount of heat is assigned to a die region having a higher wear-out level with respect to another die region.
25. (New) The method of claim 21 comprising:
27. (original) The method of claim 1 comprising:
producing fault detection information indicating that a number of faults has occurred beyond a desired threshold;
producing fault detection information indicating that a number of faults has occurred beyond a desired threshold;
storing, in persistent memory, the number of faults that has occurred beyond a desired threshold;
storing, in persistent memory, the number of faults that has occurred beyond a desired threshold;
anticipating when a fault will occur based on at least both the die region wear-out data and based on the fault detection information indicating the number of faults that has occurred beyond the desired threshold; and
anticipating when a fault will occur based on at least both the die region wear-out data and based on the fault detection information indicating the number of faults that has occurred beyond the desired threshold; and
wherein producing fault detection information comprises producing data indicating at least one of: an error rate exceeds a threshold or logic timing delays exceed a threshold.
wherein producing fault detection information comprises producing data indicating at least one of: an error rate exceeds a threshold or logic timing delays exceed a threshold.
26. (New) The method of claim 21, further comprising:
7. (original) The method of claim 1, further comprising:
determining die region wear-out level data by combining die region wear-out data from multiple temperature ranges; and
determining die region wear-out level data by combining die region wear-out data from multiple temperature ranges; and
wherein spreading thermal wear among the plurality of thermal die regions includes controlling task execution among the plurality of thermal die regions using the die region wear-out level data.
wherein spreading thermal wear among the plurality of thermal die regions includes controlling task execution among the plurality of thermal die regions using the die region wear-out level data.
27. (New) An apparatus, comprising:
8. (currently amended) An apparatus, comprising:
at least one integrated circuit package having a plurality of dies each die comprising a plurality of thermal die regions;
at least one integrated circuit having a plurality of thermal die regions;
temperature sensors operatively coupled to the plurality of thermal die regions and operative to provide temperature data associated with the plurality of thermal die regions; and
temperature sensors operatively coupled to the plurality of thermal die regions and operative to provide temperature data associated with the plurality of thermal die regions; and
thermal wear spreading logic, operatively coupled to the temperature sensors and operative to:
thermal wear spreading logic, operatively coupled to the temperature sensors and operative to:
[[[perform the steps of claim 21]]]
[[[perform the steps of claim 1]]]
CLAIMS 28-30 ~ CLAIMS 22-24
CLAIMS 10-11 ~ CLAIMS 3-4
CLAIM 14 ~ CLAIM 7
CLAIM 32 ~ CLAIM 26
15. (currently amended) An apparatus, comprising: at least one integrated circuit package having a plurality of stacked dies each with a plurality of thermal die regions;
temperature sensors operatively coupled to the plurality of thermal die regions and operative to provide temperature data associated with the plurality of thermal die regions;
33. (New) The apparatus of claim 27 comprising the persistent memory.
a persistent memory;
thermal wear spreading logic, operatively coupled to the persistent memory and responsive to the temperature data, and operative to: [[[perform the steps of claims 1/8]]]
CLAIM 17 ~ CLAIM 3
CLAIM 20 ~ CLAIM 7
CLAIMS 22-23 ~ CLAIM 21
CLAIMS 25-26 ~ CLAIM 24
CLAIM 36 ~ CLAIM 22
CLAIM 37 ~ CLAIM 24
38. (New) The integrated circuit package of claim 34 wherein the first and second thermal wear spreading logic is operative to produce fault detection information by producing data indicating at least one of: an error rate exceeds a threshold or logic timing delays exceed a threshold.
28. (original) The apparatus of claim 15 wherein the thermal wear spreading logic is operative to produce fault detection information by producing data indicating at least one of: an error rate exceeds a threshold or logic timing delays exceed a threshold.
CLAIM 39 ~ CLAIM 26
Current Application
U.S. 11,742,038
21. (New) A method for providing thermal wear spreading among a plurality of thermal die regions the method comprising:
1. (currently amended) A method for providing wear spreading among a plurality of die regions in an integrated circuit, the method comprising:
producing die region wear-out data for a die region in each die of a plurality of dies, the die region wear-out data representing a cumulative amount of time each of the plurality of thermal die regions has spent at a temperature level, based on temperature data from each of the plurality of thermal die regions;
producing die region wear-out data representing a cumulative amount of time each of the plurality of die regions has spent at an operating condition based on operating condition data from each of the plurality of die regions, wherein the operating condition data is based on at least one of the following operating characteristics: frequency of operation of the plurality of die regions, an operating voltage of the plurality of die regions and an activity level of the plurality of die regions;
3. (currently amended) The method of claim 1, wherein the die region wear-out data is based on operating condition data associated with each of the plurality of die regions accrued over the life of each respective region of the plurality of die regions.
5. (currently amended) The method of claim 1, wherein the operating condition data is based on a plurality of operating characteristics from the group consisting of: the frequency of operation of the plurality of die regions, temperature level of the plurality of die regions, the operating voltage of the plurality of die regions, the activity level of the plurality of die regions, a timing margin of the plurality of die regions, and a number of detected faults of the plurality of die regions.
storing, in persistent memory, the die region wear-out data; and
storing, in persistent memory, the die region wear-out data;
spreading thermal wear among the plurality of thermal die regions using a spreading operation based on operating condition data that overrides a thermal wear spreading operation that is based on the die region wear-out data from the persistent memory that is accumulated over the life of the respective thermal region.
determining if a short term spreading operation based on operating condition data that is not accumulated over a life of a respective thermal region should override a thermal wear spreading operation that is based on the die region wear-out data that is accumulated over the life of the respective thermal region; and when an override condition is met, spreading thermal wear among the plurality of thermal die regions based on operating condition data that is not accumulated over the life of a respective thermal region when an override condition exists.
22. (New) The method of claim 21, further comprising wherein spreading thermal wear among the plurality of thermal die regions includes remapping of memory addresses for a die region of memory.
26. (previously presented) The method of claim 1, further comprising wherein spreading wear among the plurality of die regions includes generating wear-out control data that controls at least one of: remapping of memory addresses for a die region of memory and operation of other functional units in the integrated circuit.
23. (New) The method of claim 21 wherein:
4. (currently amended) The method of claim 1, wherein:
the temperature level includes a plurality of temperature ranges;
the operating condition includes a plurality of operating ranges;
the die region wear-out data including data representing a cumulative amount of time each of the plurality of thermal die regions has spent in each of the plurality of temperature ranges; and
the die region wear-out data includes data representing a cumulative amount of time each of the plurality of die regions has spent in each of the plurality of operating ranges; and
producing die region wear-out data includes combining the cumulative amount of time each of the plurality of thermal die regions has spent in each of the plurality of temperature ranges.
generating wear-out control data by combining the cumulative amount of time each of the plurality of die regions has spent in each of the plurality of operating ranges.
24. (New) The method of claim 21, wherein: producing die region wear-out data includes:
29. (previously presented) The method of claim 1, wherein: producing die region wear-out data includes:
categorizing each of the plurality of thermal die regions into a wear-out level based on the die region wear-out data;
categorizing each of the plurality of die regions into a wear-out level based on the die region wear-out data; and
ordering threads in a manner indicative of an amount of heat a thread is determined to cause when executing; and
ordering threads in a manner indicative of an amount of heat a thread is determined to cause when executing; and
spreading thermal wear among the plurality of thermal die regions using the die region wear-out data comprises assigning threads such that a thread causing a lower amount of heat is assigned to a die region having a higher wear-out level with respect to another die region.
spreading thermal wear among the plurality of thermal die regions using the die region wear-out data comprises assigning threads such that a thread causing a lower amount of heat is assigned to a die region having a higher wear-out level with respect to another die region.
25. (New) The method of claim 21 comprising:
32. (previously presented) The method of claim 1 comprising:
producing fault detection information indicating that a number of faults has occurred beyond a desired threshold;
producing fault detection information indicating that a number of faults has occurred beyond a desired threshold;
storing, in persistent memory, the number of faults that has occurred beyond a desired threshold;
storing, in persistent memory, the number of faults that has occurred beyond a desired threshold;
anticipating when a fault will occur based on at least both the die region wear-out data and based on the fault detection information indicating the number of faults that has occurred beyond the desired threshold; and
anticipating when a fault will occur based on at least both the cumulative die region wear- out data and based on the fault detection information indicating the number of faults that has occurred beyond the desired threshold; and
wherein producing fault detection information comprises producing data indicating at least one of: an error rate exceeds a threshold or logic timing delays exceed a threshold.
wherein producing fault detection information comprises producing data indicating at least one of: an error rate exceeds a threshold or logic timing delays exceed a threshold.
26. (New) The method of claim 21, further comprising:
7. (original) The method of claim 1, further comprising:
determining die region wear-out level data by combining die region wear-out data from multiple temperature ranges; and
determining die region wear-out level data by combining die region wear-out data from multiple operating ranges; and
wherein spreading thermal wear among the plurality of thermal die regions includes controlling task execution among the plurality of thermal die regions using the die region wear-out level data.
wherein spreading wear among the plurality of die regions includes controlling task execution among the plurality of die regions using the die region wear-out level data.
27. (New) An apparatus, comprising:
9. (currently amended) An apparatus, comprising:
at least one integrated circuit package having a plurality of dies each die comprising a plurality of thermal die regions;
at least one integrated circuit having a plurality of die regions;
temperature sensors operatively coupled to the plurality of thermal die regions and operative to provide temperature data associated with the plurality of thermal die regions; and
a plurality of sensors operatively coupled to the plurality of die regions and operative to provide operating condition data associated with the plurality of die regions; and
thermal wear spreading logic, operatively coupled to the temperature sensors and operative to:
wear spreading logic, operatively coupled to the sensors and operative to:
[[[perform the steps of claim 21]]]
[[[perform the steps of claim 1]]]
CLAIMS 28-30 ~ CLAIMS 22-24
CLAIMS 11-13 ~ CLAIMS 3-5
CLAIMS 15-16 ~ CLAIMS 7-8
CLAIM 27 ~ CLAIM 26
CLAIM 30 ~ CLAIM 29
CLAIM 32 ~ CLAIM 26
17. (currently amended) An apparatus, comprising: at least one integrated circuit package having a plurality of stacked dies each with a plurality of die regions;
33. (New) The apparatus of claim 27 comprising the persistent memory.
a persistent memory;
[sensors and wear spreading logic operative to:] [[[perform the steps of claims 1/9]]]
CLAIMS 19-21 ~ CLAIMS 3-5
CLAIMS 23-24 ~ CLAIMS 7-8
CLAIM 28 ~ CLAIM 16
CLAIM 31 ~ CLAIM 29
CLAIM 36 ~ CLAIM 22
CLAIM 37 ~ CLAIM 24
38. (New) The integrated circuit package of claim 34 wherein the first and second thermal wear spreading logic is operative to produce fault detection information by producing data indicating at least one of: an error rate exceeds a threshold or logic timing delays exceed a threshold.
33. (previously presented) The apparatus of claim 17 wherein the thermal wear spreading logic is operative to produce fault detection information by producing data indicating at least one of. an error rate exceeds a threshold or logic timing delays exceed a threshold.
CLAIM 39 ~ CLAIM 26
Current Application
U.S. 12,068,215
21. (New) A method for providing thermal wear spreading among a plurality of thermal die regions the method comprising:
21. (Currently Amended) A method for providing thermal wear spreading among a plurality of thermal die regions the method comprising:
producing die region wear-out data for a die region in each die of a plurality of dies, the die region wear-out data representing a cumulative amount of time each of the plurality of thermal die regions has spent at a temperature level, based on temperature data from each of the plurality of thermal die regions;
producing die region wear-out data for a die region in each die of a plurality of stacked dies, the die region wear-out data representing a cumulative amount of time each of the plurality of thermal die regions has spent at a temperature level, based on temperature data from each of the plurality of thermal die regions;
storing, in persistent memory, the die region wear-out data; and
storing, in persistent memory, the die region wear-out data; and
spreading thermal wear among the plurality of thermal die regions using a spreading operation based on operating condition data that overrides a thermal wear spreading operation that is based on the die region wear-out data from the persistent memory that is accumulated over the life of the respective thermal region.
spreading thermal wear among the plurality of thermal die regions using a spreading operation based on operating condition data that is not accumulated over a life of a respective thermal region, that overrides a thermal wear spreading operation that is based on the die region wear-out data from the persistent memory, that is accumulated over the life of the respective thermal region.
22. (New) The method of claim 21, further comprising wherein spreading thermal wear among the plurality of thermal die regions includes remapping of memory addresses for a die region of memory.
22. (Previously Presented) The method of claim 21, further comprising wherein spreading thermal wear among the plurality of thermal die regions includes remapping of memory addresses for a die region of memory.
23. (New) The method of claim 21 wherein:
24. (Previously Presented) The method of claim 21 wherein:
the temperature level includes a plurality of temperature ranges;
the temperature level includes a plurality of temperature ranges;
the die region wear-out data including data representing a cumulative amount of time each of the plurality of thermal die regions has spent in each of the plurality of temperature ranges; and
the die region wear-out data including data representing a cumulative amount of time each of the plurality of thermal die regions has spent in each of the plurality of temperature ranges; and
producing die region wear-out data includes combining the cumulative amount of time each of the plurality of thermal die regions has spent in each of the plurality of temperature ranges.
producing die region wear-out data includes combining the cumulative amount of time each of the plurality of thermal die regions has spent in each of the plurality of temperature ranges.
24. (New) The method of claim 21, wherein: producing die region wear-out data includes:
25. (Previously Presented) The method of claim 21, wherein: producing die region wear-out data includes:
categorizing each of the plurality of thermal die regions into a wear-out level based on the die region wear-out data;
categorizing each of the plurality of thermal die regions into a wear-out level based on the die region wear-out data;
ordering threads in a manner indicative of an amount of heat a thread is determined to cause when executing; and
ordering threads in a manner indicative of an amount of heat a thread is determined to cause when executing; and
spreading thermal wear among the plurality of thermal die regions using the die region wear-out data comprises assigning threads such that a thread causing a lower amount of heat is assigned to a die region having a higher wear-out level with respect to another die region.
spreading thermal wear among the plurality of thermal die regions using the die region wear-out data comprises assigning threads such that a thread causing a lower amount of heat is assigned to a die region having a higher wear-out level with respect to another die region.
25. (New) The method of claim 21 comprising:
26. (Currently Amended) The method of claim 21 comprising:
producing fault detection information indicating that a number of faults has occurred beyond a desired threshold;
producing fault detection information indicating that a number of faults has occurred beyond a desired threshold;
storing, in persistent memory, the number of faults that has occurred beyond a desired threshold;
storing, in persistent memory, the number of faults that has occurred beyond a desired threshold;
anticipating when a fault will occur based on at least both the die region wear-out data and based on the fault detection information indicating the number of faults that has occurred beyond the desired threshold; and
anticipating when a fault will occur based on at least both the cumulative die region wear-out data and based on the fault detection information indicating the number of faults that has occurred beyond the desired threshold; and
wherein producing fault detection information comprises producing data indicating at least one of: an error rate exceeds a threshold or logic timing delays exceed a threshold.
wherein producing fault detection information comprises producing data indicating at least one of: an error rate exceeds a threshold or logic timing delays exceed a threshold.
26. (New) The method of claim 21, further comprising:
27. (Previously Presented) The method of claim 21, further comprising:
determining die region wear-out level data by combining die region wear-out data from multiple temperature ranges; and
determining die region wear-out level data by combining die region wear-out data from multiple temperature ranges; and
wherein spreading thermal wear among the plurality of thermal die regions includes controlling task execution among the plurality of thermal die regions using the die region wear-out level data.
wherein spreading thermal wear among the plurality of thermal die regions includes controlling task execution among the plurality of thermal die regions using the die region wear-out level data.
27. (New) An apparatus, comprising:
28. (Currently Amended) An apparatus, comprising:
at least one integrated circuit package having a plurality of dies each die comprising a plurality of thermal die regions;
at least one integrated circuit package having a plurality of stacked dies each stacked die comprising a plurality of thermal die regions;
temperature sensors operatively coupled to the plurality of thermal die regions and operative to provide temperature data associated with the plurality of thermal die regions; and
temperature sensors operatively coupled to the plurality of thermal die regions and operative to provide temperature data associated with the plurality of thermal die regions; and
thermal wear spreading logic, operatively coupled to the temperature sensors and operative to:
thermal wear spreading logic, operatively coupled to the temperature sensors and operative to:
[[[perform the steps of claim 21]]]
[[[perform the steps of claim 21]]]
CLAIMS 28-30 ~ CLAIMS 22-24
CLAIM 29 ~ CLAIM 22
CLAIMS 31-32 ~ CLAIMS 24-25
31. (New) The apparatus of claim 28 comprising a memory controller that employs a data remap table and remaps memory accesses to different regions of memory that have a lower amount of determined wear-out level, based on the data remap table.
33. (Previously Presented) The apparatus of claim 29 comprising a memory controller that employs a data remap table and remaps memory accesses to different regions of memory that have a lower amount of determined wear-out level, based on the data remap table.
CLAIM 32 ~ CLAIM 26
CLAIM 34 ~ CLAIM 27
35. (Currently Amended) An apparatus, comprising: at least one integrated circuit package having a plurality of stacked dies each with a plurality of thermal die regions;
temperature sensors operatively coupled to the plurality of thermal die regions and operative to provide temperature data associated with the plurality of thermal die regions;
33. (New) The apparatus of claim 27 comprising the persistent memory.
a persistent memory; and
thermal wear spreading logic, operatively coupled to the persistent memory and responsive to the temperature data, and operative to:
[[[perform the steps of claim 21]]]
CLAIM 36 ~ CLAIM 22
CLAIM 38 ~ CLAIM 24
CLAIM 39 ~ CLAIM 26
CLAIM 40 ~ CLAIM 27
CLAIM 36 ~ CLAIM 22
CLAIM 37 ~ CLAIM 24
CLAIM 39 ~ CLAIM 26
CLAIM 40 ~ CLAIM 31
Current Application
U.S. 12,080,362
21. (New) A method for providing thermal wear spreading among a plurality of thermal die regions the method comprising:
25. (Currently Amended) A method for providing wear spreading among a plurality of die regions, the method comprising:
producing die region wear-out data for a die region in each die of a plurality of dies, the die region wear-out data representing a cumulative amount of time each of the plurality of thermal die regions has spent at a temperature level, based on temperature data from each of the plurality of thermal die regions;
producing die region wear-out data for a die region in each die of a plurality of stacked dies, the die region wear-out data representing a cumulative amount of time each of the plurality of die regions has spent at an operating condition based on operating condition data from each of the plurality of die regions, wherein the operating condition data is based on at least one of the following operating characteristics: frequency of operation of the plurality of die regions, an operating voltage of the plurality of die regions and an activity level of the plurality of die regions;
27. (Previously Presented) The method of claim 25, wherein the die region wear-out data is based on operating condition data associated with each of the plurality of die regions accrued over the life of each respective region of the plurality of die regions.
29. (Previously Presented) The method of claim 25, wherein the operating condition data is based on a plurality of operating characteristics from the group consisting of: the frequency of operation of the plurality of die regions, temperature level of the plurality of die regions, the operating voltage of the plurality of die regions, the activity level of the plurality of die regions, a timing margin of the plurality of die regions, and a number of detected faults of the plurality of die regions.
storing, in persistent memory, the die region wear-out data; and
storing, in persistent memory, the die region wear-out data; and
spreading thermal wear among the plurality of thermal die regions using a spreading operation based on operating condition data that overrides a thermal wear spreading operation that is based on the die region wear-out data from the persistent memory that is accumulated over the life of the respective thermal region.
spreading wear among the plurality of die regions using a spreading operation based on operating condition data that is not accumulated over a life of a respective die region, that overrides a thermal wear spreading operation that is based on the die region wear-out data from the persistent memory, that is accumulated over the life of the respective die region.
23. (New) The method of claim 21 wherein:
28. (Previously Presented) The method of claim 25, wherein:
the temperature level includes a plurality of temperature ranges;
the operating condition includes a plurality of operating ranges;
the die region wear-out data including data representing a cumulative amount of time each of the plurality of thermal die regions has spent in each of the plurality of temperature ranges; and
the die region wear-out data includes data representing a cumulative amount of time each of the plurality of die regions has spent in each of the plurality of operating ranges; and
producing die region wear-out data includes combining the cumulative amount of time each of the plurality of thermal die regions has spent in each of the plurality of temperature ranges.
producing die region wear-out data includes combining the cumulative amount of time each of the plurality of die regions has spent in each of the plurality of operating ranges.
25. (New) The method of claim 21 comprising:
31. (Previously Presented) The method of claim 29, further comprising:
producing fault detection information indicating that a number of faults has occurred beyond a desired threshold;
storing, in persistent memory, the number of faults that has occurred beyond a desired threshold;
anticipating when a fault will occur based on at least both the die region wear-out data and based on the fault detection information indicating the number of faults that has occurred beyond the desired threshold; and
combining operating condition data associated with differing types of operating characteristics from each of the plurality of die regions; and spreading wear among the plurality of die regions by generating wear-out control data based on the combined operating condition data associated with differing types of operating characteristics of each of the plurality of die regions.
wherein producing fault detection information comprises producing data indicating at least one of: an error rate exceeds a threshold or logic timing delays exceed a threshold.
26. (New) The method of claim 21, further comprising:
30. (Previously Presented) The method of claim 25, further comprising:
determining die region wear-out level data by combining die region wear-out data from multiple temperature ranges; and
determining die region wear-out level data by combining die region wear-out data from multiple operating ranges; and
wherein spreading thermal wear among the plurality of thermal die regions includes controlling task execution among the plurality of thermal die regions using the die region wear-out level data.
wherein spreading wear among the plurality of die regions includes controlling task execution among the plurality of die regions using the die region wear-out level data.
27. (New) An apparatus, comprising:
32. (Currently Amended) An apparatus, comprising:
at least one integrated circuit package having a plurality of dies each die comprising a plurality of thermal die regions;
at least one integrated circuit having a plurality of stacked dies each stacked die comprising a plurality of die regions;
temperature sensors operatively coupled to the plurality of thermal die regions and operative to provide temperature data associated with the plurality of thermal die regions; and
a plurality of sensors operatively coupled to the plurality of die regions and operative to provide operating condition data associated with the plurality of die regions; and
thermal wear spreading logic, operatively coupled to the temperature sensors and operative to:
wear spreading logic, operatively coupled to the plurality of sensors and operative to:
[[[perform the steps of claim 21]]]
[[[perform the steps of claim 25]]]
CLAIM 29 ~ CLAIM 23
CLAIMS 34-37 ~ CLAIMS 27-31
CLAIM 32 ~ CLAIM 26
39. (Currently Amended) An apparatus, comprising: at least one integrated circuit package having a plurality of stacked dies each with a plurality of die regions;
sensors operatively coupled to the plurality of die regions and operative to provide operating condition data associated with the plurality of die regions;
33. (New) The apparatus of claim 27 comprising the persistent memory.
a persistent memory; and
wear spreading logic, operatively coupled to the persistent memory and responsive to the operating condition data, and operative to:
[[[perform the steps of claim 25]]]
CLAIMS 41-44 ~ CLAIMS 27-30
CLAIM 39 ~ CLAIM 26
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. §§ 102 and 103 (or as subject to pre-AIA 35 U.S.C. §§ 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. § 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 34-35 and 39 are rejected under 35 U.S.C. § 103 as being unpatentable over Arora et al., U.S. 2016/0086654 A1 (“Arora”)1 in view of Moyer et al., U.S. 2011/0265090 A1 (“Moyer”).
Regarding claim 34, Arora teaches: An integrated circuit package having a plurality of dies each die comprising a plurality of thermal die regions (Arora, FIGS. 2A-2B), the integrated circuit package comprising:
a first die of the plurality of dies comprising: first thermal wear spreading logic, operatively coupled to first temperature sensors, and operative to spread thermal wear among the plurality of thermal die regions of the first die using a spreading operation based on die region wear-out data …; and a second die of the plurality of dies, comprising: second thermal wear spreading logic, operatively coupled to second temperature sensors, and operative to spread thermal wear among the plurality of thermal die regions of the second die using a spreading operation based on die region wear-out data (Arora, e.g., ¶23, “Control logic for a node 201 … may model or dynamically monitor the thermal locations in the memory stacks 210-213, then assign pending operations to locations in the memory stacks based on the expected thermal level at those locations and the expected thermal penalties that will be incurred by the operations …” See also, e.g., ¶24, “… control logic for performing thermal management of the memory via the data placement and compute dispatch scheme … In alternative embodiments, memory controller functions may be implemented in the logic dies E instead of the host processor …” See also, e.g., ¶25, “physical locations may correspond to a specific die or a region within a die …” See also, e.g., ¶61, “memory controller 251 may have identified logic dies 222E and 223E … as suitable for executing the processing task … memory controller selects one of the logic dies 222E and 223E to assign to the processing task …” Examiner’s note: selecting logic dies 222E and 223E is performed in lieu of selecting other dies based on the thermal characteristics of all the dies (or die regions) in the system. See also, e.g., ¶¶64-65) …;
wherein the first thermal wear spreading logic is operative to communicate thermal information with the second thermal wear spreading logic of the second die (Arora, e.g., ¶24, “… control logic for performing thermal management of the memory via the data placement and compute dispatch scheme … In alternative embodiments, memory controller functions may be implemented in the logic dies E instead of the host processor …” See also, e.g., ¶¶64-65. Examiner’s note: in order to perform an inter-node thermal management process in embodiments in which the thermal management functions are implemented within each node, these thermal management functions (thermal wear spreading logic) must intercommunicate).
Arora does not more particularly teach that die region wear-out data is accumulated over the life of respective thermal regions of the first and second die and stored in persistent memory. However, Moyer does teach: [die-region wear-out data] from persistent memory (Moyer, e.g., ¶25, “Processor 103 includes a usage table that stores the accumulated usage information for each core. In one embodiment, table 121 is implemented in a non-volatile memory on integrated circuit 102 …”), the die region wear-out data being accumulated over the life of the respective thermal regions of the first die [and the second die] (Moyer, e.g., ¶24, “controller 117 also monitors the accumulated usage of each core over the lifetime of integrated circuit 102 …” See also, e.g., ¶29, “controller 117 includes the ability to … record separate usage values for a core operating at specific operating conditions …” and ¶32, “Table 203 records the amount of time (under the heading ‘accumulated usage’) that a core operates at a particular temperature range …”) for the purpose of measuring, tracking and storing information about the usage of each core in a circuit such that, based on information regarding a task to be allocated, a core may be selected such that usage and wear among the cores is balanced (Moyer, e.g., ¶¶23-28).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system and method for thermal aware placement and compute dispatch as taught by Arora to provide that die region wear-out data is accumulated over the life of respective thermal regions of the first and second die and stored in persistent memory because the disclosure of Moyer shows that it was known to those of ordinary skill in the pertinent art to improve a system and method for thermal and other wear balancing in a chip system to provide that die region wear-out data is accumulated over the life of respective thermal regions of the first and second die and stored in persistent memory for the purpose of measuring, tracking and storing information about the usage of each core in a circuit such that, based on information regarding a task to be allocated, a core may be selected such that usage and wear among the cores is balanced (Moyer, Id.).
Regarding claim 35, the rejection of claim 34 is incorporated, and Arora does not more particularly teach that first the spreading logic is operable to schedule operations slated for the first die to operate on the second die, when the second die has less wear-out. However, Moyer does teach: wherein the first thermal wear spreading logic is operative to schedule operations slated for the first die to operate on the second die, when the second die has less wear-out (Moyer, e.g., ¶38, “accumulated usage may be one factor in assigning cores … assign multiple cores to perform a processor operation based on both the lowest accumulated usage … combination to perform the processor operation may be the combination with the lowest total accumulated usage …” See also, e.g., ¶50, “the core or cores are assigned to perform the processor operations based on the accumulated usage of each core to balance the accumulated usages among the cores …”) for the purpose of measuring, tracking and storing information about the usage of each core in a circuit such that, based on information regarding a task to be allocated, a core may be selected such that usage and wear among the cores is balanced (Moyer, e.g., ¶¶23-28).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system and method for thermal aware placement and compute dispatch as taught by Arora to provide that first the spreading logic is operable to schedule operations slated for the first die to operate on the second die, when the second die has less wear-out because the disclosure of Moyer shows that it was known to those of ordinary skill in the pertinent art to improve a system and method for thermal and other wear balancing in a chip system to provide that first the spreading logic is operable to schedule operations slated for the first die to operate on the second die, when the second die has less wear-out for the purpose of measuring, tracking and storing information about the usage of each core in a circuit such that, based on information regarding a task to be allocated, a core may be selected such that usage and wear among the cores is balanced (Moyer, Id.).
Regarding claim 39, the rejection of claim 34 is incorporated, but Arora does not more particularly teach that the first and second wear spreading logic further determine die region wear-out level data by combining data from multiple temperature ranges and spread thermal wear among the die regions by controlling task execution among them using the wear-out data. However, Moyer does teach: wherein the first and second thermal wear spreading logic is further operative to: determine die region wear-out level data by combining die region wear-out data from multiple temperature ranges (Moyer, e.g., ¶50, “In 705, the accumulated usage values for each core are obtained. In one embodiment, the usage values for the desired operating conditions are obtained … whereas in the embodiments of FIGs. 5 and 6, the total accumulated usage values for each core are obtained …” Examiner’s note: given this disclosure of alternative embodiments, in the second, Moyer teaches cumulative wear-out over all temperature ranges (see also, e.g., ¶48, disclosing that the condition parameters may be 1, e.g., temperature only)); and
spread thermal wear among the plurality of thermal die regions by controlling task execution among the plurality of thermal die regions using the die region wear-out level data (Moyer, e.g., ¶50, “the core or cores are assigned to perform the processor operations based on the accumulated usage of each core to balance the accumulated usages across the cores …”) for the purpose of measuring, tracking and storing information about the usage of each core in a circuit such that, based on information regarding a task to be allocated, a core may be selected such that usage and wear among the cores is balanced (Moyer, e.g., ¶¶23-28).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system and method for thermal aware placement and compute dispatch as taught by Arora to provide that the first and second wear spreading logic further determine die region wear-out level data by combining data from multiple temperature ranges and spread thermal wear among the die regions by controlling task execution among them using the wear-out data because the disclosure of Moyer shows that it was known to those of ordinary skill in the pertinent art to improve a system and method for thermal and other wear balancing in a chip system to provide that the first and second wear spreading logic further determine die region wear-out level data by combining data from multiple temperature ranges and spread thermal wear among the die regions by controlling task execution among them using the wear-out data for the purpose of measuring, tracking and storing information about the usage of each core in a circuit such that, based on information regarding a task to be allocated, a core may be selected such that usage and wear among the cores is balanced (Moyer, Id.).
Claims 36 and 40 are rejected under 35 U.S.C. § 103 as being unpatentable over Arora in view of Moyer, and in further view of Lofgren et al., U.S. 7,353,325 B2 (“Lofgren”).
Regarding claim 36, the rejection of claim 34 is incorporated, but Arora in view of Moyer does not more particularly teach that the first and second thermal wear spreading logic spread thermal wear among the die regions by remapping of memory addresses for a die region of memory. However, Lofgren does teach: wherein the first and second thermal wear spreading logic is operative to spread thermal wear among the plurality of thermal die regions by remapping of memory addresses for a die region of memory (Lofgren, e.g., 3:43-60, “logical address is converted by an address translation table 27 into a physical memory address … the translation table is reprogrammable … to redirect data blocks of given logical addresses into different physical banks of memory 11 in order to even out use of the banks …” See also, e.g., 8:15-46, describing remapping of the address translation table such that the highly-used block is swapped with the lightly-used block. Examiner’s note: use and wear are similar, and Arora and Moyer, cited above and incorporated herein, disclose core / region use spreading to reduce accumulated thermal wear) for the purpose of interchanging groups of memory cells to result in more even wear among the groups in order to extend the life of flash EEPROM memory such as in disk drives (Lofgren, e.g., 2:28-62).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system and method for thermal aware placement and compute dispatch as taught by Arora in view of Moyer to provide that the first and second thermal wear spreading logic spread thermal wear among the die regions by remapping of memory addresses for a die region of memory because the disclosure of Lofgren shows that it was known to those of ordinary skill in the pertinent art to improve a system and method for wear leveling techniques in memory systems to provide that the first and second thermal wear spreading logic spread thermal wear among the die regions by remapping of memory addresses for a die region of memory for the purpose of interchanging groups of memory cells to result in more even wear among the groups in order to extend the life of flash EEPROM memory such as in disk drives (Lofgren, Id.).
Regarding claim 40, the rejection of claim 34 is incorporated, but Arora in view of Moyer does not more particularly teach a memory controller employing a data remap table and remaps memory accesses to different memory regions having lower wear-out levels based on the remap table. However, Lofgren does teach: a memory controller that employs a data remap table and remaps memory accesses to different regions of memory that have a lower amount of determined wear-out level, based on the data remap table (Lofgren, e.g., 3:43-60, “logical address is converted by an address translation table 27 into a physical memory address … the translation table is reprogrammable … to redirect data blocks of given logical addresses into different physical banks of memory 11 in order to even out use of the banks …” See also, e.g., 8:15-46, describing remapping of the address translation table such that the highly-used block is swapped with the lightly-used block. Examiner’s note: use and wear are similar, and Arora and Moyer, cited above and incorporated herein, disclose core / region use spreading to reduce accumulated thermal wear) for the purpose of interchanging groups of memory cells to result in more even wear among the groups in order to extend the life of flash EEPROM memory such as in disk drives (Lofgren, e.g., 2:28-62).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system and method for thermal aware placement and compute dispatch as taught by Arora in view of Moyer to provide a memory controller employing a data remap table and remaps memory accesses to different memory regions having lower wear-out levels based on the remap table because the disclosure of Lofgren shows that it was known to those of ordinary skill in the pertinent art to improve a system and method for wear leveling techniques in memory systems to provide a memory controller employing a data remap table and remaps memory accesses to different memory regions having lower wear-out levels based on the remap table for the purpose of interchanging groups of memory cells to result in more even wear among the groups in order to extend the life of flash EEPROM memory such as in disk drives (Lofgren, Id.).
Claim 37 is rejected under 35 U.S.C. § 103 as being unpatentable over Arora in view of Moyer, and in further view of Inoue, Kosuke, U.S. 2014/0245314 A1 (“Inoue”) and Bose et al., U.S. 2009/0328055 A1 (“Bose”).
Regarding claim 37, the rejection of claim 34 is incorporated, but Arora does not more particularly teach that the first and second wear spreading logic categorizes the thermal die regions into a wear-out level based on the die region wear-out data. However, Moyer does teach: wherein the first and second thermal wear spreading logic is further operative to: categorize each of the plurality of thermal die regions into a wear-out level based on the die region wear-out data (Moyer, e.g., ¶54, “multiple ‘life time limit’ values for each operating condition may be given core a core with each value having a different threshold. In some embodiments, in response to the accumulated usage value of a core reaching one of the lower threshold levels, controller 117 would reduce the operating voltage and/or frequency of any processor operation performed by the core …”) for the purpose of measuring, tracking and storing information about the usage of each core in a circuit such that, based on information regarding a task to be allocated, a core may be selected such that usage and wear among the cores is balanced (Moyer, e.g., ¶¶23-28).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system and method for thermal aware placement and compute dispatch as taught by Arora to provide that the first and second wear spreading logic categorizes the thermal die regions into a wear-out level based on the die region wear-out data because the disclosure of Moyer shows that it was known to those of ordinary skill in the pertinent art to improve a system and method for thermal and other wear balancing in a chip system to provide that the first and second wear spreading logic categorizes the thermal die regions into a wear-out level based on the die region wear-out data for the purpose of measuring, tracking and storing information about the usage of each core in a circuit such that, based on information regarding a task to be allocated, a core may be selected such that usage and wear among the cores is balanced (Moyer, Id.).
Arora in view of Moyer does not more particularly teach ordering tasks or operations based on an amount of heat generated when executing and assigning them such that a task or operation causing less heat is assigned to a die region having higher wear-out with respect to another die region. However, Inoue does teach: order [tasks or operations] in a manner indicative of an amount of heat a [task or operation] is determined to cause when executing (Inoue, e.g., ¶85, “scheduler 502 may populate the hot queue 504 and cool queue 506 with instructions, tasks or other operations, depending on thermal attributes. Preferably, the scheduler 502 has access to a look-up table containing thermal attributes …”); and
assign [tasks or operations] such that a [task or operation] causing a lower amount of heat is assigned to a die region having a higher wear-out level with respect to another die region (Inoue, e.g., ¶89, “PE, PU or SPU determines whether its current temperature is above the thermal threshold Tmax. If Tmax is not exceeded … it is determined whether an operation is available from the hot queue 504 … [If Tmax is exceeded] … it is determined whether an operation is available from the cool queue 506 …”) for the purpose of sensing thermal characteristics of hardware, estimating thermal characteristics of tasks to be scheduled, and using this information to balance the thermal load among the hardware (Inoue, e.g., ¶¶84-90).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system and method for thermal aware placement and compute dispatch as taught by Arora in view of Moyer to provide for ordering tasks or operations based on an amount of heat generated when executing and assigning them such that a task or operation causing less heat is assigned to a die region having higher wear-out with respect to another die region because the disclosure of Inoue shows that it was known to those of ordinary skill in the pertinent art to improve a system and method for thermal management using processing task scheduling to provide for ordering tasks or operations based on an amount of heat generated when executing and assigning them such that a task or operation causing less heat is assigned to a die region having higher wear-out with respect to another die region for the purpose of sensing thermal characteristics of hardware, estimating thermal characteristics of tasks to be scheduled, and using this information to balance the thermal load among the hardware (Inoue, Id.).
Arora in view of Moyer and Inoue does not more particularly teach that such tasks or operations assigned based on thermal characteristics are more specifically threads. However, Bose does teach: [wherein the tasks or operations are] threads (Bose, e.g., ¶37, “thread history table 122 may include … temperature information … such that threads can be assigned based on the resulting thermal profile of a combination of threads …”) for the purpose of appropriately managing allocation of threads to hardware based on a thermal profile for a plurality of threads and a risk of raising hardware temperature above a critical threshold (Bose, e.g., ¶¶34-39).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system and method for thermal aware placement and compute dispatch as taught by Arora in view of Moyer and Inoue to provide that such tasks or operations assigned based on thermal characteristics are more specifically threads because the disclosure of Bose shows that it was known to those of ordinary skill in the pertinent art to improve a system and method for enhancing the operating efficiency of processing hardware to provide that such tasks or operations assigned based on thermal characteristics are more specifically threads for the purpose of appropriately managing allocation of threads to hardware based on a thermal profile for a plurality of threads and a risk of raising hardware temperature above a critical threshold (Bose, Id.).
Claim 38 is rejected under 35 U.S.C. § 103 as being unpatentable over Arora in view of Moyer, and in further view of Naik et al., U.S. 2018/0189135 A1 (“Naik”).
Regarding claim 38, the rejection of claim 34 is incorporated, but Arora in view of Moyer does not more particularly teach that the wear spreading logic is operative to produce fault detection information by producing data indicative of an error rate exceeding a threshold. However, Naik does teach: wherein the first and second thermal wear spreading logic is operative to produce fault detection information by producing data indicating at least one of: an error rate exceeds a threshold or logic timing delays exceed a threshold (Naik, e.g., ¶39, “if the error data 176 indicates that an error count or error rate that exceeds a first threshold amount, the post-write read engine 122 may send a signal to the block manager 142 indicating a first error characteristic of the destination block … block manager 142 may perform a corrective operation that results in the block 118 not being used …” See also, e.g., ¶¶40-41, disclosing other use of thresholds, including one that indicates a likelihood of early failure for the block; also note at least ¶¶20 and 24, describing the purpose of collecting this information and managing the use of the blocks such as to level wear throughout the physical memory) for the purpose of identifying one or more bad memory blocks based on a variety of observed characteristics of the regions in response to memory operations and to perform wear leveling operations (Naik, e.g., ¶¶20-41).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system and method for thermal aware placement and compute dispatch as taught by Arora in view of Moyer to provide that the wear spreading logic is operative to produce fault detection information by producing data indicative of an error rate exceeding a threshold because the disclosure of Naik shows that it was known to those of ordinary skill in the pertinent art to improve a system and method for memory hardware health data management and wear leveling to provide that the wear spreading logic is operative to produce fault detection information by producing data indicative of an error rate exceeding a threshold for the purpose of identifying one or more bad memory blocks based on a variety of observed characteristics of the regions in response to memory operations and to perform wear leveling operations (Naik, Id.).
Conclusion
Examiner has identified particular references contained in the prior art of record within the body of this action for the convenience of Applicant. Although the citations made are representative of the teachings in the art and are applied to the specific limitations within the enumerated claims, the teaching of the cited art as a whole is not limited to the cited passages. Other passages and figures may apply. Applicant, in preparing the response, should consider fully the entire reference as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art and/or disclosed by Examiner.
Examiner respectfully requests that, in response to this Office Action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
When responding to this Office Action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
Examiner interviews are available via telephone and video conferencing using a USPTO-supplied web-based collaboration tool. Applicant is encouraged to submit an Automated Interview Request (AIR) which may be done via https://www.uspto.gov/patent/uspto-automated-interview-request-air-form, or may contact Examiner directly via the methods below.
Any inquiry concerning this communication or earlier communication from Examiner should be directed to Andrew M. Lyons, whose telephone number is (571) 270-3529, and whose fax number is (571) 270-4529. The examiner can normally be reached Monday to Friday from 10:00 AM to 6:00 PM ET. If attempts to reach Examiner by telephone are unsuccessful, Examiner’s supervisor, Wei Mui, can be reached at (571) 272-3708. Information regarding the status of an application may be obtained from the Patent Center system. For more information about the Patent Center system, see https://www.uspto.gov/patents/apply/patent-center. If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800) 786-9199 (in USA or Canada) or (571) 272-1000.
/Andrew M. Lyons/Primary Examiner, Art Unit 2191
1 As all references cited in this action are included in the 20 August 2024 IDS, they have not been cited on a PTO-892
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