DETAILED ACTION
Applicant’s response filed 2/3/26 has been considered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-23 are pending.
Prior Double Patenting rejections are maintained. See prior office action for details.
Prior art rejections are maintained. No amendments were made to the claims.
Application is pending.
Response to Arguments
Applicant's arguments filed 2/3/26 have been fully considered but they are not persuasive.
For example, claim 1 recites:
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Applicant contends, the prior art does not teach reserving a first portion of hardware resources of the memory system for first functions; and allocating a second portion of the hardware resources for second functions for a second mode.
The Examiner respectfully disagrees.
Essential this limitation broadly states to allocate portion of the resources for first functions and then another portion for second functions in a second mode which is not needed or used for the first mode. Basically this means that when the starting up in a first mode only a portion of the hardware resources are used which is very broad and obvious over the prior art.
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The prior art D1 (Grossman) teaches (i.e., Figure 1 and related text) enhanced logic & control 150 may be configured to monitor the status of signals that indicate the beginning and the completion of the DRAM (e.g., when memory 100 is a DRAM) operations. Such signals include, but are not limited to, signals such as row address strobe (RAS), column address strobe (CAS), clock enable (CKE), other DRAM internal signals, or other DRAM signals that are received or sent via the external interfaces of the DRAM. In certain examples, enhanced logic & control 150 may be configured to monitor whether any operation that requires a change to a state of a memory cell in memory 100 has completed. As an example, enhanced logic & control 150 may be configured to detect whether memory 100 is performing a write operation or a read operation. In one example, enhanced logic & control 150 may initiate tasks (e.g., starting a new background function) based on certain new DRAM commands initiated by the host (e.g., a CPU). Such commands may be initiated based on new combinations of the existing DRAM signals (e.g., RAS, CAS, CKE, or WE) and based on new bits for use with the mode registers associated with the DRAM. As an example, enhanced logic & control 150 may access mode registers (e.g., MR0 through MR3) via a standard LOAD MODE command. Enhanced logic & control 150 may be configured to process functions using its compute resources, including registers and storage resources of memory 100. Example functions include but are not limited to: Find First Occurrence, Count Occurrences, Checksum Function, Clear to Constant, Test for Constant, Read Masked, Constant Write Masked, and Error Detection and Correction.
The enhanced logic & control 150 may be configured to operate memory 100 in two different modes. In a first mode, after a host (e.g., a CPU coupled to memory 100) issues an instruction or command to memory 100 to run certain functions in background then memory 100 may opportunistically run the functions in the background without additional instructions from the host. In a second mode, the host may have complete control over when memory 100 is allowed to run any functions in the background. As an example, in the first mode, enhanced logic & control 150 may be configured to keep track of a status of a function running in the background. Enhanced logic & control 150 may be further configured to suspend the function running in the background and resume the function running in the background. Enhanced logic & control 150 may accomplish this by keeping track of the status of signals that indicate the beginning and the completion of the DRAM (e.g., when memory 100 is a DRAM) operations. Such signals include, but are not limited to, signals such as row address strobe (RAS), column address strobe (CAS), clock enable (CKE), other DRAM internal signals, or other DRAM signals that are received or sent via the external interfaces of the DRAM. Thus, as an example, enhanced logic & control 150 may be configured to monitor a status of the RAS and CAS signals. If for a certain pre-configured amount of time, these signals are inactive, then enhanced logic & control 150 may initiate or resume a function that the host had requested memory 100 to perform. Any intermediate results generated during the processing of the function or functions may be stored in internal registers associated with memory 100. Either host could keep track of a status of the function or enhanced logic & control 150 may be configured to keep track of the status of the function.
Therefore D1 substantially teaches to use a portion of the hardware resources for first functions (i.e., read) and another portion of the hardware resources for second functions (i.e., write). Running certain functions in a first mode clearly indicates that a portion of the hardware resources are used for the first functions.
It is the Examiner’s conclusion that the claims of the present application, as presented, are not patentably distinct over the prior art. Applicant is encouraged to formulate claim language that clearly defines the novelty of the application. Prior art rejections are maintained in view of remarks made herein. See prior office action. If Applicant believes an interview might be useful then they are welcome to contact the Examiner with proposed amendments for a discussion.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUJTABA M CHAUDRY whose telephone number is (571)272-3817. The examiner can normally be reached Monday-Friday 9am-5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert DeCady can be reached at 571-272-3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MUJTABA M. CHAUDRY
Primary Examiner
Art Unit 2112
/MUJTABA M CHAUDRY/Primary Examiner, Art Unit 2112