Prosecution Insights
Last updated: July 17, 2026
Application No. 18/809,872

COMPACT PHOTONIC PROCESSOR ARCHITECTURE

Non-Final OA §102§103
Filed
Aug 20, 2024
Priority
Aug 21, 2023 — provisional 63/520,781
Examiner
BOOHER, ADAM W
Art Unit
Tech Center
Assignee
Lightmatter Inc.
OA Round
1 (Non-Final)
75%
Grant Probability
Favorable
1-2
OA Rounds
10m
Est. Remaining
85%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allowance Rate
385 granted / 512 resolved
+15.2% vs TC avg
Moderate +10% lift
Without
With
+9.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
21 currently pending
Career history
532
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
92.0%
+52.0% vs TC avg
§102
2.9%
-37.1% vs TC avg
§112
2.9%
-37.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 512 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of Claims Claims 1-20 are pending. Claims 3, 7-8, and 19 are objected to and have been deemed to contain allowable subject matter. Information Disclosure Statement The information disclosure statement filed 12/11/2024 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. It has been placed in the application file, but the information referred to therein has not been considered. Specifically, the following Non-Patent Literature Documents are listed on the IDS filed 12/11/2024, but lack a copy in the application file: Multiplication, Physical Review X, 2019 February 21;9(021032), 11 pages; and Vanhoecke et al. Segmented Optical Transmitter Comprising a CMOS Driver Array and an InP IQ-MZM for Advanced Modulation Formats, Journal of Lightwave Technology, 2017 February 15;35(4): 862-67. The remainder of the IDS filed 12/11/2024, that is the references that are not crossed out, have been considered by the examiner. Drawings The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: “210” (fig. 3A). Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Allowable Subject Matter Claims 3, 7-8, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 3, the claim is objected to for at least the reason that the prior art fails to teach or suggest a photonic processor, wherein: in the first polarity, the first phase shifter causes a clockwise phase shift in the first arm and the second phase shifter causes a counterclockwise phase shift in the second arm, and in the second polarity, the first phase shifter causes a counterclockwise phase shift in the first arm and the second phase shifter causes a clockwise phase shift in the second arm, as generally set forth in claim 3, the invention including the totality of the particular limitations recited in claim 3 and claims 1 and 2, from which claim 3 depends. Regarding claim 7, the claim is objected to for at least the reason that the prior art fails to teach or suggest a photonic processor wherein the plurality of optical phase shifters of the first segment have different numbers of doped wells relative to one another, as generally set forth in claim 7, the invention including the totality of the particular limitations recited in claim 7 and claim 1, from which claims 7 depends. Regarding claim 8, the claim is objected to for at least the reason that it depends from claim 7. Regarding claim 19, the claim is objected to for at least the reason that the prior art fails to teach or suggest a photonic processor wherein the plurality of optical phase shifters of the first segment have difference numbers of doped wells relative to one another, as generally set forth in claim 19, the invention including the totality of the particular limitations recited in claim 19 and claims 16-18, from which claim 19 depends. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 11-13, 15-16, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Harris et al. (US 2021/0333818) (hereafter Harris). Regarding claim 11, Harris discloses a method for performing matrix multiplication using a photonic processor, comprising: obtaining a vector of input values and a matrix of parameters; and performing matrix multiplication between the matrix and the vector at least in part by controlling a plurality of phase shifters of an optical interferometer of the photonic processor, wherein controlling the plurality of phase shifters comprises: setting a polarity of each phase shifter of the plurality of phase shifters based on a respective parameter of the matrix; and causing each phase shifter of the plurality of phase shifters to phase shift light traveling in the optical interferometer based on the set polarity and by an amount set by a respective input value of the vector (see at least the abstract Figs. 1A, 1B, and 5B and paragraphs [0118] and [0142]-[0143]). Regarding claim 12¸ Harris discloses all of the limitations of claim 11. Harris also discloses that performing the matrix multiplication between the matrix and the vector further comprises detecting the light traveling in the optical interferometer using a differential optical receiver (see at least Fig. 5B and paragraph [0111], where 33 is a coherent detector that detects the difference in the phases). Regarding claim 13¸ Harris discloses all of the limitations of claim 12. Harris also discloses that the optical interferometer comprises first and second arms, wherein detecting the light traveling in the optical interferometer using the differential optical receiver comprises detecting a first optical output generated by combining light traveling in the first arm with light traveling in the second arm and a second optical output generated by combining the light traveling in the first arm with the light traveling in the second arm (see at least Fig. 5B and paragraph [0111]). Regarding claim 15, Harris discloses all of the limitations of claim 11. Harris also discloses that causing each phase shifter of the plurality of phase shifters to phase shift light traveling in the optical interferometer comprises causing a plurality of digital-to-analog converters (DAC) to generate a plurality of differential voltages encoded with the input values of the vector (see at least Fig. 5B and paragraphs [0118] and [0142]-[0143]). Regarding claim 16, Harris discloses a photonic processor, comprising: a controller configured to obtain a vector of input values and a matrix of parameters (see at least Fig. 1A and paragraph [0046], where the system can include a controller); an optical interferometer comprising a first output and a plurality of optical phase shifters (see at least Fig. 5B and paragraphs [0118] and [0142]-[0143]); a plurality of signal drivers, each signal driver of the plurality of signal drivers being configured to control a respective phase shifter to phase shift light traveling in the optical interferometer (see at least Fig. 5B and paragraph [0141], where the signals A11 through A44 are generated by signal drivers) based on: a polarity set by a respective parameter of the matrix, and an amount set by a respective input value of the vector (see at least Fig. 5B and paragraphs [0142]-[0143]); and an optical receiver coupled to the first output of the optical interferometer (see at least Fig. 5B and paragraph [0111], where 33 is a coherent detector that detects the difference in the phases). Regarding claim 20, Harris discloses all of the limitations of claim 16. Harris also discloses that the optical interferometer comprises a second output, wherein the optical receiver is further coupled to the second output of the optical interferometer (see at least Fig. 5B). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-2, 4-6, 9-10, 14, and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Harris et al. (US 2021/0333818) (hereafter Harris), in view of Hosseinzadeh et al. (US 2021/0173238) (hereafter Hosseinzadeh). Regarding claim 1, Harris discloses a photonic processor (see at least the abstract), comprising: a first optical interferometer having a plurality of segments, wherein each segment of the plurality of segments comprises optical phase shifters (see at least Figs. 4C and 5B and paragraphs [0109]-[0110]; a plurality of differential transmission lines (see at least Figs. 3B, 4C, and 5B and paragraphs [0094], [0112], and [0125]), each transmission line of the plurality of differential transmission lines coupling a digital-to-analog converter (DAC) to a respective segment of the first optical interferometer (see at least Figs. 4A and 5B and paragraph [0118]); a first plurality of signal drivers, each signal driver of the first plurality of signal drivers coupling a first differential transmission line to a respective phase shifter of a first segment of the plurality of segments (see at least Fig. 5B and paragraph [0141], where the signals A11 through A44 are generated by signal drivers); and a differential optical receiver coupled to an output of the first optical interferometer (see at least Fig. 5B and paragraph [0111], where 33 is a coherent detector that detects the difference in the phases). Harris does not specifically disclose that each segment of the plurality of segments comprises a plurality of optical phase shifters having different dimensions relative to one another. However, Hosseinzadeh teaches an optoelectronic matrix multiplication unit comprising an optical interferometer comprising a plurality of optical phase shifters having different dimensions relative to one another (see at least Figs. 1, 8, and 13, and paragraph [0152], where 3956a-c are phase shifters having different lengths). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the photonic processor of Harris to include the teachings of Hosseinzadeh so that each segment of the plurality of segments comprises a plurality of optical phase shifters having different dimensions relative to one another for the purpose of using a segmented design to provide optical digital-to-analog conversion using separated phase shifts for each bit of a digital input signal (see at least paragraph [0152] of Hosseinzadeh). Regarding claim 2, Harris as modified by Hosseinzadeh discloses all of the limitations of claim 1. Harris also discloses that each signal driver of the first plurality of signal drivers is configured to control the respective phase shifter based on a digital input having either a first state or a second state, wherein: in the first state, the signal driver drives the respective phase shifter in accordance with a first polarity, and in the second state, the signal driver drives the respective phase shifter in accordance with a second polarity (see at least Fig. 5B and paragraph [0143]). Regarding claim 4, Harris as modified by Hosseinzadeh discloses all of the limitations of claim 1. Harris also discloses a second plurality of signal drivers, each signal driver of the second plurality of signal drivers coupling a second differential transmission line to a respective phase shifter of a second segment of the plurality of segments (see at least fig. 5B). Regarding claim 5, Harris as modified by Hosseinzadeh discloses all of the limitations of claim 1. Hosseinzadeh also teaches that the plurality of optical phase shifters of the first segment have dimensions arranged in accordance with a binary scale. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the photonic processor of Harris as modified by Hosseinzadeh to include the further teachings of Hosseinzadeh so that the plurality of optical phase shifters of the first segment have dimensions arranged in accordance with a binary scale for the purpose of using a segmented design to provide optical digital-to-analog conversion using separated phase shifts for each bit of a digital input signal (see at least paragraph [0152] of Hosseinzadeh). Regarding claim 6, Harris as modified by Hosseinzadeh discloses all of the limitations of claim 1. Hosseinzadeh also teaches that the plurality of optical phase shifters of the first segment have doped well of different lengths relative to one another (see at least Fig. 9 and paragraph [0154]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the photonic processor of Harris as modified by Hosseinzadeh to include the further teachings of Hosseinzadeh so that the plurality of optical phase shifters of the first segment have doped well of different lengths relative to one another for the purpose of controlling the corresponding optical phase shift applied by the phase shifter (see at least paragraph [0155] of Hosseinzadeh). Regarding claim 9, Harris as modified by Hosseinzadeh discloses all of the limitations of claim 1. Harris also discloses a second optical interferometer having a plurality of segments (see at least Fig. 5B). Hosseinzadeh also teaches that each segment of a plurality of segments of the second optical interferometer comprises a plurality of optical phase shifters having different dimensions relative to one another (see at least Figs. 1, 8, and 13, and paragraph [0152], where 3956a-c are phase shifters having different lengths). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the photonic processor of Harris to include the teachings of Hosseinzadeh so that each segment of a plurality of segments of the second optical interferometer comprises a plurality of optical phase shifters having different dimensions relative to one another for the purpose of using a segmented design to provide optical digital-to-analog conversion using separated phase shifts for each bit of a digital input signal (see at least paragraph [0152] of Hosseinzadeh). Regarding claim 10, Harris as modified by Hosseinzadeh discloses all of the limitations of claim 1. Harris also discloses that each transmission line of the plurality of differential transmission lines couples a DAC to a respective segment of the second optical interferometer, and each signal driver of the first plurality of signal drivers couples the first differential transmission line to a respective phase shifter of a first segment of the plurality of segments of the second optical interferometer (see at least Fig. 5B). Regarding claim 14¸ Harris discloses all of the limitations of claim 11. Harris also discloses that the plurality of phase shifters are grouped in segments (see at least Fig. 5B). Harris does not specifically disclose that the phase shifters of a first segment of the plurality of segments have different dimensions relative to one another. However, Hosseinzadeh teaches an optoelectronic matrix multiplication unit comprising an optical interferometer comprising a plurality of optical phase shifters having different dimensions relative to one another (see at least Figs. 1, 8, and 13, and paragraph [0152], where 3956a-c are phase shifters having different lengths). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Harris to include the teachings of Hosseinzadeh so that the phase shifters of a first segment of the plurality of segments have different dimensions relative to one another for the purpose of using a segmented design to provide optical digital-to-analog conversion using separated phase shifts for each bit of a digital input signal (see at least paragraph [0152] of Hosseinzadeh). Regarding claim 17¸ Harris discloses all of the limitations of claim 16. Harris also discloses that the plurality of phase shifters are grouped in segments (see at least Fig. 5B). Harris does not specifically disclose that the phase shifters of a first segment of the plurality of segments have different dimensions relative to one another. However, Hosseinzadeh teaches an optoelectronic matrix multiplication unit comprising an optical interferometer comprising a plurality of optical phase shifters having different dimensions relative to one another (see at least Figs. 1, 8, and 13, and paragraph [0152], where 3956a-c are phase shifters having different lengths). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the photonic processor of Harris to include the teachings of Hosseinzadeh so that the phase shifters of a first segment of the plurality of segments have different dimensions relative to one another for the purpose of using a segmented design to provide optical digital-to-analog conversion using separated phase shifts for each bit of a digital input signal (see at least paragraph [0152] of Hosseinzadeh). Regarding claim 18, Harris as modified by Hosseinzadeh discloses all of the limitations of claim 17. Hosseinzadeh also teaches that the plurality of optical phase shifters of the first segment have dimensions arranged in accordance with a binary scale. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the photonic processor of Harris as modified by Hosseinzadeh to include the further teachings of Hosseinzadeh so that the plurality of optical phase shifters of the first segment have dimensions arranged in accordance with a binary scale for the purpose of using a segmented design to provide optical digital-to-analog conversion using separated phase shifts for each bit of a digital input signal (see at least paragraph [0152] of Hosseinzadeh). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 8,620,115 to Webster et al. discloses an optical modulator comprising an interferometer with phase shifters having different dimensions (see at least the abstract and Fig. 7). Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM W BOOHER whose telephone number is (571)270-0573. The examiner can normally be reached M - F: 8:00am - 4:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Stephone Allen can be reached at 571-272-2434. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /A.W.B./ Examiner, Art Unit 2872 /STEPHONE B ALLEN/ Supervisory Patent Examiner, Art Unit 2872
Read full office action

Prosecution Timeline

Aug 20, 2024
Application Filed
Jun 10, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
75%
Grant Probability
85%
With Interview (+9.6%)
2y 9m (~10m remaining)
Median Time to Grant
Low
PTA Risk
Based on 512 resolved cases by this examiner. Grant probability derived from career allowance rate.

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