DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on 06/24/2026 have been fully considered but they are not persuasive due to the following: -
With respect to (Claim 14, ---, be correct. /A); Applicant argues in bullet A, page 1 of Remarks filed on 06/24/2026. In accordance with broadest reasonable interpretation, the Examiner respectfully disagrees because the Applicant's analysis is fully incorrect and completely irrelevant to address the antecedent basis pertinent to claim 14, because the first appearance of element "a fifth transistor" is in claim 6, thus, the second appearance of the same element should be addressed as "the fifth transistor".
With respect to (Claim 1, ---, by claim 1. /B); Applicant argues in bullet B, page 1 of Remarks filed on 06/24/2026. In accordance with broadest reasonable interpretation, the Examiner respectfully disagrees because the Applicant's analysis is fully incorrect and completely irrelevant to address claim 1, because the circuit of fig. 2/Singh-081 does provide an ESD protection to transistor 214 and transistor 214 is the first transistor and is in parallel with the fourth transistor 120. The Examiner does not understand how come the Applicant came to these fully incorrect deductions, because circuit of fig. 2/Singh-081 is loud and clear and does not require any further analysis whatsoever. Again, fig. 2/Singh-081 does teach and suggest an ESD protection circuit having the first transistor 214 in parallel with the transistors string second-transistor/116, third-transistor/118 and in parallel with the fourth transistor 120.
With respect to (Claim 1 still, ---, (214). /C); Applicant argues in bullet C, pages 1-2 of Remarks filed on 06/24/2026. In accordance with broadest reasonable interpretation, the Examiner respectfully disagrees because the Applicant's analysis is fully incorrect and completely irrelevant to address the capacitor feature that is recited in claim 1, because the circuit of fig. 11a/Singh-841 does provide an ESD protection having the capacitor 1120 clamped to the terminals VDD, gate/BIGFET, respectively, plain and simple. The Examiner does not understand how come the Applicant came to these fully incorrect deductions, because the circuit of fig. 2/Singh-841 is loud and clear and does not require any further analysis whatsoever. Again, fig. 11a/Singh-841 does teach and suggest an ESD protection having the capacitor 1120 clamped to the terminals VDD, gate/BIGFET.
With respect to (In view, ---, from claim 1. /D); Applicant argues in bullet D, page 2 of Remarks filed on 06/24/2026. In accordance with broadest reasonable interpretation, the Examiner respectfully disagrees because the Applicant's analysis is fully incorrect and completely irrelevant to address the features/limitations that are recited in claim 1 as discussed above. Again, the combination of Singh (US Publication No. 20130170081), Altolaguirre et al (US Publication No. 20140063663) and Singh (US Publication No. 20190006841) does teach and suggest functional wise and component wise every single feature/limitation required by claim 1.
With respect to (New claims, ---, connections. /E); Applicant argues in bullet E, page 2 of Remarks filed on 06/24/2026. In accordance with broadest reasonable interpretation, the Examiner respectfully agrees, thence, claims 17-24 are allowed.
Therefore, the formalities objection to claim 14, the rejection of claims 1-5, 9-13 and 16, the objection to claims 6-8 and 14-15, and the allowance of claims 17-24 are all maintained.
Claim Objections
Claim 14 is objected to because of the following informalities:
In claim 14 line 1, “a fifth transistor” ---, should be corrected to ---, “the fifth transistor” ---.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 10-13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Singh (US Publication No. 20130170081) in view of Altolaguirre et al (US Publication No. 20140063663) and further in view of Singh (US Publication No. 20190006841).
Regarding claim 1, Singh discloses an electrostatic discharge protection circuit (i.e., such as electrostatic discharge protection circuit ESD 100; see for example fig. 2, para. [0060]- [0070]) for a first transistor (i.e., such as first transistor NFET 214; see for example fig. 2, para. [0060]- [0070]) of a first type (i.e., such as first type N-type as NFET; see for example fig. 2, para. [0060]- [0070]), comprising: a second transistor (i.e., such as second transistor NFET 116; see for example fig. 2, para. [0060]- [0070]) of the first type (i.e., such as first type N-type as NFET; see for example fig. 2, para. [0060]- [0070]) in series with a third transistor (i.e., such as third transistor PFET 118; see for example fig. 2, para. [0060]- [0070]) of a second type (i.e., such as second type P-type as PFET; see for example fig. 2, para. [0060]- [0070]) different from the first type (i.e., such as first type N-type as NFET; see for example fig. 2, para. [0060]- [0070]), wherein the second (i.e., such as second transistor NFET 116; see for example fig. 2, para. [0060]- [0070]) and third transistors (i.e., such as third transistor PFET 118; see for example fig. 2, para. [0060]- [0070]) in series (of course) are connected between the first conduction terminal (i.e., such as first conduction terminal Vdd; see for example fig. 2, para. [0060]- [0070]) of said first transistor (i.e., such as first transistor NFET 214; see for example fig. 2, para. [0060]- [0070]) and the second conduction terminal (i.e., such as second conduction terminal GND; see for example fig. 2, para. [0060]- [0070]) of said first transistor (i.e., such as first transistor NFET 214; see for example fig. 2, para. [0060]- [0070]); a first inverter (i.e., such as first inverter 220; for instance, NFET 214 is driven by inverter 220 via coupling transistor NFET 240; see for example fig. 2, para. [0060]- [0070]) coupling a control terminal (i.e., such as control terminal gate/drive terminal of NFET 214; see for example fig. 2, para. [0060]- [0070]) of said first transistor (i.e., such as first transistor NFET 214; see for example fig. 2, para. [0060]- [0070]) to a control terminal (i.e., such as control terminal gate/drive terminal of NFET 116; for instance, NFET 116 is driven by inverter 234; see for example fig. 2, para. [0060]- [0070]) of said second transistor (i.e., such as second transistor NFET 116; see for example fig. 2, para. [0060]- [0070]); a fourth transistor (i.e., such as fourth transistor BIGFET 120; see for example fig. 2, para. [0060]- [0070]) in parallel with said first transistor (i.e., such as first transistor NFET 214; see for example fig. 2, para. [0060]- [0070]), wherein a control terminal (i.e., such as control terminal gate/drive terminal of BIGFET 120; see for example fig. 2, para. [0060]- [0070]) of said fourth transistor (i.e., such as fourth transistor BIGFET 120; see for example fig. 2, para. [0060]- [0070]) is coupled to a junction point (i.e., such as junction point of elements 118, 116, 242, 244, and the gate of BIGFET 120; see for example fig. 2, para. [0060]- [0070]) of said second transistor (i.e., such as second transistor NFET 116; see for example fig. 2, para. [0060]- [0070]) and third transistor (i.e., such as third transistor PFET 118; see for example fig. 2, para. [0060]- [0070]).
Singh does not explicitly disclose; N diodes in series between a first conduction terminal of said first transistor and a second conduction terminal of said first transistor, N being an integer, wherein a turn-on voltage of the N diodes in series is greater, whatever the temperature, than a power supply voltage; wherein a control terminal of said third transistor is coupled to an anode of said N diodes.
Altolaguirre discloses a power-rail ESD circuit (i.e., such ESD circuit 1; see for example fig. 5, para. [0039]- [0050]); wherein N diodes in series (i.e., such as N diodes in series string 210; see for example fig. 5, para. [0039]- [0050]) between a first conduction terminal (i.e., such as first conduction terminal VDD; see for example fig. 5, para. [0039]- [0050]) of said first transistor (i.e., such as first transistor 10; see for example fig. 5, para. [0039]- [0050]) and a second conduction terminal (i.e., such as second conduction terminal VSS; see for example fig. 5, para. [0039]- [0050]) of said first transistor (i.e., such as first transistor 10; see for example fig. 5, para. [0039]- [0050]), N being an integer (i.e., such as N being integer; for instance, the number of diodes 1102 N may be any number as desired per the chip design; see for example fig. 5, para. [0039]- [0050]), wherein a turn-on voltage (i.e., such as turn-on voltage of diode 1002; see for example fig. 5, para. [0039]- [0050]) of the N diodes in series (of course) (i.e., such as N diodes in series string 210; see for example fig. 5, para. [0039]- [0050]) is greater (i.e., such as greater per the chip design/fabrication; for instance, see the voltage-temperature characteristics in TABLE II, para. [0064]), whatever the temperature (i.e., such as temperature versus voltage applied; for instance, see the voltage-temperature characteristics in TABLE II, para. [0064]), than a power supply voltage (i.e., such as power supply voltage VDD; for instance, see the voltage-temperature characteristics in TABLE II, para. [0064]); wherein a control terminal (i.e., such as control terminal gate/driver of transistor Mp; see for example fig. 5, para. [0039]- [0050]) of said third transistor (i.e., such as third transistor Mp; see for example fig. 5, para. [0039]- [0050]) is coupled to an anode (i.e., such as anode of diode 1002; see for example fig. 5, para. [0039]- [0050]) of said N diodes (i.e., such as N diodes in series string 210; see for example fig. 5, para. [0039]- [0050]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the diode string in Singh, as taught by Altolaguirre, as it provides the advantage of optimizing the circuit design towards protection against voltage spikes, and dissipating energy to the ground.
Neither Singh nor Altolaguirre explicitly discloses a first capacitor arranged between the control terminal of said fourth transistor and the first conduction terminal of said first transistor.
Singh discloses a compact RC triggered ESD clamp (i.e., such as ESD circuit 1105; see for example fig. 11a, para. [0050]); wherein a first capacitor (i.e., such as first capacitor 1120; see for example fig. 11a, para. [0050]) arranged between the control terminal (i.e., such as control terminal gate/driver terminal Trig og the transistor BIGFET; see for example fig. 11a, para. [0050]) of said fourth transistor (i.e., such as fourth transistor BIGFET; see for example fig. 11a, para. [0050]) and the first conduction terminal (i.e., such as first conduction terminal VDD; see for example fig. 11a, para. [0050]) of said first transistor (i.e., such as first transistor P1; see for example fig. 11a, para. [0050]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the capacitor in Singh, as taught by Singh, as it provides the advantage of optimizing the circuit design towards slowing down the voltage rise time as well as reducing the peak voltage stress during the ESD event.
Regarding claim 2, Singh in view Altolaguirre and further in view of Singh and the teachings of Singh as modified by Altolaguirre have been discussed above. Also, the teachings of Singh as modified by Singh have been discussed above as well.
Altolaguirre further discloses the power-rail ESD circuit (i.e., such ESD circuit 1; see for example fig. 5, para. [0039]- [0050]); further comprising a first resistor (i.e., such as first resistor R; see for example fig. 5, para. [0039]- [0050]) coupling said anode (i.e., such as anode of diode 1002; see for example fig. 5, para. [0039]- [0050]) of said N diodes (i.e., such as N diodes in series string 210; see for example fig. 5, para. [0039]- [0050]) and the first conduction terminal (i.e., such as first conduction terminal VDD; see for example fig. 5, para. [0039]- [0050]) of said first transistor (i.e., such as first transistor 10; see for example fig. 5, para. [0039]- [0050]).
Regarding claim 3, Singh in view Altolaguirre and further in view of Singh and the teachings of Singh as modified by Altolaguirre have been discussed above. Also, the teachings of Singh as modified by Singh have been discussed above as well.
Altolaguirre further discloses the power-rail ESD circuit (i.e., such ESD circuit 1; see for example fig. 5, para. [0039]- [0050]); wherein N (i.e., such as N being integer; for instance, the number of diodes 1102 N may be any number as desired per the chip design; see for example fig. 5, para. [0039]- [0050]) is between ten and twenty (i.e., such as number of diodes 1002 may be any count as desired per the chip design; for instance, conducting string 210 can be composed of one or a plurality of diodes 1002. The number of diodes 1002 in the string is determined according to the desired threshold voltage. In one embodiment, the number of diodes is process dependent; see for example fig. 5, para. [0039]- [0050]).
Regarding claim 4, Singh in view Altolaguirre and further in view of Singh and the teachings of Singh as modified by Altolaguirre have been discussed above. Also, the teachings of Singh as modified by Singh have been discussed above as well.
Altolaguirre further discloses the power-rail ESD circuit (i.e., such ESD circuit 1; see for example fig. 5, para. [0039]- [0050]); wherein N (i.e., such as N being integer; for instance, the number of diodes 1102 N may be any number as desired per the chip design; see for example fig. 5, para. [0039]- [0050]) is equal to fourteen (i.e., such as number of diodes 1002 may be any count as desired per the chip design; for instance, conducting string 210 can be composed of one or a plurality of diodes 1002. The number of diodes 1002 in the string is determined according to the desired threshold voltage. In one embodiment, the number of diodes is process dependent; see for example fig. 5, para. [0039]- [0050]).
Regarding claim 5, Singh in view Altolaguirre and further in view of Singh and the teachings of Singh as modified by Altolaguirre have been discussed above. Also, the teachings of Singh as modified by Singh have been discussed above as well.
Singh further discloses the electrostatic discharge protection circuit (i.e., such as electrostatic discharge protection circuit ESD 100; see for example fig. 2, para. [0060]- [0070]); further comprising a second resistor (i.e., such as second resistor 244; see for example fig. 2, para. [0060]- [0070]) coupling said control terminal (i.e., such as control terminal gate/drive terminal of BIGFET 120; see for example fig. 2, para. [0060]- [0070]) of said fourth transistor (i.e., such as fourth transistor BIGFET 120; see for example fig. 2, para. [0060]- [0070]) to said second conduction terminal (i.e., such as second conduction terminal GND; see for example fig. 2, para. [0060]- [0070]) of said first transistor (i.e., such as first transistor NFET 214; see for example fig. 2, para. [0060]- [0070]).
Regarding claim 10, Singh in view Altolaguirre and further in view of Singh and the teachings of Singh as modified by Altolaguirre have been discussed above. Also, the teachings of Singh as modified by Singh have been discussed above as well.
Singh further discloses the electrostatic discharge protection circuit (i.e., such as electrostatic discharge protection circuit ESD 100; see for example fig. 2, para. [0060]- [0070]); wherein said second conduction terminal (i.e., such as second conduction terminal GND; see for example fig. 2, para. [0060]- [0070]) of said first transistor (i.e., such as first transistor NFET 214; see for example fig. 2, para. [0060]- [0070]) is configured to receive a reference voltage (i.e., such as second conduction terminal/reference voltage GND; see for example fig. 2, para. [0060]- [0070]).
Regarding claim 11, Singh in view Altolaguirre and further in view of Singh and the teachings of Singh as modified by Altolaguirre have been discussed above. Also, the teachings of Singh as modified by Singh have been discussed above as well.
Singh further discloses the electrostatic discharge protection circuit (i.e., such as electrostatic discharge protection circuit ESD 100; see for example fig. 2, para. [0060]- [0070]); wherein the reference voltage (i.e., such as second conduction terminal/reference voltage GND; see for example fig. 2, para. [0060]- [0070]) is the ground (i.e., such as second conduction terminal/reference voltage GND; see for example fig. 2, para. [0060]- [0070]).
Regarding claim 12, Singh in view Altolaguirre and further in view of Singh and the teachings of Singh as modified by Altolaguirre have been discussed above. Also, the teachings of Singh as modified by Singh have been discussed above as well.
Singh further discloses the electrostatic discharge protection circuit (i.e., such as electrostatic discharge protection circuit ESD 100; see for example fig. 2, para. [0060]- [0070]); wherein the first conduction terminal (i.e., such as first conduction terminal Vdd; see for example fig. 2, para. [0060]- [0070]) of said first transistor (i.e., such as first transistor NFET 214; see for example fig. 2, para. [0060]- [0070]) is configured as an output node (i.e., such as first conduction terminal Vdd-I/O terminal; for instance, some embodiments may be used as part of the input-output (I/O) ring design of a chip; see for example fig. 2, para. [0060]- [0070]).
Regarding claim 13, Singh in view Altolaguirre and further in view of Singh and the teachings of Singh as modified by Altolaguirre have been discussed above. Also, the teachings of Singh as modified by Singh have been discussed above as well.
Singh further discloses the electrostatic discharge protection circuit (i.e., such as electrostatic discharge protection circuit ESD 100; see for example fig. 2, para. [0060]- [0070]); wherein said first (i.e., such as first transistor NFET 214; see for example fig. 2, para. [0060]- [0070]), second (i.e., such as second transistor NFET 116; see for example fig. 2, para. [0060]- [0070]), third (i.e., such as third transistor PFET 118; see for example fig. 2, para. [0060]- [0070]), fourth transistors (i.e., such as fourth transistor BIGFET 120; see for example fig. 2, para. [0060]- [0070]) are transistors of same technology (i.e., such as transistors of same technology; for instance, shrinking technology challenges have resulted in a need for trigger circuits to trigger larger field effect transistors (BIGFET) in Resistor-Capacitor (RC) coupled or dynamic triggered electrostatic discharge (ESD) networks. It may be advantageous for trigger circuits to have fast response times. Voltage overshoots during an initial part of a clamp's response due to a lag between the application of a pulse and the completion of the turning on mechanism of the trigger circuit may damage the field effect transistors. This may be because the shrinking of the circuit technology has caused a reduction in the gate oxide breakdown voltage (Vbox). A slower response may result in higher voltage overshoots. Therefore, reduced turn on times may be useful for deep sub-micron technologies. In some embodiments the width of the BIGFET may be chosen based on the amount of current which is required to pass through the BIGFET in order to discharge the electrostatic charge. In some embodiments the BIGFET may be implemented using as a two-finger MOSFET or a multi-finger MOSFET. In some embodiments the BIGFET may be implemented from a plurality of units. Some embodiments may achieve the speed and response time of feedback-based circuits whilst providing immunity from the parasitic effects due to pressure, voltage and temperate (PVT) variations and the power supply rail resistance and inductance. Some embodiments may be suitable applications requiring very fast supply ramp rates due to their improved filtering characteristics. In some embodiments the field effect transistors may be MOSFETs or, JFETs. Some embodiments of the trigger circuit may be configured to trigger a variety of clamp structures. For example, the trigger circuit may trigger a BIGFET, grounded-gate NMOS (GGNMOS) and silicon-controlled rectifier (SCR) clamps. In some embodiments small miller capacitors may be placed between the input and output of the inverters 228, 234 of the domino RC delay circuit. These capacitors may reduce the area required to implement some embodiments by increasing the effective time constant of the chain; see for example fig. 2, para. [0060]- [0070]).
Regarding claim 16, Singh in view Altolaguirre and further in view of Singh and the teachings of Singh as modified by Altolaguirre have been discussed above. Also, the teachings of Singh as modified by Singh have been discussed above as well.
Singh further discloses an electronic device (i.e., such as electronic device ESD 100; see for example fig. 2, para. [0060]- [0070]); comprising: said first transistor (i.e., such as first transistor NFET 214; see for example fig. 2, para. [0060]- [0070]); and the electrostatic discharge protection circuit (i.e., such as electrostatic discharge protection circuit ESD 100; see for example fig. 2, para. [0060]- [0070]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Singh (US Publication No. 20130170081) in view of Altolaguirre et al (US Publication No. 20140063663) and in view of Singh (US Publication No. 20190006841) and further in view of Zhao et al (US Publication No. 20180026440).
Regarding claim 9, Singh in view Altolaguirre and further in view of Singh and the teachings of Singh as modified by Altolaguirre have been discussed above. Also, the teachings of Singh as modified by Singh have been discussed above as well.
Neither Singh nor Altolaguirre nor Singh explicitly discloses further comprising a second diode arranged in parallel with said second resistor.
Zhao discloses a high voltage clamp ESD circuit (i.e., such as ESD circuit 50; see for example fig. 2, para. [0055]- [0069]); wherein a second diode (i.e., such as second diode 45; see for example fig. 2, para. [0055]- [0069]) arranged in parallel (i.e., such as elements 43, 44, 45 are all in parallel; see for example fig. 2, para. [0055]- [0069]) with said second resistor (i.e., such as second resistor 43; see for example fig. 2, para. [0055]- [0069]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the diode in Singh, as taught by Zhao, as it provides the advantage of optimizing the circuit design towards providing a low-impedance path to ground for high-voltage transients while allowing normal, low-current signals to pass through the resistor.
Allowable Subject Matter
Claims 6-8 and 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6, Singh in view of Altolaguirre and further in view of Singh teaches the invention set forth above. However, neither Singh nor Altolaguirre nor Singh particularly teaches further comprising a fifth transistor coupled in series with said second resistor between said second conduction terminal of said first transistor and said control terminal of said fourth transistor.
Hence claim 6 will be deemed allowable if rewritten in an independent form.
Regarding claim 7, Singh in view of Altolaguirre and further in view of Singh teaches the invention set forth above. However, neither Singh nor Altolaguirre nor Singh particularly teaches further comprising a second capacitor arranged in series with the first capacitor between said control terminal of said fourth transistor and said first conduction terminal of said first transistor.
Hence claim 7 will be deemed allowable if rewritten in an independent form.
Claim 8 depends on objected claim 7, consequently claim 8 will also be deemed allowable.
Regarding claim 14, Singh in view of Altolaguirre and further in view of Singh teaches the invention set forth above. However, neither Singh nor Altolaguirre nor Singh particularly teaches further comprising a fifth transistor coupling said second resistor to said second conduction terminal of said first transistor, and wherein the fifth transistor is of same technology as said first, second, third, fourth transistors.
Hence claim 14 will be deemed allowable if rewritten in an independent form.
Regarding claim 15, Singh in view of Altolaguirre and further in view of Singh teaches the invention set forth above. However, neither Singh nor Altolaguirre nor Singh particularly teaches wherein said first, second, third, fourth transistors are drift MOS transistors.
Hence claim 15 will be deemed allowable if rewritten in an independent form.
Claims 17-24 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 17, Singh in view of Altolaguirre and further in view of Singh teaches the invention set forth above. However, neither Singh nor Altolaguirre nor Singh particularly teaches an electronic device, comprising: a supply voltage node; a pullup resistor coupled between the supply voltage node and an output node; a first transistor of a first type having a first conduction terminal connected to the output node, a second conduction terminal connected to a reference node; and a first control terminal; and an electrostatic discharge protection circuit for the first transistor, comprising: a second transistor of the first type in series with a third transistor of a second type different from the first type, wherein the second and third transistors are connected between the output node and the reference node; N diodes in series between a third control terminal of the third transistor and the reference node, N being an integer, wherein a turn-on voltage of the N diodes is greater, whatever the temperature, than a power supply voltage at the supply voltage node; a first inverter having an input coupled to the first control terminal of the first transistor and an output coupled to a second control terminal of the second transistor; a fourth transistor having a third conduction terminal connected to the output node, a fourth conduction terminal connected to a reference node; and a fourth control terminal coupled to a junction point of the second transistor and third transistor; and a first capacitor arranged between the fourth control terminal of the fourth transistor and the output node.
Claims 18-24 are allowed, as they depend on allowed claim 17.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUAAMAR Q AL-TAWEEL whose telephone number is (571)270-0339. The examiner can normally be reached 0730-1700.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V Tran can be reached at (571) 270- 1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUAAMAR QAHTAN AL-TAWEEL/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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