DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
I. Election/Restrictions
1. Applicant’s election without traverse of Species 1A including claims 1-12 and 18-20 in the reply filed on 06/16/2026 is acknowledged. Claims 13-17 were not elected.
2. There was no new set of claims filed with said reply with the proper status identifier such as Original, Withdrawn, Canceled, etc. Therefore, the status of claims is improper. Consequently, appropriate correction is required.
Title Objection
3. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Examiner’s Note
4. All the words in the language of the claims of which the specifications do not provide a definition in the form stated in the MPEP, the examiner has interpreted them by their plain meanings, pursuant to the MPEP 2111.01 “Plain Meaning” and MPEP 2173.01.
27. The rejection was issued under 103 because it is uncertain whether each figure of the prior art is an embodiment or several figures could constitute a single embodiment.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claim(s) 1-5, 7-9, 11-12, 18 and 20 are/is rejected under 35 U.S.C. 103 as being unpatentable over Shao et al. (Pub. No.: US 2013/0027075 hereinafter mentioned as “Shao”).
As per claim 1, Shao discloses:
A test device (See MPEP 2111.02, Effect of Preamble, and II. Preamble Statements Reciting Purpose or Intended Use), comprising:
a control circuit (Figs. 2 and 7, see the control circuit 140. Also see [0039] and [0018]); and
M groups of pads (Figs. 2 and 8, see the testing-pads 110. Also see [0039] and [0018]) and N groups of test units (Figs. 2 and 8, see the testing-units 120. Also see [0039] and [0018]) connected to the control circuit (Fig. 7, see the testing-pads 110 and testing-units 120 connected to the control circuit 140. Also see [0039] and [0020]),
wherein M and N are both integers greater than 1 (Fig. 8, see the testing-pads 110 and testing-units 120 being greater than 1. Also see [0039] and [0018]),
a number of test units in each of the N groups of test units is less than or equal to M (Fig. 7, see subset of the testing-units 120A and 120B being less than the 8-testing-pads of testing-pads 110. Also see [0039] and [0019]), and a total number of the test units among the N groups of test units is greater than M (Fig. 8, see the total number of testing-units 120 being greater than testing-pads 110. Also see [0039] and [0018]),
wherein the control circuit (Figs. 2 and 7, see the control circuit 140. Also see [0039] and [0018]) is configured to receive a test signal (see [0021]),
select one of the N groups of test units (Figs. 2 and 7, see the switching circuit 130 and the control circuit 140. Also see claim-1 and/or [0019]-[0020]) based on the test signal (see [0021]), and
connect at least some of the M groups of pads to the test units in the selected group of test units in one-to-one correspondence (see claim-1 and/or [0020]).
As per claim 2, Shao discloses the test device of claim 1 as described above.
Shao further discloses:
wherein at least one group of pads among the M groups of pads (Figs. 2 and 8, see the testing-pads 110. Also see [0039] and [0018]) is connected with multiple test units in different groups of test units among the N groups of test units (Figs. 2 and 8, see the testing-units 120 testing-pads 110. Also see [0041], [0032], [0039] and [0018]).
As per claim 3, Shao discloses the test device of claim 2 as described above.
Shao further discloses:
wherein a same one of the test units among the N groups of test units (Figs. 2 and 8, see the testing-units 120 testing-pads 110. Also see [0041], [0032], [0039] and [0018]) is connected with at most one group of pads among the M groups of pads (Figs. 2 and 8, see the testing-pads 110. Also see [0039] and [0018]).
As per claim 4, Shao discloses the test device of claim 2 as described above.
Shao further discloses:
wherein the control circuit (Figs. 6, see the control circuit 140. Also see [0029]-[0033]) comprises a first control sub-circuit (Figs. 6, see the flip-flop devices 301-304. Also see [0032]) and a second control sub-circuit (Figs. 6, see the switching devices 200A-200D. Also see [0032]), and the second control sub-circuit is connected with the first control sub-circuit, the M groups of pads and the N groups of test units (see [0032]-[0033]);
the first control sub-circuit (Figs. 6, see the flip-flop devices 301-304. Also see [0032]) is configured to generate a selection signal (see [0035], [0019] and [0021]. The logical high-control-signal based on the test-signal) based on the test signal (see [0021]), and the selection signal is configured to indicate to select the one of the N groups of test units (see [0035] and [0019]. The high-control-signal that activates and indicates the activation of testing-unit 120A from the plurality of testing units 120); and
the second control sub-circuit (Fig. 6, see the switching devices 200A-200D. Also see [0032]) is configured to: receive the selection signal, and enable a connection between the test units in the selected group of test units and at least some of the M groups of pads according to the selection signal (see [0035] and [0019]. The switching device 200A receives the logical high-control-signal to enable the testing-unit 120A from the plurality of testing units 120).
As per claim 5, Shao discloses the test device of claim 4 as described above.
Shao further discloses:
the first control sub-circuit at least comprises a decoder (Fig. 6, see the flip-flop devices 301-304 and its implicit decoder to decode the digital signals from the flip-flops that are digital circuits. Also see [0016], [0032] and [0038]), wherein the decoder has N output terminals and is configured to receive the test signal and output an N-bit selection signal to the second control sub-circuit through the N output terminals (see [0035] and [0019]. The output of the decoder to the switching device 200A receives the logical high-control-signal to enable the testing-unit 120A from the plurality of testing units 120).
As per claim 7, Shao discloses the test device of claim 5 as described above.
Shao further discloses:
the second control sub-circuit (Fig. 6, see the switching devices 200A-200D. Also see [0032]) comprises N groups of transistors (Fig. 4, see the transistors of switching devices 200A-200C. Also see [0032]), and the N groups of transistors are connected with the N groups of test units in one-to-one correspondence (Fig. 5, see the switching devices 200 . Also see [0026]); and
a first controlled terminal of a transistor in each group of transistors among the N groups of transistors is connected with one group of pads among the M groups of pads (Fig. 6, see the switching devices 200A-200D that includes the transistors. Also see [0032]), a second controlled terminal of the transistor is connected with the test unit (Fig. 6, see the testing-pads 110 connected to the switching devices 200A-200D that includes the transistors. Also see [0032]) correspondingly connected with the group of pads (Figs. 2 and 8, see the testing-pads 110. Also see [0039] and [0018]), and a control terminal of the transistor is configured to receive one bit of the N-bit selection signal (see [0035] and [0019]. The output of the decoder to the switching device 200A receives the logical high-control-signal and/or the logical low to enable the testing-unit 120A from the plurality of testing units 120).
As per claim 8, Shao discloses the test device of claim 1 as described above.
Shao further discloses:
wherein a number of terminals to be led out from each of the test units among the N groups of test units is one or more; and a number of pads in each group of pads among the M groups of pads is the same as the number of the terminals to be led out from each of the test units (see [0015]).
As per claim 9, Shao discloses the test device of claim 1 as described above.
Shao further discloses:
wherein the test units in the N groups of test units comprise word lines or bit lines (see [0034]-[0036], [0016] and [0029]. The bit lines used for logical-high 1 and logical-low 0).
As per claim 11, Shao discloses the test device of claim 9 as described above.
Shao further discloses:
wherein word lines or bit lines (see [0034]-[ 0036], [0016] and [0029]. The bit lines used for logical-high 1 and logical-low 0) in each group of test units among the N groups of test units are spaced apart (Fig. 8, see the testing-units 120 being spaced apart, therefore, the bit lines are spaced apart. Also see [0039] and [0018]).
As per claim 12, Shao discloses the test device of claim 9 as described above.
Shao further discloses:
wherein at least two of a plurality of word lines (see [0016]. The multiplexer has at least 2 bit lines) or bit lines in each group of test units among the N groups of test units are adjacent such that no other word lines or bit lines are present therebetween (Fig. 1B, see the bit lines of testing-units 80. Also see [0034]-[ 0036], [0016] and [0029]. The bit lines used for logical-high 1 and logical-low 0).
Furthermore, pursuant to MPEP 2144.04 Legal Precedent as Source of Supporting Rationale, VI. REVERSAL, DUPLICATION, OR REARRANGEMENT OF PARTS, the Rearranging/shifting the position of the lines with respect to each other and/or other components does not modify the operation of the sensor in a novel manner, therefore, components’ positions and/or rearrangement has no patentable weight (see “In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950)). Additionally, rearranging the component positions is an obvious design choice (see “In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975)). Furthermore, if the aforesaid arrangements modify the apparatus in an unpredictable manner, it should be added language claiming the aforesaid unpredictable manner in order to add patentability weight to the claim.
As per claim 18, Shao discloses:
A test method (See MPEP 2111.02, Effect of Preamble, and II. Preamble Statements Reciting Purpose or Intended Use), comprising:
receiving a test signal (see [0021]); and
selecting one of N groups of test units (Figs. 2 and 7, see the switching circuit 130 and the control circuit 140. Also see claim-1 and/or [0019]-[0020]) based on the test signal (see [0021]); and
connecting at least some of M groups of pads to the test units in the selected group of test units in one-to-one correspondence (see claim-1 and/or [0020]),
wherein M and N are both integers greater than 1 (Fig. 8, see the testing-pads 110 and testing-units 120 being greater than 1. Also see [0039] and [0018]), a number of the test units in each of the N groups of test units is less than or equal to M (Fig. 7, see subset of the testing-units 120A and 120B being less than the 8-testing-pads of testing-pads 110. Also see [0039] and [0019]), and a total number of the test units among the N groups of test units is greater than M (Fig. 8, see the total number of testing-units 120 being greater than testing-pads 110. Also see [0039] and [0018]).
As per claim 20, Shao discloses the test method of claim 18 as described above.
Shao further discloses:
generating a selection signal (see [0035], [0019] and [0021]. The logical high-control-signal based on the test-signal) based on the test signal (see [0021]), wherein the selection signal is configured to indicate to select one of the N groups of test units (see [0035] and [0019]. The high-control-signal that activates and indicates the activation of testing-unit 120A from the plurality of testing units 120); and
receiving the selection signal, and enabling a connection between the test units in the selected group of test units and at least some of the groups of pads among the M groups of pads according to the selection signal (see [0035] and [0019]. The switching device 200A receives the logical high-control-signal to enable the testing-unit 120A from the plurality of testing units 120).
6. Claim(s) 19 are/is rejected under 35 U.S.C. 103 as being unpatentable over Shao in view of Chang et al. (Pub. No.: US 2022/0367299 hereinafter mentioned as “Chang”).
As per claim 19, Shao discloses the test method of claim 18 as described above.
Shao discloses testing the test units in the selected group of test units via at least some of the groups of test pads among the M groups of pads as described above but does not explicitly disclose that it is done by using a test probe.
However, Chang further discloses:
testing the test units in the selected group of test units via at least some of the groups of test pads among the M groups of pads by using a test probe (see [0056] and [0017]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the feature relative to testing the test units in the selected group of test units via at least some of the groups of test pads among the M groups of pads of Shao by using a “test probe”, as disclosed by Chang, with the motivation and expected benefit related to improving the system, methods and measurements by simultaneously testing two testing units (Chang, Paragraph [0056]), thus, testing a desirable sufficient number of test units to effectively and efficiently monitor degradations (Chang, Paragraph [0017]).
Furthermore, Shao states that “Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes ...” (Shao, Paragraph [0052]).
Furthermore, Chang states that “Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes ...” (Chang, Paragraph [0105]).
Allowable Subject Matter
7. Claim(s) 6 and 10 are/is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
8. The following is an examiner's statement of reasons for the objection:
9. Regarding claim 6, the prior art of record, alone or in combination, does not disclose or suggest the below underlined limitations incorporated together with the other claimed limitations not mentioned herein:
wherein the first control sub-circuit comprises one decoder and N comparators; and
an output terminal of the decoder is connected with input terminals of the N comparators, and output terminals of the N comparators are in one-to-one correspondence with the N groups of test units;
the decoder is configured to receive the test signal and output a decoded signal to the input terminals of the N comparators; each of the N comparators is configured to receive a reference signal and the decoded signal and output a 1-bit selection sub-signal, and N 1-bit selection sub-signals output by the N comparators constitute an N-bit selection signal; and each group of test units among the N groups of test units corresponds to a unique reference signal.
10. Regarding claim 10, the prior art of record, alone or in combination, does not disclose or suggest the below underlined limitations incorporated together with the other claimed limitations not mentioned herein:
wherein the N is equal to 2, the M is equal to 4, and a number of the word lines in each group of test units among the N groups of test units is equal to 4; and
a second control sub-circuit of the control circuit comprises 2 groups of transistors that are in one-to-one correspondence with 2 groups of test units among the N groups of test units, and a number of transistors in each of the groups of transistors is equal to 4; and
each group of pads among the M groups of pads is connected with 2 test units in different groups of test units among the N groups of test units.
11. The prior art of record does not anticipate the limitations of the independent claims.
Furthermore, there is not any obvious motivation for an ordinary skilled in the art to combine some and/or all of the features of the prior art of record to achieve the features of the allowable subject matter. In addition, it will further require substantial structural modification of the components that will also require substantial modification of the measurements, signal processing and configurations to achieve the features of the allowable subject matter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVARO E. FORTICH whose telephone number is (571) 272-0944. The examiner can normally be reached on Monday thru Friday from 8:30am to 5:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Huy Phan, can be reached on (571)272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALVARO E FORTICH/Primary Examiner, Art Unit 2858
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