Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over by US 2018/0365102 A1 to Li et al (herein referred to as Li) in view of US 2012/0192039 A1 to Hannuksela et al (herein Hannuksela).
Referring to claims 1 and 11, Li discloses a method and corresponding memory system for calculating checksums on scrambled data read from a storage of the memory system, comprising: reading the scrambled data from the storage inside a storage device (storage device is depicted as SSD 176 in Figure 1B) of the memory system (Figure 1, server 156 is the “memory system”; Figure 2A, read from NAND storage from interface 220 via communication 211, see also paragraphs [0054-0057], controller 178 is inside storage device 176); inside the storage device of the memory system, the storage device including the storage from which the scrambled data is read, descrambling the scrambled data read from the storage without transferring the scrambled data across a memory interface to outside the storage device (Figure 2A, descrambler 240 & All of Figure 2A is “inside” storage device 176, therefore, no memory interface to “outside” the storage device 176 is crossed); and inside the storage device of the memory system, performing checksum calculations on the descrambled data (Figure 2A, Erasure code decoder 234 & CRC 232). Li does not explicitly disclose “determining whether to externally transfer the descrambled data from the storage device based on a raw bit error in the descrambled data, wherein the checksum calculations provide an estimate for the raw bit error”. However, Li does disclose wherein the checksum calculations provide an estimate for a raw bit error in the descrambled data (Figure 2A, Erasure code decoder 234 & CRC 232 estimate the occurrence of raw bit errors by design, see also paragraph [0057]). In addition, determining whether or not to perform an action such as transferring data based on an error rate is notoriously well-known in the data processing/communication arts. In an analogous art, Hannuksela discloses this well-known teaching by describing a data transmission system where if an error rate threshold exceeds a threshold, data transmission is either halted or stopped altogether (see paragraph [0048]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Li with the teachings of Hannuksela in order to not transfer descrambled data if the checksum calculations indicate a high frequency of errors. Doing so would ensure that erroneous data is not transferred.
Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Li in view Hannuksela in further view of Official Notice.
Referring to claims 3 and 13, Li in view of Hannuksela substantially discloses the invention as applied to claims 1 and 11 but does not explicitly disclose wherein the performing checksum calculations comprise using submatrices of an LDPC matrix to calculate the checksums. Li does disclose erasure decoder 234. Official Notice is taken that it would be well known in the art to modify Li with LDPC decoding capabilities as the erasure decoder 234 in order to calculate checksums as part of LDPC decoding. Doing so would be well within the technical grasp of one of ordinary skill in the art given the benefits LDPC decoding provides such as achieving high performance at low computational costs.
Claims 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Li in view Hannuksela in further view of US 2023/0195561 A1 to Bhatia (herein referred to as Bhatia).
Referring to claims 9 and 19, Li in view of Hannuksela substantially discloses the invention as applied to claims 1 and 11 but does not explicitly disclose wherein the descrambling the read data comprises: generating a descrambling sequence during a time period when the scrambled data is read from the storage of the memory system; and descrambling the scrambled data using the descrambling sequence. Li does disclose descrambling which would require a descrambling sequence to perform. In an analogous art, Bhatia discloses the use of a scrambling sequence value (see Figure 2, element 290 & paragraph [0038]) for descrambling scrambled data. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the descrambling sequence value teachings of Bhatia within Li in order to ensure that scrambled data is timely and accurately descrambled.
Allowable Subject Matter
Claims 4-8, 10, 14-18, and 20 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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Justin R. Knapp
Primary Examiner
Art Unit 2112
/JUSTIN R KNAPP/Primary Examiner, Art Unit 2112
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