Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, line 5 recites the term “finger-shaped sub-blocks.” This term is unclear and not well known in the art. While Applicant is allowed to be their own lexicographer, any new terms must be clearly defined in the specification. See MPEP 2173.05. Figure 2 has labeled two rectangles “Finger-shaped sub-blocks in vertical direction,” and is further described in para. 38 in the specification this is further defined as “In the embodiments, the data of a finger-shaped structure on different wordline layers and corresponding to the same bit line is referred to as a sub-block which is called as a finger-shaped sub-block that can be used to store the data size of a finger-shaped structure block data.” However, it is still unclear what is meant by finger-shaped or what allows the rectangles outlined in fig. 2 to be described as finger-shaped.
Claim 1, lines 10-11 recite the limitation “a finger-dimensional error correction code operation” and line 12 recites the limitation “a finger-dimensional check code data.” These terms are unclear because “finger-dimensional” is not clear. From fig. 2, the finger-shaped sub-blocks in a vertical direction are outlined. It is unclear if “finger-dimensional” refers to blocks in a vertical direction, or how the vertical direction relates to a finger dimension.
Claims 10 and 12 correspond to claim 1, and are rejected accordingly. Dependent claims 2-9, 11, and 13-20 inherit the deficiencies of the parent claims and do not remedy the issue, therefore they are also rejected under 112B.
Claim 5, lines 6-11 recites: “and, another portion of the wordline-dimensional check code data stored by a last page corresponding to an odd-number finger-shaped sub-block in the last one even-number super wordline is used to correct an error occurring in the data of another finger-shaped sub-block, having an odd number identical to a number of the odd-number finger-shaped sub-block, in a plurality of odd-number super wordlines within the super block.” Examiner believes this to be a typo, as it is inconsistent with the disclosed invention. The rest of claim 5 and 6 and para. 42 and 58 of the specification implies that wordline-dimensional check code data stored in a last even wordline is used to correct data in a plurality of even wordlines, not in a plurality of odd wordlines, as written in the claim. Claim 5 is interpreted in accordance with the rest of the disclosure in this action. Claim 16 corresponds to claim 5, and is rejected for the same reasons.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 2, 10, 12, and 13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 2 of U.S. Patent No. 12487749. Although the claims at issue are not identical, they are not patentably distinct from each other as described below.
Claim 1 recites limitations found in claim 1 of patent 12487749.
Claim 2 recites limitations found in claim 2 of patent 12487749.
Claims 10 and 12 correspond to claim 1 and are rejected accordingly.
Claim 13 corresponds to claim 2 and is rejected accordingly.
Claims 1-3, 10, and 12-14 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 of copending Application No. 18/809302 (reference application, herein after Yang1) in view of claim 1 of 12487749 (herein after Yang2). This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Regarding claim 1 of the instant application, claim 1 of Yang1 teaches all elements except: “a specific buffer, for receiving and buffer a specific data sent from the host device.” Claim 1 of Yang2 recites “a specific buffer, for receiving and buffering specific data from the host device.”
It would be obvious to one of ordinary skill in the art, to combine the teachings of Yang1 and Yang2 to incorporate a buffer for receiving and buffering specific data sent from the host device (Yang2) into the system for performing dimensional error correction (Yang1), to allow for benefits such as: reduced circuit cost (Yang2, para 55).
Regarding claim 2 of the instant application, the combination of Yang1 and Yang2 teaches the flash memory controller of claim 1. Claim 2 of Yang1 further teaches Claim 2 of the instant application.
Regarding claim 3 of the instant application, the combination of Yang1 and Yang2 teaches the flash memory controller of claim 1. Claim 3 of Yang1 further teaches claim 3 of the instant application.
Claims 10 and 12 correspond to claim 1, and are rejected accordingly.
Claim 13 corresponds to claim 2, and is rejected accordingly.
Claim 14 corresponds to claim 3, and is rejected accordingly.
Claims 4 and 15 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 of copending Application No. 18/809302 (reference application, herein after Yang1) in view of claim 1 of 12487749 (herein after Yang2) and 2019/0095116 (herein after Igahara). This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Regarding claim 4 of the instant application, the combination of Yang1 and Yang2 teaches the flash memory controller of claim 3. In the analogous art of memory operations Igahara teaches:
wherein a data page of the super block comprises a size of a single data page in a single-level-cell writing mode; the data page of the super block comprises a size of two sub-data pages in a multi-level-cell writing mode; the data page of the super block comprises a size of three sub-data pages in a triple-level-cell writing mode; and, the data page of the super block comprises a size of four sub-data pages in a quad-level-cell writing mode. (see para. 78: NAND flash memory 5 may execute a write operation in an SLC mode in which one bit is written per memory cell, an MLC mode in which two bits are written to per memory cell, a TLC mode in which three bits are written to per memory cell, or a QLC mode in which four bits are written to per memory cell.)
It would be obvious to one of ordinary skill in the art, to combine the teachings of Yang1 and Yang2 with Igahara to incorporate treating memory cells (pages) as different sizes depending on a write operation mode (Igahara) into the system for performing dimensional error correction (Yang1), to allow for benefits such as: dynamic flexibility and high performance (Igahara, para. 105).
Claim 15 corresponds to claim 4, and is rejected accordingly.
Claims 5-11 and 16-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 3 and 4 of copending Application No. 18/809302 (reference application, herein after Yang1) in view of claim 1 of 12487749 (herein after Yang2) and 6606718 (herein after Bessios). This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Regarding claim 5, the combination of Yang1 and Yang2 teaches the flash memory controller of claim 3. Yang1 further teaches:
wherein a portion of the wordline-dimensional check code data stored by a last data page corresponding to an even-number finger-shaped sub-block in the last one even-number super wordline is used to correct an error occurring in data of a finger-shaped sub-block, having an even number… in a plurality of even-number super wordlines within the super block; and, another portion of the wordline-dimensional check code data stored by a last data page corresponding to an odd-number finger-shaped sub-block in the last one even-number super wordline is used to correct an error occurring in data of another finger-shaped sub-block, having an odd number…, in a plurality of odd-number super wordlines within the super block. (claim 3: wherein the error correction code circuit is used to correct an error occurring in data of M finger-shaped sub-blocks respectively included in a plurality of even-number wordlines of the super block respectively according to a wordline-dimensional check code data stored in M last data pages corresponding to M finger-shaped sub-blocks in a last one even-number wordline of the super block, and is used to correct an error occurring in data of M finger-shaped sub-blocks respectively included in a plurality of odd-number wordlines of the super block respectively according to another wordline-dimensional check code data stored in M last data pages corresponding to M finger-shaped sub-blocks in a last one odd-number wordline of the super block; M is an even integer.)
However, Yang1 does not explicitly disclose that:
[the wordline-dimensional check code is part of the same sub-block that it corrects]
In the analogous art of memory operations, Bessios teaches:
[the wordline-dimensional check code is part of the same sub-block (column) that it corrects] (see fig. 2 and col. 6, lines 34-40: the information matrix 200 includes both the encoded data 2101 arranged as a square information matrix, and row and column parity check values 202 and 203, respectively.) It is well understood in the art that column parity check values are calculated via XOR and are used to correct errors in their associated column. Further, column/row parities are the 2D version of the wordline-dimensional and finger-dimensional check codes of the instant application and the subject matter disclosed by Yang1.
It would be obvious to one of ordinary skill in the art, to combine the teachings of Yang1 and Yang2 with Bessios to use the wordline-dimensional check codes to correct errors in the pages of the same sub-block the check code is stored in (taught by Bessios) that are in even wordlines if the wordline storing the check code is even or that are in odd wordlines if the wordline storing the check code is odd (taught by Yang1), to allow for benefits such as: high coding gain and simplicity of structure (Bessios, para. 105).
Regarding claim 6, the combination of Yang1 and Yang2 teaches the flash memory controller of claim 3. Yang1 further teaches:
wherein a portion of the wordline-dimensional check code data stored by a last data page corresponding to an even-number finger-shaped sub-block in the last one odd-number super wordline is used to correct an error occurring in data of a finger-shaped sub-block, having an even number identical to a number of the even-number finger-shaped sub-block, in a plurality of odd-number super wordlines within the super block; and, another portion of the wordline-dimensional check code data stored by a last data page corresponding to an odd-number finger-shaped sub-block in the last one odd-number super wordline is used to correct an error occurring in data of another finger-shaped sub-block, having an odd number identical to a number of the odd-number finger-shaped sub-block, in a plurality of odd-number super wordlines within the super block. (claim 3: wherein the error correction code circuit is used to correct an error occurring in data of M finger-shaped sub-blocks respectively included in a plurality of even-number wordlines of the super block respectively according to a wordline-dimensional check code data stored in M last data pages corresponding to M finger-shaped sub-blocks in a last one even-number wordline of the super block, and is used to correct an error occurring in data of M finger-shaped sub-blocks respectively included in a plurality of odd-number wordlines of the super block respectively according to another wordline-dimensional check code data stored in M last data pages corresponding to M finger-shaped sub-blocks in a last one odd-number wordline of the super block; M is an even integer.)
However, Yang1 does not explicitly disclose that:
[the wordline-dimensional check code is part of the same sub-block that it corrects]
In the analogous art of memory operations, Bessios teaches:
[the wordline-dimensional check code is part of the same sub-block (column) that it corrects] (see fig. 2 and col. 6, lines 34-40: the information matrix 200 includes both the encoded data 2101 arranged as a square information matrix, and row and column parity check values 202 and 203, respectively.) It is well understood in the art that column parity check values are calculated via XOR and are used to correct errors in their associated column. Further, column/row parities are the 2D version of the wordline-dimensional and finger-dimensional check codes of the instant application and the subject matter disclosed by Yang1.
It would be obvious to one of ordinary skill in the art, to combine the teachings of Yang1 and Yang2 with Bessios to use the wordline-dimensional check codes to correct errors in the pages of the same sub-block the check code is stored in (taught by Bessios) that are in even wordlines if the wordline storing the check code is even or that are in odd wordlines if the wordline storing the check code is odd (taught by Yang1), to allow for benefits such as: high coding gain and simplicity of structure (Bessios, para. 105).
Regarding claim 7, the combination of Yang1 and Yang2 teaches the flash memory controller of claim 1. Yang1 further teaches:
wherein the flash memory controller writes and stores different portions of the finger-dimensional check code data respectively into a last one data page of a last one even-number finger-shaped sub-block and a last one data page of a last one odd-number finger-shaped sub-block… (see claim 4: the error correction code circuit is used to correct an error occurring in data of a plurality of even-number finger-shaped sub-blocks of the first wordline according to a portion of finger-dimensional check code data stored by a last one data page of a last one even-number finger-shaped sub-block in the first wordline of the super block, and is used to correct an error occurring data of a plurality of odd-number finger-shaped sub-blocks in the first wordline according to another portion of finger-dimensional check code data stored by a last one data page of a last one odd-number finger-shaped sub-block in the first wordline of the super block.)
However, Yang1 does not teach wherein:
[there is a finger-dimensional check code]… respectively included by each of a plurality of super wordlines within the super block.
Bessios teaches:
[there is a finger-dimensional (row) check code]… respectively included by each of a plurality of super wordlines within the super block. (see fig. 2 and col. 6, lines 34-40: the information matrix 200 includes both the encoded data 2101 arranged as a square information matrix, and row and column parity check values 202 and 203, respectively.) It is well understood in the art that row parity check values are calculated via XOR and are used to correct errors in their associated row. Further, column/row parities are the 2D version of the wordline-dimensional and finger-dimensional check codes of the instant application and the subject matter disclosed by Yang1.
It would be obvious to one of ordinary skill in the art, to combine the teachings of Yang1 and Yang2 with Bessios to include the finger-dimensional check codes at the end of each wordline or row (taught by Bessios) into the system for dimensional error correction (taught by Yang1), to allow for benefits such as: high coding gain and simplicity of structure (Bessios, para. 105).
Regarding claim 8, the combination of Yang1, Yang2, and Bessios teaches the flash memory controller of claim 7. Yang 1 further teaches:
wherein a portion of the finger-dimensional check code data stored by the last one data page of the last one even-number finger-shaped sub-block in a specific super wordline within the super block is used to correct an error occurring in data of a plurality of even-number finger-shaped sub-blocks in the specific super wordline; and, another portion of the finger-dimensional check code data stored by the last one data page of the last one odd-number finger-shaped sub-block in the specific super wordline within the super block is used to correct an error occurring in data of a plurality of odd-number finger-shaped sub-blocks in the specific super wordline. (see claim 4: the error correction code circuit is used to correct an error occurring in data of a plurality of even-number finger-shaped sub-blocks of the first wordline according to a portion of finger-dimensional check code data stored by a last one data page of a last one even-number finger-shaped sub-block in the first wordline of the super block, and is used to correct an error occurring data of a plurality of odd-number finger-shaped sub-blocks in the first wordline according to another portion of finger-dimensional check code data stored by a last one data page of a last one odd-number finger-shaped sub-block in the first wordline of the super block.)
Regarding claim 9, the combination of Yang1, Yang2, and Bessios teaches the flash memory controller of claim 7. Yang1 further teaches:
wherein M last data pages corresponding to M finger-shaped sub-blocks in the last one even-number super wordline and another M last data pages corresponding to another M finger-shaped sub-blocks in the last one odd-number super wordline within the super block are used to store the wordline-dimensional check code data; (claim 3: the error correction code circuit is used to correct an error occurring in data of M finger-shaped sub-blocks respectively included in a plurality of even-number wordlines of the super block respectively according to a wordline-dimensional check code data stored in M last data pages corresponding to M finger-shaped sub-blocks in a last one even-number wordline of the super block, and is used to correct an error occurring in data of M finger-shaped sub-blocks respectively included in a plurality of odd-number wordlines of the super block respectively according to another wordline-dimensional check code data stored in M last data pages corresponding to M finger-shaped sub-blocks in a last one odd-number wordline of the super block; M is an even integer.)
two… last data pages respectively included by the last one even-number finger-shaped sub-block and the last one odd-number finger-shaped sub-block in… one even-number super wordline are used to store a portion of finger-shaped sub-block check code data to respectively correct an error occurring in data of a plurality of even-number finger-shaped sub-blocks and an error occurring in data of a plurality of odd-number finger-shaped sub-blocks in the… one even-number super wordline; and, two… last data pages respectively included by the last one even-number finger-shaped sub-block and the last one odd-number finger-shaped sub-block in… one odd-number super wordline are used to store another portion of finger-shaped sub-block check code data to respectively correct an error occurring in data of a plurality of even-number finger-shaped sub-blocks and an error occurring in data of a plurality of odd-number finger-shaped sub-blocks in the… one odd-number super wordline. (see claim 4: wherein the error correction code circuit is used to correct an error occurring in data of a plurality of even-number finger-shaped sub-blocks of the first wordline according to a portion of finger-dimensional check code data stored by a last one data page of a last one even-number finger-shaped sub-block in the first wordline of the super block, and is used to correct an error occurring data of a plurality of odd-number finger-shaped sub-blocks in the first wordline according to another portion of finger-dimensional check code data stored by a last one data page of a last one odd-number finger-shaped sub-block in the first wordline of the super block).
However, Yang1 does not explicitly disclose:
[all wordlines contain finger-shaped sub-block check codes]
[finger-shaped sub-block check codes in the last even and odd wordlines are stored in] second last data pages.
Bessios teaches:
[all wordlines contain finger-shaped sub-block check codes]
[finger-shaped sub-block check codes in the last even and odd wordlines are stored in] second last data pages.
(see fig. 2 and col. 6, lines 34-40: the information matrix 200 includes both the encoded data 2101 arranged as a square information matrix, and row and column parity check values 202 and 203, respectively. An additional parity bit (shown as value y100 in fig. 2) may be used as a parity check bit for the column check bits.) It is well understood in the art that row parity check values are calculated via XOR and are used to correct errors in their associated row. Further, column/row parities are the 2D version of the wordline-dimensional and finger-dimensional check codes of the instant application and the subject matter disclosed by Yang1. However, one of ordinary skill in the art would obviously realize that the last page of the last even and odd sub-blocks in the last even and odd wordlines of Yang1 would be already populated with the wordline-dimensional check codes. Therefore, one of ordinary skill in the art, motivated to store a finger-dimensional check code in the (already populated) last pages of the last even and odd sub-blocks in the last even and odd wordlines, would find it obvious to instead store the finger-dimensional check codes in the second last pages.
It would be obvious to one of ordinary skill in the art, to combine the teachings of Yang1 and Yang2 with Bessios to include the finger-dimensional check codes at the last available page of the last wordline (taught by Bessios) into the system for dimensional error correction (taught by Yang1), to allow for benefits such as: high coding gain and simplicity of structure (Bessios, para. 105).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK K BARNETT whose telephone number is (571)270-0431. The examiner can normally be reached M-Th 8-5, F 8-4 EST.
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/JACK KENSINGTON BARNETT/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111