Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pgs. 10-12, filed 04/15/2026, with respect to the 112B and double patenting rejections have been fully considered and are persuasive. The 112B and double patenting rejections of claims 1-20 have been withdrawn in view of clarifying amendments and filed terminal disclaimers.
However, in view of the clarifying amendments new grounds of rejection are made, as will be described in the 103 rejection portion of this office action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 5-14, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US Publication No. 2017/0315868) in view of Kim (“Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding”).
Regarding claim 1, Yang teaches:
A flash memory controller, to be coupled between a host device and a flash memory module, comprising:
a specific buffer, for receiving and buffer a specific data sent from the host device, the specific data to be stored into the flash memory module to form a super block, and the super block being composed of a plurality of vertical sub-blocks in a vertical direction and a plurality of super wordlines in a horizontal direction; (see para. 22: In practice the flash memory controller 110… can perform a variety of control operations by using its internal circuit elements. For instance the controller 110 can use the control logic 114 to control the access of flash memory module 120… use the buffer memory 116 to buffer data, and use the interface logic 118 to communicate with a host device… and see para. 7: the flash memory controller is arranged for accessing the flash memory module, wherein when receiving a write request from a host device to write data into the flash memory module, the flash memory controller encodes the data to generate at least one parity check code, wherein the data is to be written into a first super block of the flash memory chips. Also see para. 27: the word lines disposed/positioned on the same plane is configured as or classified into a word line set. Refer back to fig. 2. Word lines WL0-WL3 are classified into a first word-line set, and word lines WL4-WL7 are classified into a second word line set; and other so on.) Each word line set (corresponding to the word line groups WL_G0-WL_G47 in fig. 6) is considered to be a super wordline. Also note in fig. 2, word lines may be grouped in a vertical direction as well, forming what is considered to be a vertical sub-block. For example, WL0, WL4, and continuing down would be a first vertical sub-block and WL1, WL5, and continuing down would be a second vertical sub-block. Further see that this grouping of wordlines corresponds to fig. 6, such that the first wordline from each super wordline (wordline group/set) comprises a vertical sub-block, the second wordline from each super wordline (wordline group/set) comprises a second vertical sub-block, and so on. Further, while it is not explicitly disclosed that the data received from the host is buffered in interface logic 118 or buffer 116, it is considered implicitly disclosed, or at the very least would be considered an obvious modification to Yang’s system by one of ordinary skill, because buffering received data before storing it is routine and very well-known in the art.
and an error correction code circuit, coupled to the specific buffer, for performing a wordline-dimensional error correction code operation upon the specific data to generate a wordline-dimensional check code data… wherein when a data error occurs in the super block, the wordline-dimensional check code data… [is] used to correct the data error occurring in the super block to obtain the specific data. (see fig. 7: SF0-SF7 is considered to be wordline-dimensional check code data. And see para. 46: Final parity check codes SF0-SF7 can be used to correct errors if data errors occur. For instance, if one word line in the word line set WL_G0 is open… the flash memory controller 110 can re-generate the parity check codes S8, S16, …, S184 and final parity check code SF0 by reading data from other word line sets so as to re-generate the parity check code S0, and then can use the parity check code S0 and data content read from the data pages P0 of flash memory chips 512, 522, and 524 to generate data of the data page P0 of flash memory chip 514.)
However, Yang does not explicitly teach:
[calculating and storing error correcting bits with respect to a horizontal AND a vertical dimension]
In the analogous art of error correcting codes, Kim teaches:
[calculating and storing error correcting bits with respect to a horizontal AND a vertical dimension] (see pg. 200, RHC, section 3: We propose applying two-dimensional (2D) error coding techniques [47, 52] to the on-die embedded memory system to enable fast common-case error-free operation while still maintaining high error coverage with low VLSI overheads. The key innovation in 2D error coding is the combination of light-weight horizontal per-word error coding with vertical column-wise error coding. The horizontal and vertical coding can either be error detection codes (EDC) or error correcting codes (ECC). The types of codes used in the horizontal and vertical directions allow us to trade-off the error coverage against the VLSI overheads to tailor the design to the types and frequency of errors expected.)
It would have been obvious to one of ordinary skill in the art, having the teachings of Yang and Kim before them, before the effective filing date of the claimed invention to perform error coding with respect to a horizontal AND a vertical direction (Kim) into the flash memory storage method (Yang) such that additional final parity check codes are calculated with respect to vertical groupings of word lines (constituting a vertical-dimensional check code), that could be used additional error detection/correction in the super block to obtain the original data, to allow for benefits such as higher multi-bit error coverage (Kim, pg. 202, LHC).
Regarding claim 2, the combination of Yang and Kim teaches the controller of claim 1. Yang further teaches:
wherein the wordline-dimensional error correction code operation… [is] implemented by an exclusive-OR operation. (see fig. 7, which describes generating wordline-dimensional error correction codes via XOR. As you can see, there are two final parity check codes for each vertical group, one corresponding to even wordline groups, and one corresponding to odd wordline groups. For example, SF0 is calculated from parities from odd wl groups (WL_G0 (first group), WL_G2 (third group)… etc) in the first vertical group. See that S0, S8, S16,… , S184 are the parities generated from the first WL (vertical group) in each odd WL group. Similarly, SF1 is generated from parities corresponding to the second WL in each odd WL group. Also see SF4 is generated from parities corresponding to the first WL in each even WL group (WL_G1 (second group), WL_G3 (fourth group…)
Kim teaches: [calculating and storing error correcting bits with respect to a horizontal AND a vertical dimension] (see pg. 200, RHC, section 3: We propose applying two-dimensional (2D) error coding techniques [47, 52] to the on-die embedded memory system to enable fast common-case error-free operation while still maintaining high error coverage with low VLSI overheads. The key innovation in 2D error coding is the combination of light-weight horizontal per-word error coding with vertical column-wise error coding. The horizontal and vertical coding can either be error detection codes (EDC) or error correcting codes (ECC). The types of codes used in the horizontal and vertical directions allow us to trade-off the error coverage against the VLSI overheads to tailor the design to the types and frequency of errors expected.)
It would have been obvious to one of ordinary skill in the art, having the teachings of Yang and Kim before them, before the effective filing date of the claimed invention to perform error coding with respect to a horizontal AND a vertical direction (Kim) into the flash memory storage method (Yang) such that additional final parity check codes are calculated with respect to vertical groupings of word lines (constituting a vertical-dimensional check code), that could be used additional error detection/correction in the super block to obtain the original data, to allow for benefits such as higher multi-bit error coverage (Kim, pg. 202, LHC). To implement the error coding in Yang with respect to the vertical direction (as taught by Kim), one of ordinary skill in the art would find it obvious to perform the final parity generation of Yang, with respect to the vertical direction instead of the horizontal, further using XOR to calculate both, as described in fig. 7.
Regarding claim 3, Yang and Kim teaches the controller of claim 1. Yang further teaches:
wherein the flash memory controller writes and stores the wordline-dimensional check code data into M last data pages corresponding to M vertical sub-blocks in a last one even-number super word line within the super block and into another M last data pages corresponding to M vertical sub-blocks in a last one odd-number super word line within the super block; M is an even number. (see fig. 6 and 7: SF0-SF3 written to the last 4 data pages (P184-P187 in chip 524) in the last odd numbered super word line (WL_G46, the 45th super wordline), further M=4 as there are 4 vertical sub-blocks (corresponding to the four WL in each WL group); SF4-SF7 written to the last 4 data pages (P188-P191 in chip 524) in the last even numbered super word line (WL_G47, the 46th super wordline), further M=4 as there are 4 vertical sub-blocks (corresponding to the four WL in each WL group).)
Regarding claim 5, Yang and Kim teaches the controller of claim 3. Yang further teaches:
wherein a portion of the wordline-dimensional check code data stored by a last data page corresponding to an even-number vertical sub-block in the last one even-number super wordline is used to correct an error occurring in data of a vertical sub-block, having an even number identical to a number of the even-number vertical sub-block, in a plurality of even-number super wordlines within the super block; and, another portion of the wordline-dimensional check code data stored by a last data page corresponding to an odd-number vertical sub-block in the last one even-number super wordline is used to correct an error occurring in data of another vertical sub-block, having an odd number identical to a number of the odd-number vertical sub-block, in a plurality of even-number super wordlines within the super block. (see fig. 6 and 7: SF4-SF7 written to the last 4 data pages (P188-P191 in chip 524) in the last even numbered super word line (WL_G47, the 46th super wordline). And see para. 46: Final parity check codes SF0-SF7 can be used to correct errors if data errors occur. For instance, if one word line in the word line set WL_G0 is open… the flash memory controller 110 can re-generate the parity check codes S8, S16, …, S184 and final parity check code SF0 by reading data from other word line sets so as to re-generate the parity check code S0, and then can use the parity check code S0 and data content read from the data pages P0 of flash memory chips 512, 522, and 524 to generate data of the data page P0 of flash memory chip 514.) See that the final parity check codes can be used to reobtain the individual parity codes they were generated from. Each of the individual parity check codes can then be used to correct the WLs they correspond to. Also, from fig. 7 it is evident that final parity check codes in the last even WL group (SF4-SF7) are generated from individual parity check codes corresponding to WLs in even WL groups within the same vertical sub-block as the final parity check codes are stored in. For example, see SF4 is stored in the first WL of WL_G47, and is generated from parity codes corresponding to the first wordlines (the first vertical sub-block) in even wordline groups. Therefore, SF4 is stored in the first vertical sub-block and is used to correct errors occurring in the first vertical sub-block (in even-numbered WL groups).
Regarding claim 6, Yang and Kim teaches the controller of claim 3. Yang further teaches:
wherein a portion of the wordline-dimensional check code data stored by a last data page corresponding to an even-number vertical sub-block in the last one odd-number super wordline is used to correct an error occurring in data of a vertical sub-block, having an even number identical to a number of the even-number vertical sub-block, in a plurality of odd-number super wordlines within the super block; and, another portion of the wordline-dimensional check code data stored by a last data page corresponding to an odd-number vertical sub-block in the last one odd-number super wordline is used to correct an error occurring in data of another vertical sub-block, having an odd number identical to a number of the odd-number vertical sub-block, in a plurality of odd-number super wordlines within the super block. (see fig. 6 and 7: SF0-SF3 written to the last 4 data pages (P184-P187 in chip 524) in the last odd numbered super word line (WL_G46, the 45th super wordline). And see para. 46: Final parity check codes SF0-SF7 can be used to correct errors if data errors occur. For instance, if one word line in the word line set WL_G0 is open… the flash memory controller 110 can re-generate the parity check codes S8, S16, …, S184 and final parity check code SF0 by reading data from other word line sets so as to re-generate the parity check code S0, and then can use the parity check code S0 and data content read from the data pages P0 of flash memory chips 512, 522, and 524 to generate data of the data page P0 of flash memory chip 514.) See that the final parity check codes can be used to reobtain the individual parity codes they were generated from. Each of the individual parity check codes can then be used to correct errors in WLs they correspond to. Also, from fig. 7 it is evident that final parity check codes in the last odd WL group (SF0-SF3) are generated from individual parity check codes corresponding to WLs in odd WL groups within the same vertical sub-block as the final parity check codes are stored in. For example, see SF0 is stored in the first WL of WL_G46, and is generated from parity codes corresponding to the first wordlines (the first vertical sub-block) in odd wordline groups. Therefore, SF0 is stored in the first vertical sub-block and is used to correct errors occurring in the first vertical sub-block (in odd-numbered WL groups).
Regarding claim 7, the combination of Yang and Kim teaches the controller of claim 1. Yang further teaches:
wherein the flash memory controller writes and stores different portions of the [WL-dimensional check code] respectively into a last one data page of a last one even-number [WL group] and a last one data page of a last one odd-number [WL group] respectively included by each of a plurality of [vertical blocks] within the super block. (see fig. 6 and 7: SF0-SF3 written to the last 4 data pages (P184-P187 in chip 524) in the last odd numbered super word line (WL_G46, the 45th super wordline), further M=4 as there are 4 vertical sub-blocks (corresponding to the four WL in each WL group); SF4-SF7 written to the last 4 data pages (P188-P191 in chip 524) in the last even numbered super word line (WL_G47, the 46th super wordline), further M=4 as there are 4 vertical sub-blocks (corresponding to the four WL in each WL group).)
Kim teaches:
[calculating and storing error correcting bits with respect to a horizontal AND a vertical dimension] (see pg. 200, RHC, section 3: We propose applying two-dimensional (2D) error coding techniques [47, 52] to the on-die embedded memory system to enable fast common-case error-free operation while still maintaining high error coverage with low VLSI overheads. The key innovation in 2D error coding is the combination of light-weight horizontal per-word error coding with vertical column-wise error coding. The horizontal and vertical coding can either be error detection codes (EDC) or error correcting codes (ECC). The types of codes used in the horizontal and vertical directions allow us to trade-off the error coverage against the VLSI overheads to tailor the design to the types and frequency of errors expected.)
It would have been obvious to one of ordinary skill in the art, having the teachings of Yang and Kim before them, before the effective filing date of the claimed invention to perform error coding with respect to a horizontal AND a vertical direction (Kim) into the flash memory storage method (Yang) such that additional final parity check codes are calculated with respect to vertical groupings of word lines (constituting a vertical-dimensional check code), that could be used additional error detection/correction in the super block to obtain the original data, to allow for benefits such as higher multi-bit error coverage (Kim, pg. 202, LHC).
It would be obvious to one of ordinary skill in the art, when attempting to implement error correction with respect to the horizontal AND vertical dimensions into Yang’s system that uses just horizontal error correction, to perform vertical error correction using the horizontal error correction as a roadmap, but swapping the vertical groups and WL groups when calculating/storing the final parities. Yang teaches horizontal error correction where two final parities are calculated for each vertical group: one from XORing the parities of wordlines in the vertical group, in the even WL groups, one from XORing the parities of wordlines in the vertical group, in the odd WL groups. The final parities corresponding to even WL groups are stored in their respective vertical groups in the last page of the last even WL group, and the final parities corresponding to odd WL groups are stored in their respective vertical groups in the last page of the last odd WL group.
If the vertical groups and WL groups are swapped to obtain additional vertical error correction, the result would clearly be this: vertical error correction where two final parities are calculated for each WL group: one from XORing the parities of wordlines in the WL group, in the even vertical groups, one from XORing the parities of wordlines in the WL group, in the odd vertical groups. The final parities corresponding to even vertical groups are stored in their respective WL group in the last page of the last even vertical group, and the final parities corresponding to odd vertical groups are stored in their respective WL groups in the last page of the last odd vertical group. Thus, clearly arriving at the subject matter of claim 7.
Regarding claim 8, the combination of Yang and Kim teaches the method of claim 7. Yang further teaches:
The flash memory controller of claim 7, wherein a portion of the [WL-group--dimensional] check code data stored by the last one data page of the last one even-number [WL-group] block in a specific [vertical sub-block] within the super block is used to correct an error occurring in data of a plurality of even-number [WL-groups] in the specific [vertical sub-block]; and, another portion of the [WL-group-dimensional] check code data stored by the last one data page of the last one odd-number [WL-group] in the specific [vertical sub-block] within the super block is used to correct an error occurring in data of a plurality of odd-number [WL-groups] in the specific [vertical sub-block].
(see fig. 6 and 7: SF0-SF3 written to the last 4 data pages (P184-P187 in chip 524) in the last odd numbered super word line (WL_G46, the 45th super wordline) and SF4-SF7 written to the last 4 data pages (P188-P191 in chip 524) in the last even numbered super word line (WL_G47, the 46th super wordline). And see para. 46: Final parity check codes SF0-SF7 can be used to correct errors if data errors occur. For instance, if one word line in the word line set WL_G0 is open… the flash memory controller 110 can re-generate the parity check codes S8, S16, …, S184 and final parity check code SF0 by reading data from other word line sets so as to re-generate the parity check code S0, and then can use the parity check code S0 and data content read from the data pages P0 of flash memory chips 512, 522, and 524 to generate data of the data page P0 of flash memory chip 514.) See that the final parity check codes can be used to reobtain the individual parity codes they were generated from. Each of the individual parity check codes can then be used to correct the WLs they correspond to. Also, from fig. 7 it is evident that final parity check codes in the last even (odd) WL group are generated from individual parity check codes corresponding to WLs in even (odd) WL groups within the same vertical sub-block as the final parity check codes are stored in. For example, see SF0 is stored in the first WL (first vertical sub-block) of last odd super wordline WL_G46, and is generated from parity codes corresponding to the first wordlines (the first vertical sub-block) in odd wordline groups. Therefore, SF0 is stored in the first vertical sub-block and is used to correct errors occurring in the first vertical sub-block (in odd-numbered WL groups). Also see SF4 is stored in the first WL (first vertical sub-block) of last even super wordline WL_G47, and is generated from parity codes corresponding to the first wordlines (the first vertical sub-block) in even wordline groups. Therefore, SF4 is stored in the first vertical sub-block and is used to correct errors occurring in the first vertical sub-block (in even-numbered WL groups).
Kim teaches:
[calculating and storing error correcting bits with respect to a horizontal AND a vertical dimension] (see pg. 200, RHC, section 3: We propose applying two-dimensional (2D) error coding techniques [47, 52] to the on-die embedded memory system to enable fast common-case error-free operation while still maintaining high error coverage with low VLSI overheads. The key innovation in 2D error coding is the combination of light-weight horizontal per-word error coding with vertical column-wise error coding. The horizontal and vertical coding can either be error detection codes (EDC) or error correcting codes (ECC). The types of codes used in the horizontal and vertical directions allow us to trade-off the error coverage against the VLSI overheads to tailor the design to the types and frequency of errors expected.)
It would have been obvious to one of ordinary skill in the art, having the teachings of Yang and Kim before them, before the effective filing date of the claimed invention to perform error coding with respect to a horizontal AND a vertical direction (Kim) into the flash memory storage method (Yang) such that additional final parity check codes are calculated with respect to vertical groupings of word lines (constituting a vertical-dimensional check code), to allow for benefits such as higher multi-bit error coverage (Kim, pg. 202, LHC).
It would be obvious to one of ordinary skill in the art, when attempting to implement error correction with respect to the horizontal AND vertical dimensions into Yang’s system that uses just horizontal error correction, to perform vertical error correction using the horizontal error correction as a roadmap, but swapping the vertical groups and WL groups when calculating/storing the final parities. Yang teaches horizontal error correction where two final parities are calculated for each vertical group: one from XORing the parities of wordlines in the vertical group, in the even WL groups, one from XORing the parities of wordlines in the vertical group, in the odd WL groups. The final parities corresponding to even WL groups are stored in their respective vertical groups in the last page of the last even WL group, and the final parities corresponding to odd WL groups are stored in their respective vertical groups in the last page of the last odd WL group. Further, the final parities in the last odd WL group in a respective vertical group are used to correct errors in odd WL groups in the respective vertical group, and final parities in the last even WL group in a respective vertical group are used to correct errors in even WL groups in the respective vertical group.
If the vertical groups and WL groups are swapped to obtain additional vertical error correction, the result would clearly be this: vertical error correction where two final parities are calculated for each WL group: one from XORing the parities of wordlines in the WL group, in the even vertical groups, one from XORing the parities of wordlines in the WL group, in the odd vertical groups. The final parities corresponding to even vertical groups are stored in their respective WL group in the last page of the last even vertical group, and the final parities corresponding to odd vertical groups are stored in their respective WL groups in the last page of the last odd vertical group. Further, the final parities in the last odd vertical group in a respective WL group are used to correct errors in odd vertical groups in the respective WL group, and final parities in the last even vertical group in a respective WL group are used to correct errors in even vertical groups in the respective WL group. Thus, clearly arriving at the subject matter of claim 8.
Regarding claim 9, claim 9 corresponds to claims 3 and 8, except for the added requirement that: two second last data pages respectively included by the last one even-number vertical sub-block and the last one odd-number vertical sub-block in the last one even-number super wordline are used to store a portion of vertical sub-block check code data… and, two second last data pages respectively included by the last one even-number vertical sub-block and the last one odd-number vertical sub-block in the last one odd-number super wordlineare used to store another portion of vertical sub-block check code data…
As discussed in depth in the rejection of claim 8, it would be obvious to one of ordinary skill in the art, having the teachings of Yang and Kim before them, before the effectively filed date of the claimed invention to incorporate a horizontal check code AND a vertical check code (as taught by Kim) into the system of Yang, that just teaches a horizontal check code, to allow for benefits such as higher multi-bit error coverage (Kim, pg. 202, LHC).
One of ordinary skill in the art, using the horizontal check code of Yang as a roadmap for implementing the vertical check code, would be motivated to store it as follows: The final parities corresponding to even vertical groups are stored in their respective WL group in the last page of the last even vertical group, and the final parities corresponding to odd vertical groups are stored in their respective WL groups in the last page of the last odd vertical group.
However, one of ordinary skill in the art would obviously realize that the last page of the last even and odd vertical sub-blocks in the last even and odd wordline groups of Yang would aready be populated with the final parities of the horizontal (wordline-group dimensional) check codes. Therefore, one of ordinary skill in the art, motivated to store a subset of final parities of a vertical dimensional check code in the (already populated) last pages of the last even and odd vertical blocks in the last even and odd wordline groups, would find it obvious to instead store the subset of final parities of the vertical dimensional check code in the second last pages.
It would have been obvious to one of ordinary skill in the art, having the teachings of Yang and Kim before them, before the effective filing date of the claimed invention to perform error coding with respect to a horizontal AND a vertical direction (Kim) into the flash memory storage method (Yang) such that additional final parity check codes are calculated with respect to vertical groupings of word lines (constituting a vertical-dimensional check code), to allow for benefits such as higher multi-bit error coverage (Kim, pg. 202, LHC).
Claims 10, 11, 12-14, and 16-20 correspond to claims 1, 7, 1-3, and 5-9 are rejected accordingly.
Claims 4 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Kim and Igahara (US 2019/0095116).
Regarding claim 4, the combination of Yang and Kim teaches the controller of claim 3. In the analogous art of memory controls, Igahara teaches:
wherein a data page of the super block comprises a size of a single data page in a single-level-cell writing mode; the data page of the super block comprises a size of two sub-data pages in a multi-level-cell writing mode; the data page of the super block comprises a size of three sub-data pages in a triple-level-cell writing mode; and, the data page of the super block comprises a size of four sub-data pages in a quad-level-cell writing mode. (see para. 78: NAND flash memory 5 may execute a write operation in an SLC mode in which one bit is written per memory cell, an MLC mode in which two bits are written to per memory cell, a TLC mode in which three bits are written to per memory cell, or a QLC mode in which four bits are written to per memory cell.)
It would be obvious to one of ordinary skill in the art, to combine the teachings of Yang and Kim with Igahara to incorporate treating memory cells (pages) as different sizes depending on a write operation mode (Igahara) into the system for performing dimensional error correction (Yang and Kim), to allow for benefits such as: dynamic flexibility and high performance (Igahara, para. 105).
Claim 15 corresponds to claim 4, and is rejected accordingly.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JACK KENSINGTON BARNETT/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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