DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 2-20 are presented for the examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17, 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
The following terms lack proper antecedent basis:
the registering— claims 17, 20.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-13 of US Patent US 12093756 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because both computer systems comprise substantially the same elements.
US Patent teaches 2 executing, on each of the hardware processing components, one or more pipeline stages of a plurality of pipeline stages(
one or more pipeline stages of the plurality of pipeline stages),
so that each pipeline stage is configured to send and/or receive messages to at least one other pipeline stage in the processing pipeline(herein communication between respective pipeline stages of the plurality of pipeline stages)
processing the received data message in one or more respective pipeline stages of the processing pipeline to generate a processed message( processing the received data message in one or more respective registered pipeline stages of the registered plurality of the pipeline stages of the session to generate a processed message), wherein said processing the received data message includes: messages being exchanged between respective pairs of publishers and subscribers among the pipeline stages in the processing pipeline( messages being exchanged between respective pairs of publishers and subscribers among the registered publishers and the registered subscribers) And outputting the processed data message( outputting the processed data message)
The difference between claims 1, 15, 18 of the copending application and this case is subsequent processing are each of the plurality of pipeline stages self-declaring as a publisher and/or subscriber for at least one topic of a plurality of topics;forming a processing pipeline for processing a received data message, the processing pipeline comprising the plurality of pipeline stages arranged in accordance with the self- declarations of the respective pipeline stages It would have been obvious to one of the ordinary skill level in the art to include above feature because this improves the overall throughput of the stage in performing the task.
Claims 2-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of US Patent US 11775361 B2.
. Although the claims at issue are not identical, they are not patentably distinct from each other because both computer systems comprise substantially the same elements.
US Patent teaches 2 executing, on each of the hardware processing components, one or more pipeline stages of a plurality of pipeline stages(
one or more pipeline stages of the plurality of pipeline stages),
so that each pipeline stage is configured to send and/or receive messages to at least one other pipeline stage in the processing pipeline(herein communication between respective pipeline stages of the plurality of pipeline stages)
processing the received data message in one or more respective pipeline stages of the processing pipeline to generate a processed message( processing the received data message in one or more respective registered pipeline stages of the registered plurality of the pipeline stages of the session to generate a processed message), wherein said processing the received data message includes: messages being exchanged between respective pairs of publishers and subscribers among the pipeline stages in the processing pipeline( messages being exchanged between respective pairs of publishers and subscribers among the registered publishers and the registered subscribers via at least one message queue;) And outputting the processed data message( outputting the processed data message)
The difference between claims 1, 15, 18 of the copending application and this case is subsequent processing are each of the plurality of pipeline stages self-declaring as a publisher and/or subscriber for at least one topic of a plurality of topics;forming a processing pipeline for processing a received data message, the processing pipeline comprising the plurality of pipeline stages arranged in accordance with the self- declarations of the respective pipeline stages It would have been obvious to one of the ordinary skill level in the art to include above feature because this improves the overall throughput of the stage in performing the task.
Claims 2-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-15 of US Patent 11567815 B2
. Although the claims at issue are not identical, they are not patentably distinct from each other because both computer systems comprise substantially the same elements.
US Patent teaches 2 executing, on each of the hardware processing components, one or more pipeline stages of a plurality of pipeline stages(
one or more pipeline stages of the plurality of pipeline stages),
so that each pipeline stage is configured to send and/or receive messages to at least one other pipeline stage in the processing pipeline(herein communication between respective pipeline stages of the plurality of pipeline stages)
processing the received data message in one or more respective pipeline stages of the processing pipeline to generate a processed message( processing the received data message in one or more respective registered pipeline stages of the registered plurality of the pipeline stages of the session to generate a processed message), wherein said processing the received data message includes: messages being exchanged between respective pairs of publishers and subscribers among the pipeline stages in the processing pipeline( messages being exchanged between respective pairs of publishers and subscribers among the registered publishers and the registered subscribers) And outputting the processed data message( outputting the processed data message)
The difference between claims 1, 15, 18 of the copending application and this case is subsequent processing are each of the plurality of pipeline stages self-declaring as a publisher and/or subscriber for at least one topic of a plurality of topics;forming a processing pipeline for processing a received data message, the processing pipeline comprising the plurality of pipeline stages arranged in accordance with the self- declarations of the respective pipeline stages It would have been obvious to one of the ordinary skill level in the art to include above feature because this improves the overall throughput of the stage in performing the task.
Claims 2-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-11 of US Patent 11243826 B2
. Although the claims at issue are not identical, they are not patentably distinct from each other because both computer systems comprise substantially the same elements.
US Patent teaches 2 executing, on each of the hardware processing components, one or more pipeline stages of a plurality of pipeline stages(
one or more pipeline stages of the plurality of pipeline stages),
so that each pipeline stage is configured to send and/or receive messages to at least one other pipeline stage in the processing pipeline(herein communication between respective pipeline stages of the plurality of pipeline stages)
processing the received data message in one or more respective pipeline stages of the processing pipeline to generate a processed message( ompleting processing of the data message in the application by processing the data message in each of the plurality of the pipeline stages of the processing pipeline of the application to generate an output message), wherein said processing the received data message includes: messages being exchanged between respective pairs of publishers and subscribers among the pipeline stages in the processing pipeline( messages being exchanged between respective pairs of publishers and subscribers among the registered publishers and the registered subscribers) And outputting the processed data message( transmitting the output message)
The difference between claims 1, 15, 18 of the copending application and this case is subsequent processing are each of the plurality of pipeline stages self-declaring as a publisher and/or subscriber for at least one topic of a plurality of topics;forming a processing pipeline for processing a received data message, the processing pipeline comprising the plurality of pipeline stages arranged in accordance with the self- declarations of the respective pipeline stages It would have been obvious to one of the ordinary skill level in the art to include above feature because this improves the overall throughput of the stage in performing the task.
Claims 2-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-16 of US Patent10810064 B2
Although the claims at issue are not identical, they are not patentably distinct from each other because both computer systems comprise substantially the same elements.
US Patent teaches 2 executing, on each of the hardware processing components, one or more pipeline stages of a plurality of pipeline stages(
one or more pipeline stages of the plurality of pipeline stages),
so that each pipeline stage is configured to send and/or receive messages to at least one other pipeline stage in the processing pipeline(herein communication between respective pipeline stages of the plurality of pipeline stages)
processing the received data message in one or more respective pipeline stages of the processing pipeline to generate a processed message( completing processing of the data message in the application by processing the data message in each of the plurality of the pipeline stages of the processing pipeline of the application to generate an output message), wherein said processing the received data message includes: messages being exchanged between respective pairs of publishers and subscribers among the pipeline stages in the processing pipeline( messages being exchanged between respective pairs of publishers and subscribers among the registered publishers and the registered subscribers) And outputting the processed data message( transmitting the output message)
The difference between claims 1, 15, 18 of the copending application and this case is subsequent processing are each of the plurality of pipeline stages self-declaring as a publisher and/or subscriber for at least one topic of a plurality of topics;forming a processing pipeline for processing a received data message, the processing pipeline comprising the plurality of pipeline stages arranged in accordance with the self- declarations of the respective pipeline stages It would have been obvious to one of the ordinary skill level in the art to include above feature because this improves the overall throughput of the stage in performing the task.
this is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 15, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kambatla ( US 20120284331 A1 ) in view of Fowler( US 20090256836 A1).
As to claim 2, Kambatla teaches at least one memory; and a plurality of hardware processing components, wherein the at least one memory and the plurality of hardware processing components are configured to perform operations comprising( The system 500 may include computational nodes 502, in communication over a network 506. Each of the computational nodes 502 may include a processor 508, para[0044], ln 1-5/ such as read-only memory and random access memory, para[0046], ln 8-10);
executing, on each of the hardware processing components, one or more pipeline stages of a plurality of pipeline stages, each of the plurality of pipeline stages self-declaring as a publisher and/or subscriber for at least one topic of a plurality of topics( The event processing pipeline 202 may generate notifications to be delivered to subscribers, based on events 204 received from publishers. The publishers publish the events through the publish-related API, which requires two parameters, the event and the associated topic. The event can be the 5% discount on the product, and the topic can be the product type, for example, the DVD player. The generated notifications may be placed in the shared intermediate store 212. The notification processing pipeline 210 may retrieve the notifications from the store 212, and deliver the generated notifications. The work of the pipelines 202, 210 may be performed in stages. The processing of each stage of the pipelines 202, 210 may be performed, respectively, by scalable matching, and notification delivery engines, para[0020]/ the event processing pipeline 202 may include four stages. Stage 214 may perform access control enforcement. The stage 214 may ensure that sources of the published events 204 are authorized to participate in the notification service 200, according to the topic-specific policies that are defined by the system administrator. For example, a particular event publisher, who is a merchant, is only entitled to publish events to the topics related to electronics, but not others. In other words, events 204 that violate pre-defined topic-based policies may be filtered out of the event processing pipeline 202, para[0021]),
processing the received data message in one or more respective pipeline stages of the processing pipeline to generate a processed message( Stage 216 may perform topic generation for all the published events 204 that have passed the access control filtering stage 214 . The stage 216 may retrieve topics for the published events 204, and generate a tuple that can be represented as <topic, event>. That is, each tuple may include a topic and an event. The output of the stage 216 is the aggregation of the events that fall into the same topic, and thus can be represented as <topic, event list>. The stage 218 may perform topic-based subscription matching, which identifies subscriptions 206 to the topics that are involved in the published events, para[0022], ln 1-14)
Fowler teaches forming a processing pipeline for processing a received data message, the processing pipeline comprising the plurality of pipeline stages arranged in accordance with the self- declarations of the respective pipeline stages so that each pipeline stage is configured to send and/or receive messages to at least one other pipeline stage in the processing pipeline( The arrangement of stages in a pipeline may vary in different embodiments, as well as for performing different functions in different applications. FIG. 6, for example, illustrates an exemplary software pipeline 220 including a plurality of stage instances 222, also separately designated as instances A-I, each of which representing a thread of execution implemented on an IP block in NOC 102. The stage instances 222 are arranged in pipeline 220 into five stages, a first stage with instance A, a second stage with instances B and C, a third stage with instances D, E and F, a fourth stage with instances G and H, and a fifth stage with instance I. As can be seen from FIG. 6, instances may have a one-to-one, a one-to-many and/or a many-to-one relationship with other instances in the pipeline. Instances may operate collectively with one another in a particular stage to perform parallel tasks and share the workload, para[0070]/ Each stage in a pipeline is composed of a flexibly configurable module of computer program instructions identified by a stage 1D with each stage executing on a thread of execution on an IP block 104 of a NOC 102. The stages are flexibly configurable in that each stage may support multiple instances of the stage, so that a pipeline may be scaled by instantiating additional instances of a stage as needed depending on workload. Because each stage is implemented by computer program instructions executing on an IP block 104 of a NOC 102, para[0067], ln 9-17/ HIP 212 (FIG. 5) typically sets up the pipeline by configuring each stage with a desired number of instances, with the network location of each instance of each stage provided to other instances of other stages to enable each instance to send its resultant workload to the proper instance in the next stage. Multiple instances may be assigned to a particular stage to provide additional processing resources relative to other stages, e.g., so work flows through the pipeline as efficiently as possible, para[0071], ln 6-16);
messages being exchanged between respective pairs of publishers and subscribers among the pipeline stages in the processing pipeline; and outputting the processed data message( Each stage implements a producer/consumer relationship with a next stage. The first stage receives work instructions and work piece data through a HIP 212, carries out its designated data processing tasks on the work piece, produces output data, and sends the produced output data to the next stage in the pipeline, which consumes the produced output data from the first stage by carrying out its designated data processing tasks on the produced output data from the first stage, thereby producing output data that is subsequently sent on to a next stage in the pipeline. This sequence of operations continues to the last stage of the pipeline, which then stores its produced output data in an output data structure for eventual return through the HIP 212 to the originating application 216, para[0069]).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this improves the overall throughput of the stage in performing the task.
As to claims 15, 18, they are rejected for the same reason as to claim 2 above. In additional, Kambatla teaches non-transitory computer-readable storage medium( units may include non-transitory, computer-readable storage media,, para[0046]).
Claim(s) 3, 16, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kambatla ( US 20120284331 A1 ) in view of Fowler( US 20090256836 A1) and further in view of Truong( US 20150347196 A1).
As to claim 3, Truong teaches wherein the at least one memory and the plurality of hardware processing components are further configured to: instantiate a control session; subscribe each of the pipeline stages to the control session; and provide for signaling one or more predetermined events to the plurality of pipeline stages by publishing to the control session(The pipeline arrangement of threads may be referred to as a “waterfall” in the examples below. The threads may be thought of as “stateless” because they wake up and view the state of the thread's pointer above them in the waterfall and perform actions based on the pointer's value. For example, a consumer thread may be below a producer thread in the waterfall (the hierarchy will be explained in further detail below) and track the state of the pointer managed by the producer thread. In such an example, the consumer thread reads the producer thread's pointer and performs actions based on its value. The producer thread and consumer thread may agree about the state of the session before it is published by the producer thread and used by the consumer thread para[0033], In 12-21) , A producer thread and a consumer thread may each manage a pointer that is initialized to reference a particular value. The producer thread may process a session by processing a first set of configuration items in the session. After the producer thread is finished processing the first set of configuration items, the producer thread may publish the session. The producer thread may publish the session by updating the producer thread's pointer to reference the session. Thus, the memory address that the producer thread's pointer references has changed from referencing the initial value to referencing the session. Thus, a change in the producer thread's pointer may represent a transition in the session state information( para[0034]).
It would have been oblivious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this prevents deadlocks but may also increase the complexity of implementing access to data.
As to claims 16, 19, they are rejected for the same reason as to claim 3 above.
Claim(s) 4, 5 are rejected under 35 U.S.C. 103 as being unpatentable over Kambatla ( US 20120284331 A1 ) in view of Fowler( US 20090256836 A1) and further in view of Arnold( US 6490674 B1).
As to claim 4, Arnold teaches wherein the at least one memory and the plurality of hardware processing components are further configured to determine an assignment of the plurality of pipeline stages to the plurality of hardware processing components( Each of the AND logic 164, 166, and 168 then compares the received m-bit register identifiers to determine whether or not a data dependency exists between the consumer being processed in the register stage 133 and any of the producers being processed in any of the other stages 136, 139, and 142. If there is a data dependency between the consumer in the register stage 133 and any one of the producers in the other stages 136, 139, and 142 that has yet to produce its data (i.e., has yet to make its data available to the consumer), then the comparison logic 144 determines that a data dependency hazard exists between the consumer and the one producer, col 10, In 20-33/ FIG. 3 shows another embodiment of circuitry that is conventionally used to process instructions in one of the pipelines 21 and to check for data dependencies that create data dependency hazards. The instruction associated with an n-bit encoded register identifier is latched into stages 25, 28, 32, and 35 and processed by processing circuitry 66, 69, 72, and 75, as described above. However, the n-bit register identifier is not decoded by a decoder 42 (FIG. 2), col 7, In 30-37/ n any event, the m-bit register identifier produced by the coalescing circuitry 179 identifies each register 37 that is identified by an m-bit register identifier received by the coalescing circuitry 179 and, in doing so, preferably identifies each register 37 that is written to by any of the producers in the stages 136, 139, or 142 of any of the pipelines 132. In this regard, each bit of the m-bit register identifier produced by the coalescing circuitry 179 that corresponds to one of the registers 37 identified by a received m-bit register identifier should be asserted, col 13, In 10-20).
It would have been oblivious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this provides need exists in the industry for an efficient processing system with minimal complexity and circuitry for detecting data hazards between instructions of a computer program.
As to claim 5, Arnold teaches the at least one memory and the plurality of hardware processing components are further configured to determine the assignment based on an ingress message interface and an egress message interface on each of the pipeline stages( col 18, In 63- 67 to col 19, In 1-10) for the same reason as to claim 4 above.
Claim(s) 6, 7, 17, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kambatla ( US 20120284331 A1 ) in view of Fowler( US 20090256836 A1) in view of Truong(US 20150347196 A1) and further in view of Layman( US 20170085445 A1).
As to claim 6, Truong teaches the registering each of the plurality
of pipeline stages as a publisher and/or subscriber in a session for processing each of the plurality of pipeline stages performing at least one of publishing a topic to the session or subscribing to a topic on the session( para[0033], In 1-20/ para[0047], In 1-10).
It would have been oblivious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this prevents deadlocks but may also increase the complexity of implementing access to data.
Layman teaches a received data message comprises each of the plurality of pipeline stages performing at least one of publishing a topic to the session or subscribing to a topic on the session( In one implementation, events are delivered over HTTP to input pipeline 204. In another implementation, events are transmitted via POST requests to a receiver operating on behalf of input pipeline 204. For instance, Twitter Firehose
API (accessible via Twitter-affiliated companies like Datashift, TweetStreamer, tiwwter4j) provides unbounded time stamped events, called tweets, as a stream of JSON objects along with metadata about those tweets, including timestamp data about the tweets, user information, location, topics, keywords, retweets, followers, following, timeline, user line, etc, para[0108], In 3-12/ In a particular implementation, Apache Kafkaᵀ is used as the input pipeline 204. Kafka is a distributed messaging system with a publish and subscribe model. Kafka maintains events in categories called topics. Events are published by so-called producers and are pulled and processed by so-called consumers., para[0115], In 1-6).
It would have been oblivious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this provides an opportunity arises to provide systems and methods that use simple and easily codable declarative language based solutions to execute big data computing and analytics tasks.
As to claim 7, Layman teaches the registering each of the plurality of pipeline stages as a publisher and/or subscriber in a session for processing a received data message at least one of the plurality of pipeline stages performing the subscribing to a topic on the session in response to a received message notifying of the topic( para[0108], In 1-12/ para[0115], In 1-6) for the same reason as to claim 6 above.
As to claims 17, 20, they are rejected for the same reason as to claim 6 above.
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kambatla ( US 20120284331 A1 ) in view of Fowler( US 20090256836 A1) and further in view of Young( US 20020198888 A1).
As to claim 8, Young teaches the session is instantiated as a thread( receiving metered information in the form of session objects from the associated VAS device, persistently storing the session objects, and passing the session objects to the pipeline 130, para[0033], ln 6-11/ The pipeline 130 processes the metered session through a sequence of steps or stages that transform the metered data contents of the session objects into the processed usage data, which are stored in memory 135. The processed usage data can include a subset of the metered properties of the metered data along with additional properties that are synthesized from the metered properties, para[0034], ln 1-7/ FIG. 4 shows an architectural view of a pipeline stage 400. The stage 400 includes an input queue 402 (e.g., a FIFO buffer), a multithreading process space 404, and an output queue 408 (e.g., a FIFO buffer). The process space 404 processes a number of plug-ins, numbered 1 through 8, under the control of an execution management framework 412, and pursuant to processing threads stored in a thread pool 414. A stage configuration module 416 receives configuration files 418 from the configuration manager 150, which define stage operations as well as operation of the plug-ins nos. 1-8 of the corresponding process space 404 and their processing interdependencies. , para[0052], ln 1-12).
It would have been oblivious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this provides controls the plug-in processing modules to execute in series, or in parallel, to speed processing by the plug-ins while accommodating computational dependencies.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kambatla ( US 20120284331 A1 ) in view of Fowler( US 20090256836 A1) and further in view of Mejdrich( US 20110292063 A1).
As to claim 9, Mejdrich teaches a first pair of the plurality of pipeline stages are configured to exchange messages via a shared memory and a second pair of the pipeline stages are configured to exchange messages over a network( ore software pipelines 204 on top of an NOC architecture. Each pipeline 204 is typically allocated one or more data structures 206 in a shared memory 208 to enable different stages of a pipeline to exchange data. Furthermore, an interrupt mechanism 210 is provided to enable stages of a pipeline to notify one another of pending work to be performed., para[0076], ln 5-12/ Each stage is assigned a stage ID, and each instance of a stage is assigned an identifier. HIP 212 (FIG. 5) typically sets up the pipeline by configuring each stage with a desired number of instances, with the network location of each instance of each stage provided to other instances of other stages to enable each instance to send its resultant workload to the proper instance in the next stage. earlier and/or later stage 3 to which an instance of stage 2 is authorized to send its resultant workload, para[0082], ln 5-16).
It would have been oblivious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this ensures synchronization of shared texture data among the stages of the pipeline.
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kambatla ( US 20120284331 A1 ) in view of Fowler( US 20090256836 A1) and further in view of Kling(US 6728867 B1).
As to claim 10, Kling teaches the at least one memory and the plurality of hardware processing components are further configured to automatically, in accordance with configuration parameters, decompose a received sequence of instructions to generate the plurality of pipeline stages( FIG. 3 is a diagram of simplified processor pipeline 300 in which the present invention may be implemented. For a processor represented by pipeline 300, instruction processing is divided into a sequence of operations, and each operation is performed by hardware in a corresponding pipe stage. An instruction is completed as it progresses from one pipe stage to the next on successive clock cycles. For example, the instruction may be fetched in pipe stage 310(1), operands may be retrieved and processed in pipe stages 310(i)-310(j), and results generated by executing the instruction may be written to the processor state in pipe stage 310(n). Different processors may divide instruction execution into different operations and employ different numbers and types of pipe stages 310 to implement these operations. Except where noted, the present invention does not require a specific configuration of pipe stages 310, col 5, ln 31-45).
It would have been oblivious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this provides a high frequency, flush-based pipeline. Such a pipeline allows sufficient time for the check operation to complete before any instructions that depend on data returned by the advanced load retire.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kambatla ( US 20120284331 A1 ) in view of Fowler( US 20090256836 A1) in view of Kling(US 6728867 B1) and further in view of Gordy (US 20070169046 A1).
As to claim 11, Gordy teaches the at least one memory and the plurality of hardware processing components are further configured to automatically, in accordance with at least a function of respective pipeline stages, distribute the respective pipeline stages among the plurality of hardware processing components( Another strategy includes detecting two or more processing stages which are then distributed across the available processors, whereby data is then passed from an input processor to the stage-one processor to the stage-two processor and so on until the last stage processor produces the final output, para[0032], ln 17-15).
It would have been oblivious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this provides transparent, parallel, coherent and highly available access to a database constructed from single-tier or multi-tier storage clusters.
Claim(s) 12, 13, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kambatla ( US 20120284331 A1 ) in view of Fowler( US 20090256836 A1) and further in view of Gupta( US 20040088520 A1).
As to claim 12, Gupta teaches the at least one memory and the plurality of hardware processing components are further configured to perform said processing the received data message by accessing a transaction processing engine with respect to the data message( In one embodiment, host IF block 146 may pass a pointer or other indication of a memory location to first INIT block 120 indicating the position of the control data (also known as the Task Frame). A task frame contains all the information that is required to control the execution of one particular task through the various stages of a pipeline. Different stages of pipeline 100 may need different portions of the task frame. The various INIT blocks 120-124 may perform memory transactions using the pointers supplied by host IF block 146 to access control data from the task frame for use by the respective SA. The timing of these transactions is carefully controlled by the timing controller that starts the respective INIT blocks. Host IF block 146 decodes commands from the host processor including the run command that begins the processing of a new task in the pipeline. A chain link including links 147-155 links each of the INIT and FINAL blocks and is used to propagate the task frame base address through the pipeline stages in parallel with the performed task. This chain link allows many tasks to be in the pipeline at the same time and stay synchronized with the corresponding base addresses, para[0023]).
It would have been oblivious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this reduces the time required to process information in a pipeline is to overlap data processing between producer and consumer stages.
As to claim 13, Gupta teaches the at least one memory and the plurality of hardware processing components are further configured to perform said processing the received data message in a plurality of the pipeline stages by said accessing the transaction processing engine in parallel for a first transaction request and another transaction request( para[0023]) for the same reason as to claim 12 above.
As to claim 14, Fowler teaches the at least one memory and the plurality of hardware processing components are further configured to dynamically determine a number of instances of a pipeline stage for said accessing the transaction processing engine( para[0085], ln 6-20) for the same reason as to claim 1 above.
Conclusion
US 20120284331 A1 teaches The event processing pipeline 202 may generate notifications to be delivered to subscribers, based on events 204 received from publishers. The publishers publish the events through the publish-related API, which requires two parameters, the event and the associated topic. The event can be the 5% discount on the product, and the topic can be the product type, for example, the DVD player. The generated notifications may be placed in the shared intermediate store 212. The notification processing pipeline 210 may retrieve the notification
US 20180024837 A1 teaches individual stages within the asynchronous pipeline are not necessarily synchronized with each other and are able to operate according to their own internal clocks in some cases. The stages in the asynchronous pipeline are sometimes referred to as “self-timed” stages. Operating speeds of the stages the asynchronous pipeline can therefore vary independently of the operating speeds of the other stages in the asynchronous pipeline, as discussed herein.
US 20090256836 A1 teaches Each stage implements a producer/consumer relationship with a next stage. The first stage receives work instructions and work piece data through a HIP 212, carries out its designated data processing tasks on the work piece, produces output data, and sends the produced output data to the next stage in the pipeline, which consumes the produced output data from the first stage by carrying out its designated data processing tasks on the produced output data from the first stage, thereby producing output data that is subsequently sent on to a next stage in the pipeline. This sequence of operations continues to the last stage of the pipeline, which then stores its produced output data in an output data structure for eventual return through the HIP 212 to the originating application 216.
US 11152087 B2 teaches multi-tenancy model 500 includes multiple data processing pipelines 400′, 400″, 400′″ corresponding to data processing pipeline 400, three data processing pipelines for three tenants, the principles of the present invention are not to be limited in scope to monitoring only three data processing pipelines for three tenants. Instead, the principles of the present invention are to include the aspect of monitoring any number of data processing pipelines for any number of tenants.
US 20150010000 A1 teaches this problem increases as the MFEs implement logical network topologies and the number of required lookups increase as the size of the logical topology grows, with each logical forwarding element in the logical topology having its own logical pipeline in some embodiments. If a packet needs to traverse more than one logical hop in a logical network, the MFE will perform the logical pipeline of each logical forwarding element that the packet traverses. While the MFE can use a flow cache to speed up processing for subsequent packets in a flow or data flow (e.g., data transmitted over a transport-layer connection), the MFE still performs the full stage-by-stage lookup process for the first packet in a flow in some embodiments
US 20080281786 A1 teaches not only can consumer activities be run in parallel, a query planner can make decisions based on this. For example, pipelining is often used to balance a query with imbalanced costs. This assumes that the planner is aware of consumer costs as traditional approaches are limited to producer activity. With this approach, a planner may choose to introduce new pipeline stages including running the consumer as its own pipeline, simply because it knows about this extension of the query.
US 20120137102 A1 teaches To illustrate, one of the stages such as reading from a file creates or produces the data buffers that are subsequently consumed by another stage such as a decoder which is part of the data pipeline. Since the data entering a stage as input might leave the stage unaltered or might get transformed during the processing at a stage, the data buffers of various kinds are needed to accomplish the overall goal of the application. In addition, it may also be possible that some of the stages have their own physical memory to store working memory buffers in which case the data from previous stage has to be copied into these local
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/LECHI TRUONG/Primary Examiner, Art Unit 2194
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