DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-14 are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of U.S. Patent No. 12095997. Although the claims at issue are not identical, they are not patentably distinct from each other because although the independent claims at issue are not identical, they are not patentably distinct from each other. Both applications teach the equalization training methodology between links coupling devices. The configuration needs to take place within a certain time window. Before timeout occurs. The present application has a different embodiment, where the ports of the device rather than the associated chip involved as embodied in the associated patent.
The table below illustrates said.
Present Application
US12095997
1. (Currently Amended) An equalization training method, comprising: obtaining a training rate of each of a downstream port and an upstream port a slave chip in a target phase of equalization training, wherein the target phase is a third phase or a fourth phase of phases of the equalization training; and determining a target rate threshold interval within which the training rate in the target phase falls, determining, based on a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configuring the target equalization timeout period as an equalization timeout period in the target phase, wherein N rate thresholds are predetermined, N is an integer greater than or equal to 0, and a longer rate threshold interval corresponds to a longer equalization timeout period, wherein equalization training in the target phase is performed on the downstream port and the upstream port within the equalization timeout period in the target phase.
1. An equalization training method, comprising: obtaining a training rate of each of a master chip and a slave chip in a target phase of equalization training, wherein the target phase is a third phase or a fourth phase of phases of the equalization training; and determining a target rate threshold interval within which the training rate in the target phase falls, determining, based on a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configuring the target equalization timeout period as an equalization timeout period in the target phase, wherein N rate thresholds are predetermined, N is an integer greater than or equal to 0, and a longer rate threshold interval corresponds to a longer equalization timeout period, wherein equalization training in the target phase is performed on the master chip and the slave chip within the equalization timeout period in the target phase.
5. (Currently Amended) An equalization training apparatus, comprising: a transceiver, configured to obtain a training rate of each of a downstream port and a upstream port in a target phase of equalization training, wherein the target phase is a third phase or a fourth phase of phases of the equalization training; and at least one processor, coupled with the transceiver, configured to: determine a target rate threshold interval within which the training rate in the target phase falls, determine, based on a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configure the target equalization timeout period as an equalization timeout period in the target phase, wherein N rate thresholds are predetermined, N is an integer greater than or equal to 0, and a longer rate threshold interval corresponds to a longer equalization timeout period, wherein equalization training in the target phase is performed on the downstream port and the upstream port within the equalization timeout period in the target phase.
5. An equalization training apparatus, comprising: a transceiver, configured to obtain a training rate of each of a master chip and a slave chip in a target phase of equalization training, wherein the target phase is a third phase or a fourth phase of phases of the equalization training; and a manager, configured to: determine a target rate threshold interval within which the training rate in the target phase falls, determine, based on a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configure the target equalization timeout period as an equalization timeout period in the target phase, wherein N rate thresholds are predetermined, N is an integer greater than or equal to 0, and a longer rate threshold interval corresponds to a longer equalization timeout period, wherein equalization training in the target phase is performed on the master chip and the slave chip within the equalization timeout period in the target phase
9. (Currently Amended) A chip, comprising: a register, configured to store a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods; a transceiver, configured to obtain a training rate of each of a master downstream port and a upstream port in a target phase of equalization training, wherein the target phase is a third phase or a fourth phase of phases of the equalization training; and at least one processor, coupled with the transceiver, configured to: determine a target rate threshold interval within which the training rate in the target phase falls, determine, based on the correspondence between the N+1 rate threshold intervals and the N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configure the target equalization timeout period as an equalization timeout period in the target phase, wherein N rate thresholds are predetermined, N is an integer greater than or equal to 0, and a longer rate threshold interval corresponds to a longer equalization timeout period, wherein equalization training in the target phase is performed on the downstream port and the upstream port within the equalization timeout period in the target phase.
9. A chip, comprising: a register, configured to store a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods; a transceiver, configured to obtain a training rate of each of a master chip and a slave chip in a target phase of equalization training, wherein the target phase is a third phase or a fourth phase of phases of the equalization training; and a manager, configured to: determine a target rate threshold interval within which the training rate in the target phase falls, determine, based on the correspondence between the N+1 rate threshold intervals and the N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configure the target equalization timeout period as an equalization timeout period in the target phase, wherein N rate thresholds are predetermined, N is an integer greater than or equal to 0, and a longer rate threshold interval corresponds to a longer equalization timeout period, wherein equalization training in the target phase is performed on the master chip and the slave chip within the equalization timeout period in the target phase.
12. (Currently Amended) A communications system, comprising: a processing system configured to execute a system software stored in a memory of the communications system; a upstream port; a upstream port; wherein the downstream port and the upstream port are connected to each other through a peripheral component interconnect express (PCIe) bus or a cache coherent interconnect for accelerators (CCIX) bus; and wherein the processing system accesses the system software in the memory and executes the system software to configure the processing system communications system to: obtain a training rate of each of a downstream port and a upstream port in a target phase of equalization training, wherein the target phase is a third phase or a fourth phase; and determine a target rate threshold interval within which the training rate in the target phase falls, determine, based on a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configure the target equalization timeout period as an equalization timeout period in the target phase, wherein N rate thresholds are predetermined, N is an integer greater than or equal to 0, and a longer rate threshold interval corresponds to a longer equalization timeout period, wherein equalization training in the target phase is performed on the downstream port and the upstream port within the equalization timeout period in the target phase.
12. A communications system, comprising: a processing system configured to execute system software; a master chip; a slave chip; wherein the master chip and the slave chip are connected to each other through a peripheral component interconnect express (PCIe) bus or a cache coherent interconnect for accelerators (CCIX) bus; and wherein the processing system executes the system software to configured the processing system to: obtain a training rate of each of a master chip and a slave chip in a target phase of equalization training, wherein the target phase is a third phase or a fourth phase of phases of the equalization training; and determine a target rate threshold interval within which the training rate in the target phase falls, determine, based on a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configure the target equalization timeout period as an equalization timeout period in the target phase, wherein N rate thresholds are predetermined, N is an integer greater than or equal to 0, and a longer rate threshold interval corresponds to a longer equalization timeout period, wherein equalization training in the target phase is performed on the master chip and the slave chip within the equalization timeout period in the target phase.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.A.D/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184