DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/21/24 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Akhavan et al. (US 11,569,837).
With regard to claim 1 Akhavan discloses:
A pipeline analog to digital converter (ADC) comprising: a first stage of a "k" number of stages (Fig. 4), wherein the first stage is configured to:receive an analog differential input signal; produce a first digital output based on the analog differential input signal; and produce a first single ended analog output (402 Fig.4) based on the analog differential input signal; a second stage (410 Fg.4) of the "k" number of stages, wherein the second stage is configured to: receive the first single ended analog output; and produce a second digital output based on the first single ended analog output; and an output data register (420 Fig. 4) that is configured to generate an output digital value based on the first digital output and the second digital output. (the pipelined ADC 400 may also include a digital combiner 420 for combining the output(s) of the one or more stages and the digital residue from the ADC 410 and generating the digital output (labeled "Dout"). Although illustrated as a differential pipelined ADC, the ADC 400 may alternatively be implemented as a single-ended pipelined ADC).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2, 3, 15, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Akhavan (US 11,569,837) in view of Signell (US 6,028,546).
With regard to claim 2, Akhavan fails to teach:
The pipeline ADC of claim 1, wherein when the "k" number of stages includes a third stage, the second stage is further configured to produce a second single ended analog output.
Signell discloses a multiple stages analog to digital converter that notably comprises a third stage coupled to a second stage. Therefore, anyone having ordinary skill in the art before the effective filing date of the application would have been motivated to use the teaching of Signell in the pipeline analog to digital converter of for the benefit to increase the resolution of the converter.
With regard to claim 3, Akhavan fails to teach:
The pipeline ADC of claim 1, wherein the first stage comprises: a differential input sample and hold circuit; an analog to digital converter (ADC); and a residual analog output circuit.
Signell discloses in Figure 7 a differential operation of a pipeline analog to digital converter that comprises that comprises a differential sample and hold circuit and a residual analog signal. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have applied the teachings of Signell in the pipeline converter of Akhavan for the benefit to increase performance of the pipeline of the analog to digital converter.
With regard to claim 15, Akhavan fails to teach:
The pipeline ADC of claim 1, wherein the second stage comprises: a single ended input sample and hold circuit; and a second ADC.
Signell discloses this limitation (see Figs 1 and 7). Single ended input devices are well known in the art to ensure the compatibility of the converter being powered.
With regard to claim 16 Akhavan fails to teach
The pipeline ADC of claim 15, wherein when the second stage is not a final stage of
the "k" number of stages, the second stage further comprises: a second residual
analog output circuit.
Signell discloses this limitation (see Figs. 1 and 7). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have applied the teachings of Signell in the pipeline converter of Akhavan for the benefit to increase performance of the pipeline of the analog to digital converter.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Akhavan in
view of Cesura et al. (US 2009/0102688).
With regard to claim 19 Akhavan fails to teach:
The pipeline ADC of claim 1, wherein the first stage comprises: a pseudo differential
input sample and hold circuit; an analog to digital converter (ADC); and a residual
analog output circuit.
Cesura discloses
a pipeline analog to digital converter whose first sequence of samples is a
pseudorandom sequence of samples (abstract: a sampling circuit inputting the
signal and outputting a first sequence of analog samples; a generation block of a
pseudorandom sequence of samples). Therefore, it would have been obvious to one
having ordinary skill in the art before the effective filing date of the application to have
applied the teachings of Cesura in the pipeline converter of Akhavan so that the error
to be corrected in the converter is modulated by the sequence.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 19 is further rejected on the ground of nonstatutory double patenting as being unpatentable over claim 19 of U.S. Patent No. 12,107,594) in view of Buter (US 8,362,939).
For instance,
Claim 19 of the patent application recites:
A pipeline analog to digital converter (ADC) comprising: a first stage of a "k" number of stages, wherein the first stage is configured to receive an analog differential input signal and produce a first digital output and a first single ended analog output, and wherein the first stage includes a pseudo differential input sample and hold circuit comprising: a sampling capacitor operable to sample the analog differential input signal to produce a sampled analog differential input signal; a charge subtraction capacitor operable to subtract a charge from the sampled analog differential input signal to produce a subtracted sampled analog differential input signal; and an operational amplifier operable to generate a single ended voltage signal based on a voltage difference between the subtracted sampled analog differential input signal and a common voltage, wherein the single ended voltage signal is output on a single ended output line of the operational amplifier; a second stage of the "k" number of stages configured to receive the first single ended analog output and produce a second digital output; and an output data register configured to generate an output digital value based on the first digital output and the second digital output.
However, claim 19 of the application fails to recite “a feedback capacitor”.
The application is the same as the recitation of claim 19 of the patent except for a feedback capacitor,
Butler discloses a pipeline analog to digital converter (Fig. 1) that comprises an amplifier that comprises a feedback capacitor (col. 7, lines 25-30). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention presented with the teaching of Buter to implement a feedback capacitor in the present application for, among other benefits, to maintain the stability of the device and further preventing the amplification of unwanted signal.
Allowable Subject Matter
Claims 4-14, 17-18 and 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEGUY JEAN PIERRE whose telephone number is (571) 272-1803. The examiner can normally be reached from 8:00-6:30 PM Monday-Thursday. The examiner’s fax phone number is (571) 273-1803. The Examiner email address is peguy.jeanpierre@uspto.gov. If attempts to reach the Examiner are unsuccessful, the Examiner’s supervisor Dameon E. Levi can be reached at (571) 272-2105.
/PEGUY JEAN PIERRE/Primary Examiner, Art Unit 2845