DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Republic of Korea on 5/22/2024. It is noted, however, that applicant has not filed a certified copy of the Korea application as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Cagno et al (U.S. 2010/0011261), and in view of Zhong et al (U.S. 2013/0232289), hereinafter Cagno.
Regarding claim 1:
An apparatus for diagnosing a memory, the apparatus comprising: a memory; and a processor configured to write data to the memory or erase data written to the memory, Cagno taches a method and system (Fig. 7 and corresponding text) to perform diagnostic on non-volatile memory (Fig. 3, controller 312, non-volatile memory 338).
wherein the processor is configured to diagnose a deterioration of the memory based on one or more of an erase count of the data written to the memory, [an erase time required to erase the data written to the memory, and a write error count when writing data to the memory]. Cagno, ¶0060, the controller determine whether the non-volatile memory is close to reaching its lifetime (highly deteriorated), based on programming cycles counter.
However, Cagno does not teach diagnose a deterioration of the memory based on one or more of an erase count of the data written to the memory, an erase time required to erase the data written to the memory, and a write error count when writing data to the memory.
In an analogous art of storage management, Zhong teaches the idea of manage a solid-state storage media, according to health metrics of the solid-state storage media. The metric maybe used to predict the reliability or remaining useful life of the solid-state storage media. A health metric may be based on one or more of: performance characteristics of the storage section, such as program time (e.g., the time required to program data to the storage section), erase time (e.g., the time required to erase data from the storage section), read time (e.g., the time required to perform read operations on the storage section), error rates, including, but not limited to the reliability metric(s) disclosed above, wear level (e.g., PE count, PE ratio, or the lie), ¶0043.
Because both Cagno and Zhong concern about to storage reliability. Zhong further suggests that wear level is not always an accurate measure and/or estimate of the reliability and/or remaining useful life of the solid-state storage medium. One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Zhong into the teaching of Cagno to obtain the claimed limitations above. The motivation for doing so is to apply a known technique to the apparatus ready for improvement of Cagno to yield predictable results, which provides more accurate prediction lifespan of the solid-state storage device.
Regarding claim 11:
The apparatus of claim 1, wherein the processor is configured to diagnose the deterioration of the memory by further considering a write time required to write the data to the memory. Zhong, ¶0043, suggests taking program time into consideration when predict or diagnose the deterioration of the memory.
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Cagno et al (U.S. 2010/0011261), hereinafter Cagno, and in view of Zhong et al (U.S. 2013/0232289), and further in view of Lakhani et al (U.S. 2004/0015674).
Regarding claim 14:
The apparatus of claim 1, wherein: the memory includes a flash memory, and when an error occurs when writing data to the flash memory, the processor unconditionally blocks subsequent writing of data to an address at which the error occurs. The combination of Cagno does not teach the claimed limitation above. However, in an analogous art of storage management, Lakhani teaches when an erase block becomes defective, flash memory controller replaces the defective block with another block, and disables access to the address of the defective block (¶0044). Both Lakhani and Cagno concern about data integrity. Thus, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Lakhani into the teaching of Cagno to obtain the claimed limitations above. The motivation is to apply a known technique to the apparatus ready for improvement of Cagno to yield predictable results, which prevents accessing bad block, or accessing same data block with two different addresses.
Regarding claim 15:
The apparatus of claim 1, wherein: the memory includes an electrically erasable programmable read-only memory (EEPROM),and when an error occurs when writing data to the EEPROM, the processor is allocated a spare address converted from an address at which the error occurs, and the processor performs a data write operation using the allocated spare address. The combination of Cagno does not teach the claimed limitations above. However, in an analogous art of storage management, Lakhani teaches a Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time (¶004). Lakhani further teaches when an erase block becomes defective, flash memory controller programs an undamaged block, replaces the defective block with the undamaged block, and disables access to the address of the defective block (¶0044). Lakhani does not explicitly teach allocates a spare address converted from an address at which the error occurs. However, the address conversion from old address to new address is a built-in function of the EEPROM. Both Lakhani and Cagno concern about data integrity. Thus, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Lakhani into the teaching of Cagno to obtain the claimed limitations above. The motivation is to apply a known technique to the apparatus ready for improvement of Cagno to yield predictable results, which prevents accessing bad block, or accessing same data block with two different addresses.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Cagno et al (U.S. 2010/0011261), hereinafter Cagno, and in view of Zhong et al (U.S. 2013/0232289), and further in view of Eisner et al (U.S. 10,599,753).
Regarding claim 16:
The apparatus of claim 1, wherein the processor transmit a deterioration diagnosis result for the memory to an external device only when a currently received request for transmission of diagnostic information is authenticated by a predefined authentication key. The combination of Cagno does not teach the claimed limitations above. In a same field of endeavor, Eisner discloses a computer system comprises a front-end system which may perform authentication of a customer, user, before granting access to data, or enables the customer to execute applications, receives the results of the execution, and transmit the results to the user (7:5-40). One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Eisner into the teaching of Cagno to obtain the claimed limitations above. The motivation is to apply a known work in one field of endeavor (computing system of Eisner) to prompt variations of it for use in a same field of computing of Cagno to yield predictable variations and results.
Allowable Subject Matter
Claims 17-20 are allowed.
Claims 2-10, 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
The prior art of record teaches a storage controller diagnoses a deterioration of a memory based on an erase count of data written to the memory cell, an erase time required to erase the data written to the memory cell, a write error count when writing the data to the memory cell, write time required to write data to the memory cells.
However, the prior art of record does not teach a controller, which is different from the storage controller, controls an operation of the memory, and determine an operating state according to a control result, and identifies the deterioration of the memory based on the result of determining the operating state of the memory, or an interrupt generated by the storage controller.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chou et al (U.S. 2021/0126946) teaches an integrated circuit (IC) system comprising a memory array having a plurality of memory cells, a crypto subsystem for performing encryption and decryption, and a processor, coupled with the memory array and crypto subsystem. The processor is configured to receive encrypted diagnostic data from the crypto subsystem and communicate such encrypted diagnostic data to a remote server while the IC is embedded in an end-user system. The encrypted diagnostic data pertains to the health of the memory cells of the memory array
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/KHOA D DOAN/ Primary Examiner, Art Unit 2133