Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 4 and 16 have been canceled.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant's arguments filed 02/25/2026 regarding the prior art rejections of Claims 1 – 20 have been fully considered, but they are not persuasive.
The Remarks argue that:
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Colgrove (US 2012/0079318 Al) in view of Yang (TW 1658364 B). Applicant respectfully traverses the rejection for at least the following reasons.
Independent claim 1 has been amended to recite:
A data protection method, comprising: partitioning first to-be-protected data obtained by a chip, to obtain a plurality of first subdata;
performing a predetermined check operation based on the plurality of first subdata, to obtain first check code corresponding to the first to-be-protected data, wherein the predetermined check operation is used for obtaining check code with a preset data
volume for to-be-checked data with any data volume;
determining first data protection reference information associated with the first check code; and
storing the first to-be-protected data and the first data protection reference information into an on-chip memory of the chip,
wherein the performing a predetermined check operation based on the plurality of first subdata, to obtain first check code corresponding to the first to-be-protected data
comprises:
determining a first bus bit width corresponding to a first module in the chip that generates the first to-be-protected
data;
in response to that a sum of data volumes of the plurality of first subdata is a non-integer multiple of the first bus bit width, updating the plurality of first subdata according to a first preset data padding rule, to obtain a plurality of third subdata of which a sum of data volumes is an integer multiple of the
first bus bit width; and
performing a predetermined check operation based on the plurality of third subdata, to obtain the first check code
corresponding to the first to-be-protected data.
(Emphasis added).
Colgrove is directed to a system and method for adaptive RAID geometries. Colgrove
teaches that a data storage subsystem comprises a storage controller configured to determine a first RAID layout for use in storing data, and write a first RAID stripe to the device group according to the first RAID layout. In response to detecting a first condition, the controller is configured to determine a second RAID layout which is different from the first RAID layout, and write a second RAID stripe to the device group according to the second layout. Colgrove teaches that the data is protected by parity at the RAID level.
It can be seen that Colgrove discloses dynamically adjusting the RAID layout to modify the composition of RAID stripes, writing data into the adjusted RAID stripes for storage, and protecting the data through RAID-level parity. That is, the partitioning object in Colgrove is the hardware storage space. The purpose of partitioning the hardware storaqe space is to adapt to the core design for SSD environments. Through dynamic allocation of storage units, partition management, and multi-level error protection, flexible adjustment of RAID is achieved, ultimately enhancing system reliability, performance, and lifespan. However, according to the present disclosure, the to-be-protected data is partitioned. Therefore, the partitioning object is the to-be-protected data. The purpose of partitioning the to-be- protected data is to obtain check code with a preset data volume through a check operation, thereby solvinq the problem of linear growth of check code with data volume, and reducinq the storage space and transmission bandwidth that need to be occupied for implementing data protection. Consequently, the partitioning object and purpose of Colgrove are entirely different from those of the present disclosure. Moreover, when storing and protecting user data, the solution in Colgrove protects the data through parity check, and it does not involve solutions such as bus bit width and padding rules. In contrast, after partitioning the data, this present disclosure further performs data padding in combination with the bus bit width of the first module to ensure that the check operation adapts to the chip's hardware computing capability. This is a technical effect that the solution in Colgrove cannot achieve.
Therefore, Colgrove at least does not disclose the following features of amended claim 1:
partitioning first to-be-protected data obtained by a chip, to obtain a plurality of first subdata;
performing a predetermined check operation based on the plurality of first sub-data, to obtain first check code corresponding to the first to-be-protected data, wherein the predetermined check operation is used for obtaining check code with a preset data
volume for to-be-checked data with any data volume;
determining first data protection reference information associated with the first check code; and
storing the first to-be-protected data and the first data protection reference in-formation into an on-chip memory of the
chip,
wherein the performing a predetermined check operation based on the plurality of first subdata, to obtain first check code
corresponding to the first to-be-protected data comprises:
determining a first bus bit width corresponding to a first module in the chip that generates the first to-be-protected data;
in response to that a sum of data volumes of the plurality of first subdata is a non-integer multiple of the first bus bit width, updating the plurality of first subdata according to a first preset data padding rule, to obtain a plurality of third subdata of which a sum of data
volumes is an integer multiple of the first bus bit width; and
performing a predetermined check operation based on the plurality of third subdata, to obtain the first check code
corresponding to the first to-be-protected data.
Regarding the above distinguishing technical features, first, the application scenario of Colgrove is RAID management in storage systems, while the application scenario of the present disclosure is protection for internal chip data register access. Therefore, the application scenarios of Colgrove and the present disclosure are different. The technical problem addressed by Colgrove is: how to dynamically adjust RAID layouts in a storage array composed of solid-state drives (SSDs) to adapt to different characteristics of SSDs (such as error rates, lifespan) and protect data. To solve this technical problem, Colgrove discloses partitioning hardware storage devices, writing data into each partition, and using parity to protect data within each partition, thereby achieving storage and protection of user data. In contrast, the technical problem addressed by the present disclosure is: how to solve the issue where the check code increases linearly with the data volume, so as to reduce the storage space and transmission bandwidth required for implementing data protection. To
solve this technical problem, the present disclosure requires partitioning the first to-be-protected data into a plurality of first subdata, and processing them based on a predetermined check operation to obtain a first check code with a fixed data volume. That is, in the solution of the present disclosure, regardless of the data volume of the first to-be-protected data, the size of the generated first check code is fixed. As shown in Fig. 2, which is reproduced below for convenience, by adopting the technical solution of the present disclosure, the larger the data volume of the to-be-protected data, the lower the data expansion rate, which can more significantly reduce the amount of data stored in the on-chip memory, thereby reducing the storage space and transmission bandwidth required for implementing data protection.
Clearly, Colgrove addresses the problem of data storage and protection based on dynamically adjusting RAID layouts. In contrast, the present disclosure solves the problem of check codes increasing linearly with data volume. Therefore, the application scenarios, technical problems addressed, and the technical solutions adopted are different between Colgrove and the present disclosure.
Second, paragraph [0113] and FIG. 12 of the specification of Colgrove disclose that each partition includes multiple storage devices. It can be seen that the partitioning object in Colgrove is hardware, with each partition containing multiple storage devices, the purpose being to dynamically adjust RAID layouts, i.e., to partition physical hardware resources, not for parity check. In the present disclosure, however, the partitioning object is the to- be-protected data itself. By partitioning the to-be-protected data into a plurality of first subdata, it is possible to obtain a check code of a fixed size even when the data volume of the to-be-protected data is large. That is, the partitioning object in the present disclosure is the to-be-protected data itself, and the purpose of data partitioning is to perform a predetermined check operation to obtain a check code of a fixed data volume.
According to the present disclosure, if it is assumed that the plurality of first subdata are Rfirst subdata, which are respectively represented as data1, data2, data3 .., dataR-1, and dataR
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32-bit CRC1 may be obtained based on the data1 and the CRC initial value through a cyclic redundancy check operation; and then, 32-bit CRC2 may be obtained based on the data2 and the CRC1 through a cyclic redundancy check operation; subsequently, 32-bit CRC3 may be obtained based on the data3 and the CRC2 through a cyclic redundancy check operation; ...; and finally, 32-bit CRCR may be obtained based on the dataR and CRCR-1 through a cyclic redundancy check operation. The 32-bit CRCR may be used as the first check code corresponding to the first to-be- protected data. Therefore, the present disclosure, through data partitioning, enables obtaining a check code of a fixed data volume during the check operation, ensuring that the check code does not increase linearly with the data volume of the to-be-protected data; moreover, the larger the data volume of the to-be-protected data, the lower the data expansion rate.
Consequently, the object, method, result, and partitioning purpose in the amended claim 1 are all different from those in Colgrove.
Furthermore, according to paragraph [0099] of Colgrove, it is known that parity check is performed on data to protect page checksums within data pages. Parity check does not require limiting the size of the checksum, and the checksum varies with the RAID layout. Therefore, the data volume of the checksum in Colgrove is not fixed but related to the RAID layout, which may potentially occupy significant storage space and bandwidth. In contrast, in the present disclosure, the first check code obtained is of a fixed size, solving the problem of the data volume of the first check code continuously expanding as the data volume of the first to-be-protected data increases, thereby reducing storage space and bandwidth requirements. Moreover, Colgrove does not disclose the technical solution of padding the to-be-protected data according to the bus bit width; instead, it directly performs parity check on the data. The present disclosure considers that the data volume of the first to-be-protected data is random, while hardware generally has difficulty supporting predetermined check operations of any length through parameterized configuration. Therefore, based on the first bus bit width corresponding to the first module, data padding can be performed on the plurality of first subdata to obtain a plurality of third subdata whose total bit width is an integer multiple of the first bus bit width. This facilitates performinq the predetermined check operation on the plurality of third subdata to obtain a first check code of a fixed data volume. Hence, the present disclosure can ensure that the check operation adapts to the hardware computational capabilities of the chip to generate a check code of a fixed data volume.
Yang discloses a method for accessing a flash memory module, which performs a cyclic redundancy check operation on the data to generate a cyclic redundancy check code; before the data is written to a buffer memory of the flash memory controller, an encoding operation is performed on the metadata and the cyclic redundancy check code to generate an adjusted check code, wherein the byte count of the adjusted check code is the same as the byte count of the metadata, and the adjusted check code containing the metadata and the cyclic redundancy check code provides protection for the data and the metadata; an encoding operation is performed on the data and the adjusted check code together to generate encoded data, wherein the encoded data includes the data, the adjusted check code, and an error correction code corresponding to the data and the adjusted check code; and the encoded data and the metadata are written to a data page within a block of the flash memory module.
Regarding the aforementioned distinguishing technical features, first, the application scenario of Yang is to protect metadata of a flash memory, while the application scenario of the present disclosure is to protect internal chip data register access. That is, the application scenarios of Yang and the present disclosure are different.
Second, according to paragraph [0020] and Figure 7 (the schematic diagram of metadata partitioning principle) of Yang, it can be seen that although Yang partitions the metadata, the purpose of partitioning the metadata is to allow the obtained sub-metadata to match the corresponding data, not for performing a check operation on the metadata. In contrast, in the present disclosure, partitioning the first to-be-protected data is to perform a predetermined check operation on the obtained plurality of first subdata to obtain a first check code of a fixed size. That is, the purpose of partitioning the first to-be-protected data in the present disclosure is to perform a predetermined check operation. Therefore, the purpose of partitioning the metadata in Yang is different from the purpose of partitioning the first to- be-protected data in the present disclosure.
Third, when generating the check code in Yang, each sub-metadata independently undergoes an XOR operation with the corresponding cyclic redundancy check (CRC) code, with each sub-metadata corresponding to an adjusted check code. Therefore, when generating the check code in Yang, a check code is generated for each sub-metadata, and the check codes of the multiple sub-metadata together constitute the check code for the metadata. In contrast, when generating the check code for the to-be-protected data in the present disclosure, a final check code of a fixed length is generated. The data volume of this check code is independent of the number of subdata into which the to-be-protected data is partitioned and independent of the size of the data volume of the to-be-protected data itself. Therefore, unlike Yang, the present disclosure can generate a fixed-size check code regardless of the data volume of the to-be-protected data, thereby reducing storage space and bandwidth. The solution of Yang cannot achieve this technical effect.
Finally, Yang does not disclose the technical solution of padding data based on the bus bit width. Instead, it directly performs XOR operations on the sub-metadata without any padding processing, nor does it judge the multiple relationship between the sum of the data volumes of the sub-metadata and the bus bit width of the hardware module. Moreover, Yang does not perform padding on the data; it directly performs cyclic redundancy calculation on the data. In contrast, the present disclosure can perform data padding based on the first bus bit width of the first module that acquires the to-be-protected data and the first preset data padding rule, thereby ensuring that the check operation is adapted to the chip's hardware computational capabilities to generate a check code with a fixed data volume. This is also a technical effect that Yang cannot achieve.
In summary, the present disclosure not only adapts to the hardware architecture but also reduces the storage space and transmission bandwidth required to implement data protection. This is a technical effect that cannot be achieved by Yang.
Post (US2011/0213945 A1), which is of record and not relied on in the current Office Action, discloses systems and methods for partitioning data for storage in a non-volatile memory ("NVM") such as flash memory. In one embodiment, a priority may be assigned to stored data, and the data may be logically partitioned based on that priority. For example, a file system may determine a logical address within a first predetermined range for storing high-priority data and within a second predetermined range for storing low-priority data, such as by using a union file system.
Using the logical address, an NVM driver may determine the priority of the data to be stored and may process (e.g., encode) the data according to the priority. The NVM driver may store an identifier along with the data in the NVM, which may indicate the processing technique used for the associated data.
It can be seen that Post only discloses partitioning data based on priority, but does not disclose the technical solutions of processing data based on bus bit width and padding rules, and obtaining a check code for the processed data based on a predetermined check operation.
In summary, the technical solution claimed by amended claim 1 cannot be derived from Colgrove, Yang, and Post, nor is there any technical suggestion provided to solve the technical problem actually addressed by the technical solution of amended claim 1. Therefore, the technical solution claimed by amended claim 1 would not have been obvious to a person ordinary skilled in the art.
Independent Claims 13 and 20
The reasoning concerning the inventive step of claim 1 applies, mutatis mutandis, to the corresponding claims 13 and 20 the subject matter of which is therefore also non-obvious over Colgrove, Yang, and Post.
Dependent Claims
The remaining claims are non-obvious over Colgrove, Yang, and Post, at least because claims 1 and 13, from which these claims depend, are non-obvious as discussed above.
It is believed that all of the stated grounds of rejection have been properly traversed, accommodated, or rendered moot. Applicant therefore respectfully requests that the Office reconsider and withdraw all presently outstanding rejections. It is believed that a full and complete response has been made to the outstanding Office Action and that the present application is in condition for allowance. Thus, prompt and favourable consideration of this response is respectfully requested.
The Examiner agrees the partitioning object and purpose of Colgrove are entirely different from those of the present disclosure. Colgrove protects the data through parity check, and it does not explicitly involve solutions such as bus bit width and padding rules. However, Cologrove does teach the partitioning of the to-be-protected data, bus size, and data padding. (0093-0094 & 0108, Device Layout I/O shard size--This represents the size used to stripe across each device during a write. This will typically be in the range of 256 KB to 1 MB and probably be a multiple of the erase block size on each device. FIG. 11B calls out I/O shard size 1125 for purposes of illustration. [0094] (3) I/O read size--This is a logical read size. Each I/O shard may be formatted as a series of logical pages. Each page may in turn include a header and a checksum for the data in the page. When a read is issued it will be for one or more logical pages and the data in each page may be validated with the checksum. In order to align data 1144 in a given page in storage device 176j with data 1142 in a corresponding page in one or more of the storage devices 176a-176i, padding 1146 may be added to the corresponding pages.) Cologrove does teach parity checks. (0055, Other examples of intra-device redundancy schemes include single parity check (SPC), maximum distance separable (MDS) erasure codes, interleaved parity check codes (IPC), hybrid SPC and MDS code (MDS+SPC), and column diagonal parity (CDP).) Although the application of Cologrove is different from the presented application, they both function the same with CRC and ECC operations aiming for better efficiency and reliability.
The Examiner agrees the application scenarios of Yang and the present disclosure are different. However, Yang still teaches the same functions of partitioning data, check operations, and fixed size of check codes. (Fig. 2 and corresponding specification, In this embodiment, referring to FIG. 3, the size of the first piece of data is 4 kilobytes (KB) and the size of the metadata is 8 bytes. In the following operations of this embodiment, the first piece of data is. The data is divided into eight parts D1 to D8 with a size of 512 bytes, and the metadata is divided into four parts M1 to M4 with a size of 2 bytes. In step 204, the first codec 132 performs a cyclic redundancy check operation on the first piece of data to generate a cyclic redundancy check code, and in step 206 the second codec 134 combines the metadata with the cycle. The ring redundancy check code is encoded to generate an adjusted check code. Specifically, referring to FIG. 4, the first codec 132 first performs a cyclic redundancy check operation on the eight parts D1 to D8 of the first piece of data to generate multiple cyclic redundancy check codes P1 to P8. Where the size of each cyclic redundancy check code P1 ~ P8 is 2 bytes;)
The Examiner agrees Yang does not disclose the technical solution of padding data based on the bus bit width.
Cologrove and Yang do not teach the claimed invention individually. However, these prior arts in combination with the teachings of Srinivasan, one skilled in the art could conclude the claimed invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Colgrove (US 2012/0079318 A1 in view of Yang (TW I658364 B) in view of Srinivasan (US 11500719 B1). Claims 4 & 16 have been canceled.
In regards to claim 1, Colgrove teaches:
A data protection method, comprising: partitioning first to-be-protected data obtained by a chip, to obtain a plurality of first subdata (0113, Three partitions are shown although any number of partitions may be chosen. Each partition may correspond to a separate device group; Each partition may correspond to a separate device group); wherein the predetermined check operation is used for obtaining check code with a preset data volume for to-be-checked data with any data volume; determining first data protection reference information associated with the first check code (0098, FIG. 11B also depicts segment tail data which identifies any (volume, snapshot) combinations that take up a significant amount of space in the segment. an object storage model may be used where each node may have a segment table that can take a logical reference and identify the segment layout node where the data is stored); and storing the first to-be-protected data and the first data protection reference information into an on-chip memory of the chip (0048, As used herein, characteristics of a device may refer to characteristics of the device as a whole, characteristics of a sub-portion of a device such as a chip or other component). in response to that a sum of data volumes of the plurality of first subdata is a non-integer multiple of the first bus bit width, updating the plurality of first subdata according to a first preset data paddinq rule, to obtain a plurality of third subdata of which a sum of data volumes is an inteqer multiple of the first bus bit width; (0108, the data 1144 is a checksum value generated from one or more other checksum values 1142 stored in other storage devices. In order to align data 1144 in a given page in storage device 176j with data 1142 in a corresponding page in one or more of the storage devices 176a-176i, padding 1146 may be added to the corresponding pages.)
Colgrove fails to teach:
performing a predetermined check operation based on the plurality of first subdata, to obtain first check code corresponding to the first to-be-protected data; and performing a predetermined check operation based on the plurality of third subdata, to obtain the first check code corresponding to the first to-be-protected data.
However, Yang teaches:
performing a predetermined check operation based on the plurality of first subdata, to obtain first check code corresponding to the first to-be-protected data (Claims ¶ 1, performing a cyclic redundancy check (CRC) on the data) Operation to generate a cyclic redundancy check code); and performing a predetermined check operation based on the plurality of third subdata, to obtain the first check code corresponding to the first to-be-protected data. (YANGABSTRACT, performing a cyclic redundancy check operation on the data to generate A cyclic redundancy check code);
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the method of Colgrove which teaches A data protection method with the teaching of Yang which teaches a predetermined check operation based on the plurality of first subdata, to obtain check codes in order to access a flash memory (Yang: Claims ¶ 1, A method for accessing a flash memory module includes: receiving a data from a host device and a metadata corresponding to the data; and performing a cyclic redundancy check (CRC) on the data ) Operation to generate a cyclic redundancy check code).
Colgrove in view of Yang fails to teach:
wherein the performing a predetermined check operation based on the plurality of first subdata, to obtain first check code corresponding to the first to-be-protected data comprises: determining a first bus bit width corresponding to a first module in the chip that generates the first to-be-protected data;
However, Srinivasan teaches:
wherein the performing a predetermined check operation based on the plurality of first subdata, to obtain first check code corresponding to the first to-be-protected data comprises: determining a first bus bit width corresponding to a first module in the chip that generates the first to-be-protected data; (56, depending on the size of the grouping of data bits, the data bus width of the system, and whether the error correction code is stored contiguous with the protected data, the set of data bits and the corresponding error correction code can be read in one read operation.)
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the method of Colgrove which teaches A data protection method with the teaching of Srinivasan which teaches the reliability of a memory system, data and error correction codes associated with the data can be stored in a first memory in order to increase reliability. (Srinivasan: 15, To increase the reliability of a memory device, additional parity protection can be employed together with ECC).
In regards to claim 2, Colgrove in view of Yang teaches the method according to claim 1.
Colgrove teaches:
wherein the performing a predetermined check operation based on the plurality of first subdata, to obtain first check code corresponding to the first to-be-protected data comprises: performing position flipping on the plurality of first subdata respectively, to obtain a plurality of second subdata; performing cyclic redundancy check operations on the plurality of second subdata by using a preset first cyclic redundancy polynomial, to obtain the first check code corresponding to the first to-be-protected data; and the determining first data protection reference information associated with the first check code comprises: performing position flipping on the first check code to obtain second check code; and determining the first data protection reference information based on the second check code (0055, When the information is read back from the device, the system may calculate the checksum again and compare it to the value that was stored originally. Examples of checksum functions include cyclical redundancy check (CRC); An XOR-based operation may be used to derive parity information to store in the intra-device redundancy data 220).
In regards to claim 3, Colgrove in view of Yang teaches the method according to claim 1.
Colgrove teaches:
wherein the performing a predetermined check operation based on the plurality of first subdata, to obtain first check code corresponding to the first to-be-protected data comprises: performing position flipping on a preset first cyclic redundancy polynomial to obtain a second cyclic redundancy polynomial; and performing cyclic redundancy check operations on the plurality of first subdata by using the second cyclic redundancy polynomial, to obtain the first check code corresponding to the first to-be-protected data (0055, When the information is read back from the device, the system may calculate the checksum again and compare it to the value that was stored originally. Examples of checksum functions include cyclical redundancy check (CRC); An XOR-based operation may be used to derive parity information to store in the intra-device redundancy data 220).
In regards to claim 4, the claim has been canceled.
In regards to claim 5, Colgrove in view of Yang teaches the method according to claim 1.
Colgrove teaches:
determining second data protection reference information associated with the third check code; and performing a preset data protection operation on the first to-be-protected data based on the first data protection reference information and the second data protection reference information (0098, an object storage model may be used where each node may have a segment table that can take a logical reference and identify the segment layout node where the data is stored;).
Colgrove fails to teach:
further comprising: reading the on-chip memory to obtain a plurality of fourth subdata associated with the first to-be-protected data; performing the predetermined check operation based on the plurality of fourth subdata, to obtain third check code corresponding to the first to-be-protected data; determining second data protection reference information associated with the third check code;
However, Yang teaches:
further comprising: reading the on-chip memory to obtain a plurality of fourth subdata associated with the first to-be-protected data; performing the predetermined check operation based on the plurality of fourth subdata, to obtain third check code corresponding to the first to-be-protected data (Claims ¶ 1 & Fig. 1 and corresponding specification, performing a cyclic redundancy check (CRC) on the data ) Operation to generate a cyclic redundancy check code; the flash memory module 120 includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks, and the controller);
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the method of Colgrove which teaches A data protection method with the teaching of Yang which teaches a predetermined check operation based on the plurality of first subdata, to obtain check codes in order to access a flash memory (Yang: Claims ¶ 1, A method for accessing a flash memory module includes: receiving a data from a host device and a metadata corresponding to the data; and performing a cyclic redundancy check (CRC) on the data ) Operation to generate a cyclic redundancy check code).
In regards to claim 6, Colgrove in view of Yang teaches the method according to claim 5.
Colgrove teaches:
wherein the storing the first to-be-protected data into an on-chip memory of the chip comprises: updating the first to-be-protected data according to a second preset data padding rule, to obtain updated data of which a data volume is an integer multiple of the first bus bit width; and storing the updated data comprising the first to-be-protected data into the on-chip memory of the chip (0048 & 0060, a device may refer to characteristics of the device as a whole, characteristics of a sub-portion of a device such as a chip; the width for the corresponding data being written is the same within each storage device. In block 308, the intra-device protection data is generated by an ECC algorithm, an XOR-based algorithm, or any other suitable algorithm. In addition, the system may generate a checksum to help identify data that has not been retrieved properly. In block 310, the generated intra-device protection data is written in the second amount of space in the storage devices).
In regards to claim 7, Colgrove in view of Yang teaches the method according to claim 6.
Colgrove teaches:
wherein the method further comprises: recording a target data volume of the first to-be-protected data; and the reading the on-chip memory to obtain a plurality of fourth subdata associated with the first to-be-protected data comprises: determining a second bus bit width corresponding to a second module in the chip that is to use the first to-be-protected data; and reading the updated data in the on-chip memory based on the second bus bit width, until a plurality of fourth subdata of which a sum of data volumes is greater than or equal to the target data volume are obtained (0060 & 0098, the width for the corresponding data being written is the same within each storage device. In block 308, the intra-device protection data is generated by an ECC algorithm, an XOR-based algorithm, or any other suitable algorithm. In addition, the system may generate a checksum to help identify data that has not been retrieved properly. In block 310, the generated intra-device protection data is written in the second amount of space in the storage devices. FIG. 11B also depicts segment tail data which identifies any (volume, snapshot) combinations that take up a significant amount of space in the segment).
In regards to claim 8, Colgrove in view of Yang teaches the method according to claim 7.
Colgrove teaches:
wherein the sum of the data volumes of the plurality of fourth subdata is greater than the target data volume; and the performing the predetermined check operation based on the plurality of fourth subdata, to obtain third check code corresponding to the first to-be-protected data comprises: determining valid subdata in a last one in the plurality of fourth subdata based on the target data volume and the second bus bit width; determining fifth subdata of which a data volume is the first bus bit width or the second bus bit width based on the valid subdata; and performing the predetermined check operation based on other fourth subdata except the last one in the plurality of fourth subdata and the fifth subdata, to obtain the third check code corresponding to the first to-be-protected data (0055 & 0060, In addition to the above described redundancy information, the system may be configured to calculate a checksum value for a region on the device. For example, a checksum may be calculated when information is written to the device. This checksum is stored by the system. When the information is read back from the device, the system may calculate the checksum again and compare it to the value that was stored originally. If the two checksums differ, the information was not read properly, and the system may use other schemes to recover the data. Examples of checksum functions include cyclical redundancy check (CRC) the width for the corresponding data being written is the same within each storage device. In block 308, the intra-device protection data is generated by an ECC algorithm, an XOR-based algorithm, or any other suitable algorithm. In addition, the system may generate a checksum to help identify data that has not been retrieved properly).
In regards to claim 9, Colgrove in view of Yang teaches the method according to claim 8.
Colgrove teaches:
wherein a first check calculation component supporting the first bus bit width and a second check calculation component supporting the second bus bit width are instantiated in the second module; and the performing the predetermined check operation based on the other fourth subdata except the last one in the plurality of fourth subdata and the fifth subdata, to obtain the third check code corresponding to the first to-be-protected data comprises (0055, the system may be configured to calculate a checksum value for a region on the device. For example, a checksum may be calculated when information is written to the device. This checksum is stored by the system. When the information is read back from the device, the system may calculate the checksum again and compare it to the value that was stored originally. If the two checksums differ, the information was not read properly, and the system may use other schemes to recover the data. Examples of checksum functions include cyclical redundancy check (CRC)): in response to that a data volume of the fifth subdata is the second bus bit width, performing the predetermined check operation by using the second check calculation component based on the other fourth subdata except the last one in the plurality of fourth subdata and the fifth subdata, to obtain the third check code corresponding to the first to-be-protected data; and in response to that the data volume of the fifth subdata is the first bus bit width, performing the predetermined check operation by using the second check calculation component based on the other fourth subdata except the last one in the plurality of fourth subdata, to obtain first intermediate check code, and performing the predetermined check operation by using the first check calculation component based on the fifth subdata and the first intermediate check code, to obtain the third check code corresponding to the first to-be-protected data (0098 & 0060, FIG. 11B also depicts segment tail data which identifies any (volume, snapshot) combinations that take up a significant amount of space in the segment. When snapshots are removed, a data scrubber may help identify segments for garbage collection based on this data. Referring again to FIG. 2, the width for the corresponding data being written is the same within each storage device. In block 308, the intra-device protection data is generated by an ECC algorithm, an XOR-based algorithm, or any other suitable algorithm. In addition, the system may generate a checksum to help identify data that has not been retrieved properly. In block 310, the generated intra-device protection data is written in the second amount of space in the storage devices).
In regards to claim 10, Colgrove in view of Yang teaches the method according to claim 8.
Colgrove teaches:
wherein the determining fifth subdata of which a data volume is the first bus bit width or the second bus bit width based on the valid subdata comprises: in response to that a data volume of the valid subdata is greater than the first bus bit width and is less than the second bus bit width, updating the valid subdata according to a first preset data padding rule, to obtain the fifth subdata of which the data volume is the second bus bit width; and in response to that the data volume of the valid subdata is less than the first bus bit width, updating the valid subdata according to the first preset data padding rule, to obtain the fifth subdata of which the data volume is the first bus bit width (0060, Referring again to FIG. 2, the width for the corresponding data being written is the same within each storage device. In block 308, the intra-device protection data is generated by an ECC algorithm, an XOR-based algorithm, or any other suitable algorithm. In addition, the system may generate a checksum to help identify data that has not been retrieved properly. In block 310, the generated intra-device protection data is written in the second amount of space in the storage devices).
In regards to claim 11, Colgrove in view of Yang teaches the method according to claim 5.
Colgrove teaches:
further comprising: reading the on-chip memory to obtain a plurality of sixth subdata associated with second to-be-protected data (0057, increases or decreases in a given level of data protection may occur on a selective basis); determining data priorities for the first to-be-protected data and the second to-be-protected data in response to that it is detected that the first to-be-protected data is to be used by the second module during a process in which the second module in the chip performs the predetermined check operation based on the plurality of sixth subdata (0055, In addition to the above described redundancy information, the system may be configured to calculate a checksum value for a region on the device. For example, a checksum may be calculated when information is written to the device. This checksum is stored by the system. When the information is read back from the device, the system may calculate the checksum again and compare it to the value that was stored originally. If the two checksums differ, the information was not read properly, and the system may use other schemes to recover the data); in response to that the data priority of the first to-be-protected data is higher than that of the second to-be-protected data, pausing the step of performing the predetermined check operation based on the plurality of sixth subdata, recording second intermediate check code obtained from the step of performing the predetermined check operation based on the plurality of sixth subdata, and performing the step of reading the on-chip memory to obtain a plurality of fourth subdata associated with the first to-be-protected data to the step of performing the preset data protection operation on the first to-be-protected data based on the first data protection reference information and the second data protection reference information; and in response to that the data priority of the first to-be-protected data is lower than that of the second to-be-protected data, continuing to perform the step of performing the predetermined check operation based on the plurality of sixth subdata (0098, Examples of checksum functions include cyclical redundancy check (CRC) an object storage model may be used where each node may have a segment table that can take a logical reference and identify the segment layout node where the data is stored).
In regards to claim 12, Colgrove in view of Yang teaches the method according to claim 5.
Colgrove teaches:
wherein the determining first data protection reference information associated with the first check code comprises: performing an XOR operation between the first check code and preset data, to obtain the first data protection reference information; and the determining second data protection reference information associated with the third check code comprises: performing an XOR operation between the third check code and the preset data, to obtain the second data protection reference information (0098 & 0060, an object storage model may be used where each node may have a segment table that can take a logical reference and identify the segment layout node where the data is stored. In block 308, the intra-device protection data is generated by an ECC algorithm, an XOR-based algorithm, or any other suitable algorithm. In addition, the system may generate a checksum to help identify data that has not been retrieved properly).
In regards to claim 13, Colgrove in view of Yang teaches the computer readable storage medium. The claim corresponds to claim 1 and analyzed accordingly.
In regards to claim 14, Colgrove in view of Yang teaches the non-transitory computer readable storage medium according to claim 13. The claim corresponds to claim 2 and analyzed accordingly.
In regards to claim 15, Colgrove in view of Yang teaches the non-transitory computer readable storage medium according to claim 13. The claim corresponds to claim 3 and analyzed accordingly.
In regards to claim 16, the claim corresponds to claim 4 and analyzed accordingly.
In regards to claim 17, Colgrove in view of Yang teaches the non-transitory computer readable storage medium according to claim 13. The claim corresponds to claim 5 and analyzed accordingly.
In regards to claim 18, Colgrove in view of Yang teaches the non-transitory computer readable storage medium according to claim 17. The claim corresponds to claim 6 and analyzed accordingly.
In regards to claim 19, Colgrove in view of Yang teaches the non-transitory computer readable storage medium according to claim 18. The claim corresponds to claim 7 and analyzed accordingly.
In regards to claim 20, Colgrove in view of Yang teaches the electronic device and the claim corresponds to claim 1 and analyzed accordingly.
Prior Art Made of Record
The prior art mode of record and not relied upon is considered pertinent to
Applicant’s disclosure:
Post (US 2011/0213945 A1): Systems and methods are disclosed for partitioning data for storage in a non-volatile memory ("NVM"), such as flash memory.
Conclusion
Applicant's arguments filed 02/25/2026 regarding the prior art rejections of Claims 1 – 20 have been fully considered, but they are not persuasive.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/V.P./Examiner, Art Unit 2111
/GUERRIER MERANT/Primary Examiner, Art Unit 2111 5/27/2026
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