DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claims 1-2 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xue et al. (Pub. No. US20220343146)
As per claim 1, Xue discloses a neural network accelerator (fig.1, computing device 140), comprising:
always-on circuitry (fig.1, accelerator 230) configured to determine pre-processed data (paragraph 31, data preprocessing);
buffer circuitry (fig.1, storage/memory 210) comprising a plurality of banks (fig.2, register bank 229) configured to store the determined pre-processed data (paragraph 33, the storage/memory 210 and temporarily store them in its on-chip memory for preprocessing the input data); and
processor circuitry (fig.2, processor 222) comprising a neural network model (paragraph 33, neural network models) and configured to perform power-gating (fig.1, scheduler 220), wherein the neural network model is configured to perform a neural network computation on the pre-processed data (paragraph 33, perform preprocessing of the input data to the models to accelerate the subsequent neural network computations).
As per claim 2, Xue discloses wherein the processor circuitry comprises a non-volatile memory (NVM) (paragraph 33, a processor executable non-volatile computer-readable storage medium).and one or more processor elements configured to perform power-gating on the NVM, and wherein the neural network computations are executed by the one or more processor elements with respect to the stored pre-processed data and parameters of the neural network stored in the NVM (paragraph 33, processors are implemented as part of the accelerators 230, the schedulers 220 may send the addresses of the parameters of the corresponding neural network model in storage/memory 210 to the accelerator 230 in the form of instructions).
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 3-20 are rejected under 35 U.S.C. 103 as being unpatentable over Xue et al. (Pub. No. US20220343146) in view of Ray et al. (Pub. No. US20240054595)
As per claim 3, Xue discloses wherein the processor circuitry comprises any one or any combination of any two or more of:
the one or more processor elements as respective one or more in-memory processor elements, within the NVM, configured to perform in-memory computing (IMC) (paragraph 33, processors are implemented as part of the accelerators 230, the schedulers 220 may send the addresses of the parameters of the corresponding neural network model in storage/memory 210 to the accelerator 230 in the form of instructions);
a first clock generator configured to generate a first clock for driving the NVM and the one or more processor elements (paragraph 45, a plurality of sets of input data collected across a plurality of timesteps); and
a power management unit (PMU) (paragraph 48, workflow 400 for accelerating temporal GNN computation) configured to provide a power voltage for the NVM, one or more processor elements, and the first clock generator (paragraph 18, performing calculation on these redundant data may result in poor performance and energy consumption spikes).
Xue discloses all the limitations as the above but does not explicitly disclose provide a power voltage for the NVM. However, Ray discloses this (paragraph 18, performing calculation on these redundant data may result in poor performance and energy consumption spikes and in comparison with existing temporal GNN designs in which all nodes in each graph (data collected from each time step) have to go through the spatial and temporal computations).
Xue discloses all the limitations as the above but doesn’t explicitly disclose wherein the PMU is configured to provide the power voltage for the NVM, the one or more in-memory processor elements, and the first clock generator. However, Ray discloses this (paragraph 241, a power supply or source can provide voltage and/or current to system 1400 or any component or system described herein.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Ray with the teaching of Xue so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 4, Xue discloses all the limitations as the above but does not explicitly discloss wherein the PMU is configured to provide the power voltage for the NVM, the one or more in-memory processor elements, and the first clock generator. However, Ray discloses this (paragraph 241, a power supply or source can provide voltage and/or current to system 1400 or any component or system described herein.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Ray with the teaching of Xue so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 5, Xue disloses wherein the buffer circuitry configured to simultaneously perform a first operation of writing the pre-processed data into the plurality of banks through a first port and a second operation of reading the pre-processed data stored in the plurality of banks through a second port (paragraph 40, The DMA interface 235 may refer to a function provided by some computer bus architectures, which enables devices to directly read data from and/or write data to the memory 210).
Xue discloses all the limitations as the above but does not explicitly disclose dual port PING-PONG static random-access memory (SRAM). However, Ray discloses this (paragraph 235, The memory device 1420 can be a dynamic random-access memory (DRAM) device, a static random-access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Ray with the teaching of Xue so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 6, Xue discloses wherein the buffer circuitry is configured to: performing the second operation of reading the pre-processed data stored in the plurality of banks and transferring the pre-processed data to the one or more in-memory processor elements (paragraph 40, The DMA interface 235 may refer to a function provided by some computer bus architectures, which enables devices to directly read data from and/or write data to the memory 210).
Xue discloses all the limitations the above but does not explicitly disclose wherein the buffer circuitry is configured to: operate with a second voltage and a second clock in response to performing the first operation, and operate with a first voltage, the first voltage having a first value higher than a second voltage of the second voltage. However, Ray discloses this (paragraph 73, a direct current (DC) voltage pulse corresponding to toggle clock pulse that may be generated by a phase locked loop (PLL) circuit associated with the processor 102)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Ray with the teaching of Xue so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 7, Ray discloses wherein the buffer circuitry is configured to alternately repeat the first operation, the second operation, and a third operation of powering down until the pre-processed data is written again into the plurality of banks after the second operation is performed (paragraph 205, lines 9-13, the training process occurs repeatedly as the weights of the network are adjusted to refine the output generated by the neural network. The training process can continue until the neural network reaches a statistically desired accuracy associated.)
As per claim 8, Ray discloses wherein the PMU is configured to turn off power to the NVM and the one or more in-memory processor elements during an idle period excluding an active period, and wherein the processor circuitry performs the neural network computation during the active period (paragraph 220, parallel processors described herein can enable rapid training of the increasingly complex neural networks used for autonomous driving solutions and enables the deployment of low power inferencing processors).
As per claim 9, Ray discloses wherein the PMU is configured to turn off power to the first clock generator during an idle period excluding an active period, and wherein the processor circuitry performs the neural network computation during the active period(paragraph 220, parallel processors described herein can enable rapid training of the increasingly complex neural networks used for autonomous driving solutions and enables the deployment of low power inferencing processors).
As per claim 10, Ray discloses wherein the first clock generator is configured to provide the first clock of a first voltage for the NVM and the one or more in-memory processor elements to operate at high speed during an active period, and wherein the processor circuitry performs the neural network computation during the active period (paragraph 73, a direct current (DC) voltage pulse corresponding to toggle clock pulse that may be generated by a phase locked loop (PLL) circuit associated with the processor 102).
As per claim 11, Ray discloses wherein the always-on circuitry is configured to provide voice data, the voice data being obtained by converting a voice audio signal into a digital signal and extracting a feature, as the pre-processed data to the processor circuitry (paragraph 241, the power source includes a DC power source, such as an external AC to DC converter).
As per claim 12, Ray discloses wherein the always-on circuitry comprises:
an analog front end (AFE) configured to convert the voice audio signal into the digital signal (paragraph 241, the power source includes a DC power source, such as an external AC to DC converter);
a pre-processor circuitry configured to perform pre-processing to extract a feature of the digital signal (paragraph 343, models the flow of digital signals between hardware registers, including the associated logic performed using the modeled digital signals); and
a second clock generator configured to generate a second clock for driving the AFE and the pre-processor circuitry (paragraph 252, lines 9-10, enable an interface between a clock domain of the graphics processor core block 1519 and other clock domains within the SoC).
As per claim 13, Ray discloses the neural network accelerator further comprising: voice activity detection (VAD) circuitry configured to determine whether the voice audio signal is present or absent, wherein the VAD circuitry is configured to wake up the always-on circuitry responsive to a determination that the voice audio signal is present (paragraph 177, machine learning applications 602 include, but are not limited to, voice-based virtual assistants, image or facial recognition algorithms.)
As per claim 14, Xue discloses a method, the method comprising:
generating pre-processed data (paragraph 31, data preprocessing);
storing (paragraph 33, the storage/memory 210 and temporarily store them in its on-chip memory for preprocessing the input data) the pre-processed data in a plurality of banks (fig.2, register bank 229); and
performing, by a neural network model (paragraph 33, neural network models), a neural network computation (paragraph 33, perform preprocessing of the input data to the models to accelerate the subsequent neural network computations) on the pre-processed data (paragraph 31, data preprocessing).
Vue discloses all the limitations as the above but does not explicitly disclose converting a voice audio signal into a digital signal and extracting a feature. However, Ray discloses this (paragraph 177, machine learning applications 602 include, but are not limited to, voice-based virtual assistants, image or facial recognition algorithms.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Ray with the teaching of Xue so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 15, Xue discloses wherein the performing of the neural network computation comprises:
transferring, by a first clock, the pre-processed data stored in the plurality of banks to one or more in-memory processor elements (paragraph 75, When the thread group includes more threads than the number of processing engines within the graphics multiprocessor 234, processing can be performed over consecutive clock cycles); and
Xue discloses all the limitations as the above but does not explicitly discloses performing, by the first clock, the neural network computation comprising a multiply-accumulate (MAC) computation between the pre-processed data and a stored weight. However, Ray discloses this, (paragraph 307, data manipulation instructions, dot product instructions, multiply-add instructions, or multiply-accumulate instructions, can have a third source operand).
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Ray with the teaching of Xue so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 16, Xue discloses wherein the storing of the pre-processed data in the plurality of banks comprises simultaneously performing a first operation of writing the pre-processed data in the plurality of banks through a first port and a second operation of reading the pre-processed data stored in the plurality of banks through a second port (paragraph 40, The DMA interface 235 may refer to a function provided by some computer bus architectures, which enables devices to directly read data from and/or write data to the memory 210).
As per claim 17, Xue discloses wherein the storing of the pre-processed data in the plurality of banks comprises:
performing the second operation of reading the pre-processed data stored in the plurality of banks and transferring the pre-processed data to one or more in-memory processor elements(paragraph 40, The DMA interface 235 may refer to a function provided by some computer bus architectures, which enables devices to directly read data from and/or write data to the memory 210).
Xue discloses all the limitations the above but does not explicitly disclose performing the first operation with a second voltage and a second clock; and performing with a second voltage and a second clock in response to performing with a first voltage having the first voltage having a first value higher than a second voltage of the second voltage and a first clock faster than the second clock. However, Ray discloses this (paragraph 73, a direct current (DC) voltage pulse corresponding to toggle clock pulse that may be generated by a phase locked loop (PLL) circuit associated with the processor 102)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Ray with the teaching of Xue so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 18, Ray discloses wherein the storing of the pre-processed data in the plurality of banks comprises alternately repeating the first operation, the second operation, and a third operation of powering down until the pre-processed data is written again into the plurality of banks after the second operation is performed (paragraph 205, The training process occurs repeatedly as the weights of the network are adjusted to refine the output generated by the neural network. The training process can continue until the neural network reaches a statistically desired accuracy associated.)
As per claim 19, Ray discloses the method further comprising: turning off power to non-volatile memory (NVM) and the one or more in-memory processor elements during an idle period excluding an active period during which the neural network computation is performed (paragraph 220, parallel processors described herein can enable rapid training of the increasingly complex neural networks used for autonomous driving solutions and enables the deployment of low power inferencing processors).
As per claim 20, Ray discloses the method further comprising: providing the first clock of a first voltage for NVM and the one or more in-memory processor elements to operate at high speed in an active period in which the neural network computation is performed (paragraph 73, a direct current (DC) voltage pulse corresponding to toggle clock pulse that may be generated by a phase locked loop (PLL) circuit associated with the processor 102).
5. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Nez et al. [Pub. No. US20240169192] discloses generating integrated circuit instructions for the integrated circuit to perform inference of the neural network.
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV].
The fax phone numbers for the organization where this application or proceeding is assigned are (571)273-8300 for regular communications and After Final communications. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-2100.
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/K. T. H./
Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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