DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to amendment filed on 10/28/2025.
No claim amendments have been made.
The objections and rejections from the prior correspondence that are not restated herein are withdrawn.
Terminal Disclaimer
The terminal disclaimer filed on 10/28/2025 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of US Patent 12,099,725 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3, 5, 7-10, 12, 14-17, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanpairoj et al. (US 2019/0065080) and Alhussien et al. (US 2013/0145238).
With respect to claim 1, Tanpairoj teaches of a method comprising: determining whether a logical saturation of a memory device in a memory sub-system satisfies an adjust criterion (paragraph 35, 65; where the logical saturation of the of the memory device is monitored and when it exceeds the logical saturation usage threshold, the cache memory cells are reconfigured from SLC to MLC or from MLC to SLC).
Tanpairoj fails to explicitly teach of responsive to determining that the logical saturation satisfies the adjust criterion, designating an additional block of the memory device to store error correction data.
However, Alhussien teaches of responsive to determining that a higher level of error correcting capability is needed, designating an additional block of the memory device to store error correction data (fig. 7, paragraph 60, 63; where a portion of the spare area (claimed block) is allocated to another page to store the strong ECC encoding of a lower code rate based on the error probabilities, i.e. a four-level cell (QLC) MSB page requires more parity bits).
The combination of Tanpairoj and Alhussien teaches of responsive to determining that the logical saturation satisfies the adjust criterion, designating an additional block of the memory device to store error correction data (Tanpairoj, paragraph 35, 65; Alhussien, fig. 7, paragraph 60, 63; where in the combination as the SLC cells in the cache are reconfigured to MLC based on the logical saturation compared to the threshold, the spare area will be added to the MSB pages of the multi-level cells to provide a stronger ECC code for the pages as taught in Alhussien).
Tanpairoj and Alhussien are analogous art because they are from the same field of endeavor, as they are directed to memory management.
It would have been obvious to one of ordinary skill in the art having the teachings of Tanpairoj and Alhussien before the time of the effective filing of the claimed invention to incorporate the dedicating spare area in the pages memory for storing the ECC for lower code rates of Alhussien into Tanpairoj. Their motivation would have been to correct more errors that occur in the data.
With respect to claim 8, the combination of Tanpairoj and Alhussien teaches of the limitations cited and described above with respect to claim 1 for the same reasoning as recited with respect to claim 1.
Tanpairoj also teaches of a system comprising: a memory device; and a processing device, operatively coupled with the memory device, to perform operations recited in claim 1 (paragraph 12; where the SSD includes processors and controllers that the functions to operate the memory device as disclosed).
With respect to claim 15, the combination of Tanpairoj and Alhussien teaches of the limitations cited and described above with respect to claim 1 for the same reasoning as recited with respect to claim 1.
Tanpairoj also teaches of a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations of claim 1 (paragraph 80-82; where the machine readable medium stores instructions that are executed by a processor to perform the disclosed techniques).
With respect to claims 2, 9, and 16, Tanpairoj teaches of wherein the adjust criterion represents a system requirement for a minimum amount of valid blocks required to accommodate a certain logical storage capacity (paragraph 60-61, 63, 65; where as the cache device fills up/is used to the usage threshold, memory cells are reconfigured from SLC to MLC to increase storage capacity of the cache, thus keeping a minimum amount of valid blocks available to store data).
With respect to claims 3, 10, and 17, Alhussien teaches of wherein designating the additional block of the memory device to store the error correction data decreases a code rate of the memory device (fig. 7, paragraph 60, 63; where a portion of the spare area (claimed block) is allocated to another page to store the strong ECC encoding with a lower code rate).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
With respect to claims 5, 12, and 19, Tanpairoj teaches of determining whether the logical saturation satisfies a restore criterion (paragraph 65; where the LBA usage threshold is such that the memory cells are reconfigured from MLC to SLC).
The combination of Tanpairoj and Alhussien teaches of responsive to determining that the logical saturation satisfies the restore criterion, undesignating the additional block of the memory device for storing the error correction data (Tanpairoj, paragraph 65; Alhussien, fig. 7, paragraph 60, 63; where as the memory is reconfigured from MLC to SLC, the spare area is no longer needed for the stronger ECC because the memory cell is no longer a multi-level cell but a SLC. Thus, it suggests to one of ordinary skill in the art that the spare area is released from being used for ECC).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
With respect to claims 7 and 11, Alhussien teaches of wherein undesignating the additional block of the memory device for storing the error correction data increases a code rate of the memory device (fig. 7, paragraph 60, 63; since when a portion of the spare area (claimed block) is allocated to another page to store the strong ECC encoding the code rate is lowered, this suggests that when the spare area is unallocated, the code rate would increase).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
Claim(s) 4, 11, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanpairoj and Alhussien as applied to claims 1, 8, and 15 above, and further in view of Chung et al. (US 2023/0106125).
With respect to claims 4, 11, and 18, the combination of Tanpairoj and Alhussien fails to explicitly teach of wherein the code rate of the memory device represents a ratio of user data to a combination of the user data and the error correction data.
However, Chung teaches of adjusting a code rate of the memory device based on the operating conditions of the memory (paragraph 7, 45; where the ECC code rate is selected based on the specific write address and the operating conditions); and
wherein the code rate of the memory device represents a ratio of user data to a combination of the user data and the error correction data (paragraph 3; where the code rate is the size of the payload data divided by the sum of the size of the payload data and the size of the ECC code).
Tanpairoj, Alhussien, and Chung are analogous art because they are from the same field of endeavor, as they are directed to memory management.
It would have been obvious to one of ordinary skill in the art having the teachings of Tanpairoj, Alhussien, and Chung before the time of the effective filing of the claimed invention to incorporate the determining the code rate in the combination of Tanpairoj and Alhussien as taught in Chung. Their motivation would have been to more efficiently use ECC algorithms (Chung, paragraph 5).
Claim(s) 6, 13, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanpairoj and Alhussien as applied to claims 5, 12, and 19 above, and further in view of Bahirat (US 2019/0171564).
With respect to claims 6, 13, and 20, the combination of Tanpairoj and Alhussien fails to explicitly teach of wherein the logical saturation satisfies the restore criterion when a surplus physical capacity of the memory device at the logical saturation does not meet a minimum physical capacity of the memory device.
However, Bahirat teaches of wherein the logical saturation satisfies the restore criterion when a surplus physical capacity of the memory device at the logical saturation does not meet a minimum physical capacity of the memory device (paragraph 32; where when the free space in the storage is below the lower threshold, the stream with the lowest logical saturation is chosen for garbage collection).
Tanpairoj, Alhussien, and Bahirat are analogous art because they are from the same field of endeavor, as they are directed to memory management.
It would have been obvious to one of ordinary skill in the art having the teachings of Tanpairoj, Alhussien, and Bahirat before the time of the effective filing of the claimed invention to incorporate the performing GC on the lowest logical saturation data stream when the free space is below the threshold in the combination of Tanpairoj and Alhussien as taught in Bahirat. Their motivation would have been to ensure there is space available for data stores.
Response to Arguments
Applicant's arguments filed on 10/28/2025 have been fully considered but they are not persuasive.
Applicant argues with respect to independent claims 1, 8, and 15, that the combination of Tanpairoj and Alhussien does not teach or suggest, “responsive to determining that the logical saturation satisfies the adjust criterion, designating an additional block of the memory device to store error correction data,” as Alhussien is silent about determining that the logical saturation satisfies the adjusted criterion. The examiner disagrees with this reasoning.
The claims specify that “responsive to determining that the logical saturation… designating.” The claims do not require the designating to occur directly responsive to the determining, but only that the designating occurs responsive or as one or more results of the determining.
Tanpairoj discloses in paragraphs 60 and 65 that as the memory fills up memory cells configured as SLC cache are migrated to MLC to increase data storage capacity. This is done by size rules where, “based upon logical saturation i.e., a list of one or more Logical Block Addressing (LBA) usage thresholds and corresponding SLC cache sizes,” the memory cells are reconfigured from SLC to MLC, changing the size of the SLC cache, see paragraph 65.
Tanpairoj also discloses in paragraph 35 that an MLC NAND flash has a higher bit error rate than a corresponding SLC flash, and as a result, the MLC device requires more metadata bytes for error data than the corresponding SLC device.
Alhussien discloses in figure 7 and paragraphs 60, 63 that the spare area is allocated among different pages based on the relative error probabilities of each page. MSB pages are more error prone than LSB pages and as a result a portion of the spare area is allocated to a different page, a MSB page, to be used for stronger ECC codes with lower code rates for that MSB page.
Therefore, in the combination of Tanpairoj and Alhussien, when the logical saturation threshold is reached and SLC flash is migrated to MLC flash in Tanpairoj (Tanpairoj, paragraph 65), Tanpairoj is aware that the now MLC flash cells have a higher bit error rate and require more metadata bytes for error correction than SLC flash cells (Tanpairoj, paragraph 35). As a result of this change, space in the spare area of Alhussien is allocated to the MLC flash cells to be used for stronger ECC codes with lower code rates (Alhussien, paragraph 60, 63).
Thus, as in the combination, the logical saturation threshold is reached which causes SLC cells to be migrated to MLC cells, which need additional storage for error correction, causing the spare area to be allocated to the MLC for stronger ECC codes. If the logical saturation threshold isn’t reached, then the allocation of the spare area for stronger ECC codes would not have occurred in the combination. Therefore, the combination of Tanpairoj and Alhussien reads on the limitations at issue.
As discussed in the interview on 10/21/2025, the examiner noted that by specifying that the designating an additional block of the memory device to store error correction data occurs “directly responsive” to the claimed determining would over come the applied prior art rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL C KROFCHECK whose telephone number is (571)272-8193. The examiner can normally be reached on Monday - Friday 8am -5pm, first Friday off.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on (571) 272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MICHAEL C. KROFCHECK
Primary Examiner
Art Unit 2138
/Michael Krofcheck/Primary Examiner, Art Unit 2138