DETAILED ACTION
This action is responsive to 08/22/2024.
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5-10, and 12-20 are is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (US Pub. 2021/0098457), hereinafter Cheng.
Regarding claim 1, Cheng discloses a semiconductor device (see fig. 11I) comprising: a semiconductor substrate including a first active region (active region 122 corresponding to semiconductor device 102A-see fig. 11I) and a second active region (active region 122 corresponding to semiconductor device 102E-see fig. 11I); a first dielectric layer disposed over the first active region (gate dielectric layer 120A (1102A, 1122) on 102A-see fig. 11I); a second dielectric layer disposed over the second active region (gate dielectric layer 120E (1102E, 1122) on 102E-see fig. 11I); a first gate electrode disposed over the first dielectric layer (a gate electrode is formed on work function layer (e.g., 1180) in semiconductor device 102A-see fig. 11I, [0096], and [0099]); and a second gate electrode disposed over the second dielectric layer (a gate electrode is formed on work function layer (e.g., 1180) in semiconductor device 102E-see fig. 11I, [0096], and [0099]), wherein: the first active region and the second active region have different conductivity types (102A is an n-type semiconductor device, and 102E is a p-type semiconductor device), the first dielectric layer and the second dielectric layer include a same dielectric material (first gate dielectric layers (1102A-1102E) can be formed of a lanthanum or magnesium doped hafnium oxide material-see [0089]), and dipole concentration of the first dielectric layer is different from dipole concentration of the second dielectric layer (dopants, such as lanthanum or magnesium, in the doped gate dielectric layers can form electric dipole structures between the doped gate dielectric layers and the first or second gate dielectric layers (see [0097]). First gate dielectric layer (e.g., 1102A formed in device1030A) has greater dopant concentration compared to first gate dielectric layer (e.g., 1102E formed in device region 1030E)-see [0089]).
Regarding claim 2, Cheng discloses wherein each of the first dielectric layer and the second dielectric layer includes: a first sub-dielectric layer (1102A and 1102E-see fig. 11I); and a second sub-dielectric layer disposed over the first sub-dielectric layer (1122-see fig. 11I).
Regarding claim 5, Cheng discloses wherein each of the first dielectric layer and the second dielectric layer include a defect in which dipole diffusion occurs (see [0021] and [0097]-variations of the dopant concentrations can lead to changes in the crystallographic structure of the hafnium-based gate dielectric layers).
Regarding claim 6, Cheng discloses wherein concentration of the defect of the first dielectric layer and concentration of the defect of the second dielectric layer are controlled by heat treatment (see figs. 11F-11G with description in [0091]-[0093]).
Regarding claim 7, Cheng discloses wherein the first dielectric layer includes a dipole material that is diffused from an upper portion of the first dielectric layer to the inside of the first dielectric layer (dopants, such as lanthanum or magnesium, in the doped gate dielectric layers can form electric dipole structures between the doped gate dielectric layers and the first or second gate dielectric layers, which in turn impacts the threshold voltages-see [0097]).
Regarding claim 8, Cheng discloses wherein the dipole material includes at least one of hafnium (Hf), aluminum (Al), lanthanum (La), zirconium (Zr), scandium (Sc), and erbium (Er)- (Lanthanum [0097]).
Regarding claim 9, Cheng discloses wherein the semiconductor substrate further includes: a third active region (active region 122 in device 102B-see fig. 11I) and a fourth active region (active region 122 in device 102F-see fig. 11I); a third gate electrode disposed to overlap the third active region (a gate electrode is formed on work function layer (e.g., 1180) in semiconductor device 102B-see fig. 11I, [0096], and [0099]); a fourth gate electrode disposed to overlap the fourth active region (a gate electrode is formed on work function layer (e.g., 1180) in semiconductor device 102F-see fig. 11I, [0096], and [0099]); a third dielectric layer disposed between the third active region and the third gate electrode (gate dielectric layer 120B (1102B, 1122) on 102B-see fig. 11I); and a fourth dielectric layer disposed between the fourth active region and the fourth gate electrode (gate dielectric layer 120F (1102F, 1122) on 102F-see fig. 11I), wherein: the third active region and the fourth active region have different conductivity types (102C is n-type device and 102F is p-type device), the first active region and the third active region have a same conductivity type (102A and 102B are both n-type devices), and the third dielectric layer and the fourth dielectric layer include a same dielectric material (first gate dielectric layers (1102A-1102E) can be formed of a lanthanum or magnesium doped hafnium oxide material, AND 1102F may be intrinsic in some embodiments (i.e., formed of undoped hafnium oxide-see [0089]).
Regarding claim 10, Cheng discloses wherein dipole concentration of the third dielectric layer is different from dipole concentration of the fourth dielectric layer (see [0089]).
Regarding claim 12, Cheng discloses wherein each of the third dielectric layer and the fourth dielectric layer includes: a third sub-dielectric layer (1102B-see fig. 11I); and a fourth sub-dielectric layer disposed over the third sub-dielectric layer (1122-see fig. 11I).
Regarding claim 13, Cheng discloses wherein the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer include a same dielectric material (first dielectric layers can be formed of a lanthanum doped hafnium oxide. Other suitable dopants such as silicon, yttrium, gadolinium, strontium, any other suitable material, and/or combination thereof).
Regarding claim 14, Cheng discloses a method for manufacturing a semiconductor device, the method comprising: forming a first dielectric layer (gate dielectric layer 120A (1102A, 1122) on 102A-see fig. 11I) over a first active region included in a semiconductor substrate (active region 122 corresponding to semiconductor device 102A-see fig. 11I); forming a second dielectric layer (gate dielectric layer 120E (1102E, 1122) on 102E-see fig. 11I) over a second active region included in the semiconductor substrate (active region 122 corresponding to semiconductor device 102E-see fig. 11I); forming a metal pattern layer over the second dielectric layer (see operation 904 in fig. 9 with description in [0082]); forming a dipole material layer over the first dielectric layer and the metal pattern layer (see operation 906 in fig. 9 with description in [0086]); diffusing dipole material from the dipole material layer to the first dielectric layer and the second dielectric layer (performing anneal process to drive dopants from the first and/or second n-dipole layers and forming doped first gate dielectric layers-see operation 908 in fig. 9 with description in [0088]); forming a first gate electrode overlapping the first dielectric layer (a gate electrode is formed on work function layer (e.g., 1180) in semiconductor device 102A-see fig. 11I, [0096], and [0099]); and forming a second gate electrode overlapping the second dielectric layer (a gate electrode is formed on work function layer (e.g., 1180) in semiconductor device 102E-see fig. 11I, [0096], and [0099]), wherein: the first dielectric layer and the second dielectric layer include a same dielectric material (first gate dielectric layers (1102A-1102E) can be formed of a lanthanum or magnesium doped hafnium oxide material-see [0089]), and the first active region and the second active region have different conductivity types (102A is an n-type semiconductor device, and 102E is a p-type semiconductor device).
Regarding claim 15, Cheng discloses further comprising forming an interlayer dielectric layer over the first active region and the second active region (interface layer 112 (made of any suitable dielectric material, such as silicon oxide, aluminum oxide, etc., is formed on the semiconductor layers 122-see figs. 11A-11K and [0083]-which can provide a variety of functions, such as a binding layer and/or a barrier layer (see [0081] and [0083]), wherein the forming the first dielectric layer includes: forming a first sub-dielectric layer overlapping the interlayer dielectric layer (1102A-see fig. 11I)); and forming a second sub-dielectric layer overlapping the first sub-dielectric layer (1122 formed on 1102A-see fig. 11I), and wherein the forming the second dielectric layer includes: forming the first sub-dielectric layer overlapping the interlayer dielectric layer (1102E formed on 112A-see fig. 11I); and forming the second sub-dielectric layer overlapping the first sub-dielectric layer (1122 formed on 1102E-see fig. 11I).
Regarding claim 16, Cheng discloses further comprising: forming a first defect control layer over the first dielectric layer; forming a second defect control layer over the second dielectric layer; performing heat treatment to control defect concentration of the first dielectric layer and defect concentration of the second dielectric layer; and removing the first defect control layer and the second defect control layer (first and second capping layer 1130 and 1132 can be deposited on first and second gate dielectric layers 1102A-1102F and 1122. A first treatment process 1160 can be performed between the deposition of first and second capping layers 1130 and 1132. A second treatment process 1170 can be performed on deposited first and second capping layers. The first and second treatment processes 1160 and 1170 can be used to improve the quality of first and second gate dielectric layers by improving crystalline quality through annealing-see figs. 11F-11G and [0091]-[0093]).
Regarding claim 17, Cheng discloses wherein the first defect control layer or the second defect control layer includes a plurality of sub-control layers (first and second capping layers 1130 and 1132-see [0091]-[0093] and figs. 11F-11G).
Regarding claim 18, Cheng discloses wherein the plurality of sub-control layers include at least one of titanium nitride (TiN), titanium aluminide (TiAl), and polysilicon (Si)-(capping layer 1130 can be any suitable material, e.g. titanium silicon nitride (TiSiN) or titanium nitride (see [0092]), and capping layer 1132 can be formed using any suitable material, such as silicon-see [0093]).
Regarding claim 19, Cheng discloses further comprising removing the metal pattern layer (an etching process can be used to remove the capping layer-see [0094]).
Regarding claim 20, Cheng discloses wherein the dipole material includes at least one of hafnium (Hf), aluminum (Al), lanthanum (La), zirconium (Zr), scandium (Sc), and erbium (Er)-(see [0086]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng.
Regarding claim 11, Cheng does not appear to expressly disclose wherein the first dielectric layer and the third dielectric layer include different dielectric materials.
However, Cheng, in for example, [0081] discloses that gate dielectric material 1102 can be formed using other suitable gate dielectric materials, such as silicon oxide or any other suitable dielectric material.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to glean from the combined teachings of Cheng the idea of using different dielectric materials for the first and the second dielectric layers, as a simple substitution of one known element for another to yield predictable results.
Claim 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of JI et al. (US Pub. 2013/0069166), hereinafter JI.
Regarding claim 3, Cheng does not appear to expressly disclose wherein the first sub-dielectric layer and the second sub-dielectric layer have different silicon concentrations.
Cheng is relied upon to teach wherein the first sub-dielectric layer and the second sub-dielectric layer have different silicon concentrations (see, for example, fig. 3 with description in [0028]-[0030], wherein, interlayer 23 is formed of an insulating layer that includes SiO2 with a thickness of about 10 Å, and high dielectric constant layer 24 is disposed on the interlayer 23 and includes a metal silicate, for example, hafnium silicate (HfSiO) grown with a thickness of 30 Å).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of JI with the invention of Cheng such that the first sub-dielectric layer and the second sub-dielectric layer have different silicon concentrations, as taught by JI, which constitutes combining prior art elements according to known methods to yield predictable results.
Claim 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Kim et al. (US Pub. 2012/0129330), hereinafter Kim.
Regarding claim 4, Cheng does not appear to expressly disclose wherein the first sub-dielectric layer and the second sub-dielectric layer have different nitrogen concentrations.
Kim is relied upon to teach wherein the first sub-dielectric layer and the second sub-dielectric layer have different nitrogen concentrations (see, for example, fig. 4 with description in [0010], [0019], and [0039], which teaches an upper gate insulating layer 11 and a lower gate insulating layer 9, wherein a nitrogen concentration of the upper gate insulating layer 11 is lower than that of the lower gate insulating layer 9).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Kim with the invention of Cheng such that the first and the second sub-dielectric layers having different nitrogen concentrations, as taught by Kim, therefore, wet etch rate of the upper gate insulating layer 11 may be lower than that of the lower gate insulating layer 9, as a result, the upper gate insulating layer 11 may act as an etch stop layer that prevents exposure of the nitrogen containing lower gate insulating layer 9 while a lower metal layer 18 in the first region A is selectively removed using a wet etching process (see [0044]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARDIS F AZONGHA whose telephone number is (571)270-7706. The examiner can normally be reached 10AM-7:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at (571)272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SARDIS F AZONGHA/Primary Examiner, Art Unit 2627
Prosecution Insights