DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I and Specie 1 directed to claims 1-11 in the reply filed on 5/6/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 states, “the first electrical structure is electrically parallel to the first electrical structure”. It is unclear how the “first electrical structure” can be parallel with itself. Appropriate amend is required to clarify the meaning of the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jensen et al. (US PG. Pub. 2021/0305211).
Regarding claim 9 – Jensen teaches a circuit package (fig. 1, 100 [paragraph 0017] Jensen states, “semiconductor package 100”) comprising: a first die (die 102a having substrate 104a and redistribution layer 110a [paragraph 0026] Jensen states, “first and second semiconductor dies 102a-b”) comprising a first coupler (traces within the redistribution structure 110a [paragraph 0022] Jensen states, “The first and second redistribution structures 110a-b can each include one or more electrically conductive components, such as contacts, traces, pads, pins, wiring, circuitry, and the like”) spread across multiple layers (layers 110a and 104a) within the first die (102a) and one or more exposed first connections (122a [paragraph 0025] Jensen states, “interconnect pad 122a”); a second die (102b) comprising a second coupler (traces within the redistribution structure 110b) spread across second multiple layers (layers 110b and 104b) withing the second die (102b) and one or more exposed second connections (122b [paragraph 0025] Jensen states, “interconnect pad 122b”), the second die (102b) stacked on the first die (102a); and an electrical connection formed by a conductive bonding agent (109 [paragraph 0019] Jensen states, “interconnect structure 109 can be formed of any suitably conductive material such as copper, nickel, gold, silicon, tungsten, solder (e.g., SnAg-based solder) between the one or more exposed first connections (122a) and the one or more exposed second connections (122b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 & 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jensen et al in view of Roy et al. (US PG. Pub. 2021/0408015)
Regarding claim 1 – Jensen teaches a circuit package (fig. 1, 100 [paragraph 0017] Jensen states, “semiconductor package 100”) comprising: a first multi-layer structure (die 102a having substrate 104a and redistribution layer 110a [paragraph 0026] Jensen states, “first and second semiconductor dies 102a-b”) comprising: a first electrical structure (112a [paragraph 0023] Jensen states, “signal trace 112a”) spread across layers of the first multi-layer structure (104a/110a); and one or more first exposed conductors (122a [paragraph 0025] Jensen states, “interconnect pad 122a”) on an exterior layer of the first multi-layer structure (102a); a second multi-layer structure (die 102b having substrate 104b and redistribution layer 110b) stacked on the first multi-layer structure (102a), the second multi-layer structure (102b) comprising: a second electrical structure (112b [paragraph 0025] Jensen states, “signal trace 112b”) spread across layers of the second multi-layer structure (104b/110b); and one or more second exposed conductors (122b [paragraph 0025] Jensen states, “interconnect pad 122b”) on an exterior layer of the second multi-layer structure (102b); a conductive bonding agent (109 [paragraph 0019] Jensen states, “interconnect structure 109 can be formed of any suitably conductive material such as copper, nickel, gold, silicon, tungsten, solder (e.g., SnAg-based solder), conductive-epoxy, combinations thereof”) coupling the one or more first exposed conductors (122a) to the one or more second exposed conductors (122b); and a material encapsulating (126 [paragraph 0021] Jensen states, “The mold material 126 can be a resin, epoxy resin, silicone-based material, polyimide, or any other material suitable for encapsulating the first and second semiconductor dies 102a-b”) the first multi-layer structure (102a) and the second multi-layer structure (102b) and flowing around the conductive bonding agent (109; claimed structure shown in figure 1).
Jensen fails to explicitly teach wherein the first electrical structure is electrically parallel to the second electrical structure.
Roy teaches a circuit package (figs. 1 & 5D) having a first (fig. 5D, [paragraph 0040] Roy states, “metal layers 1-6 in the PCB 490”) and second electrical structure (424 [paragraph 0034] Roy states, “inner metal layer 424”) wherein the first electrical structure is electrically parallel to the second electrical structure ([paragraph 0029] Roy states, “The PCB 120 also has a parallel impedance path…The package 130 also includes an OPD 150 as discussed above. The OPD 150 is part of a parallel impedance path…The die 140 has a bump resistance 142 and parallel impedance path”; figure 1 shows the PCB, Package and Die being “electrically parallel” to each other).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit package having first and second electrical structures as taught by Jensen with the first and second electrical structures being electrically parallel to each other as taught by Roy because Roy states, “It will be appreciated that voltage droop is proportional to the impedance of the PDN. The voltage droop can be significantly improved using various aspects disclosed herein…allows for tuning the impedance of individual devices to reduce the impedance at the resonant frequencies (see, e.g., FIG. 3). This reduces the voltage drop and noise in the power distribution network.” [paragraph 0033 & 0041]. Additionally a parallel arrangement between the first and second coupler allows for consistent voltage across components and improved reliability.
Regarding claims 2 – Jensen in view of Roy teach the circuit package of claim 1, wherein the first electrical structure (Jensen; fig. 1, 112a) is a first coupler ([Abstract] Jensen states, “an interconnect structure can be positioned between the first and second semiconductor dies to electrically couple the first and second redistribution structures to each other”; claimed structure shown in figure 1).
Regarding claim 3 – Jensen in view of Roy teach the circuit package of claim 2, wherein the second electrical structure (Jensen fig. 1, 112b) is a second coupler ([Abstract] Jensen states, “an interconnect structure can be positioned between the first and second semiconductor dies to electrically couple the first and second redistribution structures to each other”; claimed structure shown in figure 1).
Regarding claim 4 – Jensen in view of Roy teach the circuit package of claim 3, wherein the first coupler (Roy; fig. 5D, metal layers extending across the PCB 490) and the second coupler (424) being in parallel (figure 1 shows the PCB, Package and Die being “electrically parallel” to each other).
Please note that the claims are directed to apparatus which must be distinguished from the prior art in term of structure rather function [MPEP 2144]. Hence, the functional limitations “creates an effective impedance less than an impedance less than either coupler alone“ which are narrative in form have not been given any patentable weight. In order to be given patentable weight, a functional recitation must be supported by recitation in the claim of sufficient structure to warrant the presence of the functional language. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997).
Regarding claim 7 – Jensen in view of Roy teach the circuit package of claim 1, wherein the first multi-layer structure (Jensen; fig. 1, 102a) comprises a metalized laminate ([paragraph 0017 & 0022] Jensen states, “The first and second semiconductor dies 102a-b can each include a respective semiconductor substrate 104a-b (e.g., a silicon substrate, a gallium arsenide substrate, an organic laminate substrate, etc.)…the redistribution structures 110a-b can be made of any suitable conductive material, such as one or more metals”).
Regarding claim 8 – Jensen in view of Roy teach the circuit package of claim 1, wherein the first multi-layer structure (Jensen; fig. 1, 102a) comprises a structure selected from the group consisting of a low temperature co-fired ceramic structure, a high temperature co-fired ceramic structure, and an additive manufacturing structure (the first multi-layer structure 102a is consists of a semiconductor substrate 104a with is considered to be an “additive manufacturing structure” and appears to meet the claimed limitation).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jensen et al. in view of Roy et al. as applied to claim 3 above, and further in view of Huang et al. (US PG. Pub. 2017/0250172).
Regarding claim 5 – Jensen in view of Roy teach the circuit package of claim 3, but fails to teach further comprising a third multi-layer structure stacked on the second multi-layer structure, the third multi-layer structure comprising: a third electrical structure spread across layers of the third multi-layer structure; and one or more third exposed conductors on an exterior layer of the second multi-layer structure electrically coupled to at least one of the one or more second exposed conductors.
Huang teaches further comprising a third multi-layer structure (fig. 4a, 124a [paragraph 0036] Huang states, “semiconductor die 124a”) stacked on the second multi-layer structure (224b), the third multi-layer structure (124a) comprising: one or more third exposed conductors (134a [paragraph 0037] Huang states, “bonding conductive layer 134a”) on an exterior layer (lower exterior layer of 124a) of the second multi-layer structure (124b) electrically coupled to at least one of the one or more second exposed conductors (see top of conductor 132a on upper surface of second multi-layer structure 124b).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit package having a first and second multi-layer structure as taught by Jensen in view of Roy with the addition of a third multi-layer structure connected to the second multi-layer structure as taught by Huang because additionally stacked dies/multi-layer structure will increase the capacity of the overall circuit package such as increased memory/storage.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the third multi-layer structure having a third electrical structure spread across layers of the third multi-layer structure, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Please note that in the instant application, paragraph 0040 applicant has not disclosed any criticality for the claimed limitations. Additionally stacked dies/multi-layer structure with additional electrical structure spread across will increase the capacity of the overall circuit package such as increased memory/storage.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jensen et al. in view of Roy et al. as applied to claim 1 above, and further in view of Kim et al. (US PG. Pub. 2022/0013444).
Regarding claim 6 – Jensen in view of Roy teach the circuit package of claim 1, but fails to teach further comprising an impedance-matching circuit electrically positioned between the first electrical structure and a power amplifier die.
Kim teaches a circuit package (fig. 6, 600) further comprising an impedance-matching circuit (circuitry shown between power amplifier 508 and first electrical structure 304) electrically positioned between the first electrical structure (304 [paragraph 0049] Kim states, “integrated device 304”) and a power amplifier die (508 [paragraph 0049] Kim states, “power amplifier 508”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit package having a first electrical structure as taught by Jensen in view of Roy with an impedance-matching circuit electrically positioned between the first electrical structure and a power amplifier die as taught by Kim because Kim states, “The ability to provide a substrate with several capacitor devices and/or inductors allows better impedance matching and thus provides better and improved signal filtering across a wider range of frequencies (e.g., broadband filtering).” [paragraph 0028].
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jensen et al. and further in view of Frenette et al. (US PG. Pub. 2017/0301653).
Regarding claim 10 – Jensen teaches the circuit package of claim 9, but fails to teach further comprising a power amplifier positioned in the first die.
Frenette teaches a power amplifier positioned in the first die ([Abstract] Frenette states, “a second die that includes at least a power amplifier”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit package having a first die as taught by Jensen with a power amplifier positioned in the first die as taught by Frenette because Frenette states, “a second die that includes at least a power amplifier for amplifying a radio frequency input signal” [Abstract]. A power amplifier will improve signal integrity in wireless communications.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jensen et al in view of Roy et al.
Regarding claim 11 – Jensen teaches the circuit package of claim 9, but fails to explicitly teach wherein the first coupler is electrically parallel to the second coupler.
Roy teaches a circuit package (figs. 1 & 5D) having a first coupler (fig. 5D, [paragraph 0040] Roy states, “metal layers 1-6 in the PCB 490”) and a second coupler (424 [paragraph 0034] Roy states, “inner metal layer 424”) wherein the first coupler is electrically parallel to the second coupler ([paragraph 0029] Roy states, “The PCB 120 also has a parallel impedance path…The package 130 also includes an OPD 150 as discussed above. The OPD 150 is part of a parallel impedance path…The die 140 has a bump resistance 142 and parallel impedance path”; figure 1 shows the PCB, Package and Die being “electrically parallel” to each other).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit package having a first and second coupler in a first and second die as taught by Jensen with the first and second coupler being electrically parallel to each other as taught by Roy because Roy states, “It will be appreciated that voltage droop is proportional to the impedance of the PDN. The voltage droop can be significantly improved using various aspects disclosed herein…allows for tuning the impedance of individual devices to reduce the impedance at the resonant frequencies (see, e.g., FIG. 3). This reduces the voltage drop and noise in the power distribution network.” [paragraph 0033 & 0041]. Additionally a parallel arrangement between the first and second coupler allows for consistent voltage across components and improved reliability.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al. (US PG. Pub. 2021/0013138) discloses a stacked die semiconductor package.
Lee et al. (US PG. Pub. 2004/0251529) discloses a multi-chip Ball Grid Array Package.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN T SAWYER whose telephone number is (571)270-5469. The examiner can normally be reached M-F 8:30 am - 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 5712722342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/STEVEN T SAWYER/Primary Examiner, Art Unit 2847
Prosecution Insights