DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamamoto et al. (US 2007/0115062).
In regard to Claim 1:
Yamamoto discloses, in Figure 1, a power amplification device, comprising:
a power node (Vc2 node) configured to receive a power voltage (Vc2);
a power amplifier (Tr2) that includes a power amplifier input (Tr2 base) configured to receive a radio frequency (RF) input signal (RFin); and
a bias circuit comprising:
a feedback circuit (Trb4) configured to receive a feedback input voltage (Vbo fed back to Trb4) that indicates a bias voltage (Vbo) applied to the power amplifier input of the power amplifier (Tr2 base) and to receive a reference voltage (Vrefb);
a bias node (Vbo node) coupled to the power amplifier input (Tr2 base), wherein the bias voltage (Vbo) applied to the power amplifier input (Tr2 base) is generated at the bias node (Vbo node);
a bipolar junction transistor (BJT) (Trb2) in a common emitter configuration (Trb2 and Rbb5 are a common emitter), wherein the BJT includes a base connected to receive a control voltage (Trb4 output) from the feedback circuit (Trb2 base receives voltage from Trb4 via Trb3), an emitter (Trb2 emitter), and a collector (Trb2 collector), wherein the collector is coupled to the bias node (Trb2 collector is connected to Vbo);
a resistor (Rbb22) connected between the power node (Vc2) and the bias node (Vb0); and
wherein the feedback circuit (Trb4) is configured to generate the control voltage (Trb4 output) such that the bias voltage (Vbo) is set in accordance with the reference voltage (Vrefb).
In regard to Claim 2:
Yamamoto discloses, in Figure 1, the power amplification device of claim 1, wherein an input voltage (voltage at Tr2 base) is generated from the bias voltage (Vbo) generated at the bias node (Vbo node) and the RF input signal (RFin) applied to the power amplifier input (Tr2 base).
In regard to Claim 3:
Yamamoto discloses, in Figure 1, the power amplification device of claim 1, wherein the emitter is connected to ground (Trb2 emitter is connected to ground).
In regard to Claim 11:
Yamamoto discloses, in Figure 1, the power amplification device of claim 1, further comprising a base-emitter voltage level (VBE) multiplying circuit (Vrefb generator (not shown)) configured to generate the reference voltage (Vrefb2) as a temperature dependent reference voltage (¶ 0014).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4-5, 14-15, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al. (US 2007/0115062), in view of Newman et al. (US 6,809,593).
In regard to Claim 4:
Yamamoto discloses, in Figure 1, wherein: the power amplifier is a Bipolar Transistor (300) having a second base (300 base), a second emitter (300 emitter), and a second collector; the base is a first base (Trb2 base), the emitter is a first emitter (Trb2 emitter), and the collector is a first collector (Trb2 collector); the power amplifier input is the second base (Tr2 base); and the bias circuit is configured to receive a regulated voltage (Vrefb).
Yamamoto does not disclose wherein: the power amplifier is a Heterojunction Bipolar Transistor (HBT); and the regulated voltage is between 1.8 Volts and 2.7 Volts.
Newman discloses, in Figure 3, wherein: the power amplifier is a Heterojunction Bipolar Transistor (HBT) (300, Column 2: lines 41-42); and the regulated voltage is between 1.8 Volts and 2.7 Volts (Column 1: lines 60-67).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively field to use the Heterojunction Bipolar Transistor taught by Newman with the bias circuit and amplifier taught by Yamamoto, in order to utilize the high power density and reduced die size of the heterojunction bipolar transistor (Newman Column 1: lines 21-22).
In regard to Claim 5:
Newman further discloses, in Figure 3, wherein the feedback circuit comprises a differential amplifier (360) configured to receive the feedback input voltage (352) and the reference voltage (310 output), wherein the differential amplifier (360) is further configured to generate the control voltage (350) such that the bias voltage (353) is set in accordance with the reference voltage (310 output, Column 3: lines 12-20).
In regard to Claim 14:
Yamamoto discloses, in Figure 1, a power amplification device, comprising: a power node (Vc2 node) configured to receive a power voltage (Vc2); a Bipolar Transistor (BT) (Tr2) that includes a first base (Tr2 base) configured to receive a radio frequency (RF) input signal (RFin), a first collector (Tr2 collector) configured to output an RF output signal (RFout), and a first emitter (Tr2 emitter) connected to ground (ground); and a bias circuit comprising: a feedback circuit (Trb4) configured to receive a feedback input voltage (Vbo fed back to Trb4) that indicates a bias voltage (Vbo) applied to the first base of the BT (Tr2 base) and to receive a reference voltage (Vref2); a resistor (Rbb22) coupled to the power node (Vc2); a bipolar junction transistor (BJT) (Trb2) in a common emitter configuration (Trb2 and Rbb5 are a common emitter), wherein the BJT (Trb2) includes a second base (Trb2 base) connected to receive a control voltage (Trb4 output) from the feedback circuit (Trb2 base receives voltage from Trb4 via Trb3), a second emitter coupled to the ground (Trb2 emitter connected to ground), and a second collector (Trb2 collector), wherein the second collector (Trb2 collector) and the resistor (Rbb22) are connected to apply the bias voltage (Vbo) to the first base (Tr2 base); and wherein the feedback circuit (Trb4) is configured to generate the control voltage (Trb4 output) such that the bias voltage (Vbo) is set in accordance with the reference voltage (Vrefb).
Yamamoto does not disclose a Heterojunction Bipolar Transistor (HBT).
Newman discloses, in Figure 3, a Heterojunction Bipolar Transistor (HBT) (300, Column 2: lines 41-42).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively field to use the Heterojunction Bipolar Transistor taught by Newman with the bias circuit and amplifier taught by Yamamoto, in order to utilize the high power density and reduced die size of the heterojunction bipolar transistor (Newman Column 1: lines 21-22).
In regard to Claim 15:
Newman further discloses, in Figure 3, wherein the feedback circuit comprises a differential amplifier (360) configured to receive the feedback input voltage (352) and the reference voltage (310 output), wherein the differential amplifier (360) is further configured to generate the control voltage (350) such that the bias voltage (353) is set in accordance with the reference voltage (310 output, Column 3: lines 12-20).
In regard to Claim 20:
Newman further discloses, in Figure 3, wherein the bias circuit is configured to receive a regulated voltage (310 output) and the regulated voltage is between voltage of the HBT is between 1.8 Volts and 2.7 Volts (Column 1: lines 60-67).
Allowable Subject Matter
Claims 6-10, 12-13, and 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In regard to Claim 6:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
further comprising: a second resistor connected between the power node and a feedback input node, wherein the differential amplifier is configured to receive the feedback input voltage at the feedback input node and wherein the resistor is a first resistor; and a second BJT having a second base, a second collector, and a second emitter, wherein: the base is a first base, the collector is a first collector, and the emitter is a first emitter; the second base is coupled to the first base; the second collector is connected to the feedback input node; and the second emitter is connected to ground.
In regard to Claim 8:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein the BJT is a first BJT, the base is a first base, the emitter is a first emitter, and the collector is a first collector, and wherein the differential amplifier comprises: a second BJT and a third BJT that form a differential pair; the second BJT has a second base that is configured to receive the feedback input voltage, a second collector that is coupled to the power node, and a second emitter that is connected to a differential pair biasing node that receives a second bias voltage, the bias voltage being a first bias voltage; and the third BJT has a third base that is configured to receive the reference voltage, a third collector that is coupled to the power node, and a third emitter that is connected to the differential pair biasing node that receives the second bias voltage.
In regard to Claim 12:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein the resistor is a first resistor, the BJT is a first BJT, the base is a first base, the collector is a first collector, the emitter is a first emitter, and wherein the VBE multiplying circuit comprises: a second resistor; a third resistor; a second BJT having a second base, a second collector, and a second emitter; and wherein: the second collector is connected to the feedback circuit such that the reference voltage is generated at the second collector; the second resistor is connected between the second collector and the second base; and the third resistor is connected between the second base and ground.
In regard to Claim 16:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
further comprising: a second resistor connected between the power node and a feedback input node, wherein the differential amplifier is configured to receive the feedback input voltage at the feedback input node and wherein the resistor is a first resistor; and a second BJT having a third base, a third collector, and a third emitter, wherein: the third base is coupled to the first base; the third collector is connected to the feedback input node; and the third emitter is connected to the ground.
In regard to Claim 17:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein a dominant pole filter is connected between a third base and a power amplifier input.
In regard to Claim 18:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein the BJT is a first BJT and wherein the differential amplifier comprises: a second BJT and a third BJT that form a differential pair; the second BJT has a third base that is configured to receive the feedback input voltage, a third collector that is coupled to the power node, and a third emitter that is connected to a differential pair biasing node that receives a second bias voltage, the bias voltage being a first bias voltage; and the third BJT has a fourth base that is configured to receive the reference voltage, a fourth collector that is coupled to the power node and a fourth emitter that is connected to the differential pair biasing node that receives the second bias voltage.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Linwinski (US 2002/0186084) discloses a transistor bias circuit that is capable of operating from a power supply voltage that is slightly higher than twice the base-emitter voltage of the transistor to be biased. The bias circuit includes a transistor connected in a current-mirror configuration with the transistor to be biased. A feedback circuit maintains the mirrored current at a constant level. The gain of the feedback circuit is improved by the addition of a non-inverting amplifier within the feedback circuit.
Ding (US 2020/0313626) discloses a power amplifier circuit includes a first transistor, a second transistor and a bias circuit. The first transistor has a base configured to receive a first signal. The second transistor has an emitter connecting to a collector of the first transistor and a collector configured to output a second signal. The bias circuit is coupled to the first transistor and the second transistor. The bias circuit is configured to provide a direct current (DC) voltage at the collector of the second transistor about twice a DC voltage at the collector of the first transistor. The bias circuit is configured to provide an alternating current (AC) or radio frequency (RF) voltage at the collector of the second transistor about twice an AC or RF voltage at the collector of the first transistor.
Johnson et al. (US 6,842,075) discloses a transistor bias circuit that is capable of operating from a power supply voltage that is slightly higher than twice the base-emitter voltage of the transistor to be biased. The bias circuit includes a transistor connected in a current-mirror configuration with the transistor to be biased. A feedback circuit maintains the mirrored current at a constant level. The gain of the feedback circuit is improved by the addition of a non-inverting amplifier within the feedback circuit.
Noh et al. (US 7,005,923) discloses an adaptive bias circuit is provided for an amplifier module including a RF power amplifier for amplifying an input signal to generate an output signal, wherein the bias circuit receives the input signal to adjust a driving current to control a quiescent current of the RF power amplifier.
Li et al. (US 9,800,205) discloses a power amplifier circuit including a power transistor, a variable impedance circuit, first and second envelope detecting circuits is provided. The power transistor receives an input signal and outputs an output signal. The variable impedance circuit includes an impedance control transistor and a first filter capacitor. An equivalent impedance of the variable impedance circuit varies with the input signal.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOHN W POOS/Primary Examiner, Art Unit 2843
