DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on 08/22/24 has been considered by the examiner.
Specification
3. The disclosure is objected to because of the following informalities: on the last line of page 4, the word --an-- should be inserted after “of”. On the first line of page 7, “a LC” should be changed to --an LC--, and on the last line of paragraph [0024], the word “can” should be deleted (or, alternatively, the word “turns” should be changed to --turn--. On the penultimate line of paragraph [0025], “of a” should be changed to --the--. On the second line of paragraph [0029], the second occurrence of the word “an” should be changed to --the--. On line 5 of paragraph [0031], the word “and” should be deleted and replaced with a comma, and note that the same change should also be made on line 6 of this paragraph, before the word “consequently”, and again on line 7 of this paragraph, after the word “formed”. On the penultimate line of paragraph [0032], the second occurrence of the word “and” should again be changed to a comma. On the penultimate line of paragraph [0033], “can be” should be changed to either --is--, or --will be--. On the penultimate line of paragraph [0036], the word “which” should be changed to
--when--.
Appropriate correction is required.
Claim Objections
4. Claim 10 is objected to because of the following informalities:
On the second line of claim 10, “of a” should be changed to --the--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Deng et al (USP 12,580,541) in view of Rajendran et al (USP 8,483,627).
As to claim 1, Deng et al discloses, in figure 4,
a radio frequency power amplifier (RFA) including:
an n-type common-source amplifier NCSA (the claimed NCSA is the combination of transistors MN1 and MN2) used to convert a first voltage signal (the recitation of the first voltage signal is just a statement of intended use—because the input signals of the claimed amplifier are not components of the amplifier but rather what the claimed amplifier receives use—however, the claimed first voltage signal can be read on differential input signal VIN shown in figure 4 of Deng et al) into a first current signal (the claimed first current signal is the current signal flowing through transistor MN1 and/or MN2);
an n-type common-gate amplifier NCGA (the claimed NCGA is the combination of transistors MN3 and MN4) relaying the first current signal into a second current signal (the claimed second current signal is the current signal flowing through transistor MN3 and/or MN4) directed to an output node (the claimed output node is the output node at the common drain terminals of transistors MP3 and MN3 and/or the output node at the common drain terminals of transistors MP4 and MN4) based on a first bias voltage (the claimed first bias voltage is again just a statement of intended use but note that it can be read on the bias voltage which is applied to the gate terminals of transistors MN3 and/or MN4);
a p-type common-source amplifier PCSA (the claimed PCSA is the combination of transistors MP1 and MP2) powered by a first power supply (the claimed first power supply is again just a statement of intended use but note that the first power supply is VDD in figure 4 of Deng et al) to convert a second voltage signal (the claimed second voltage signal is again just a statement of intended use but note that the second voltage signal can also be read on VIN being applied to the gate terminals of transistors MP1 and MP2) into a third current signal (the claimed third current signal is the current flowing through transistor MP1 and/or MP2);
a p-type common-gate amplifier PCGA (the claimed PCGA is the combination of transistors MP3 and MP4) relaying the third current signal into a fourth current signal (the claimed fourth current signal is the current signal flowing through transistor MP3 and/or MP4) directed to the output node based on a second bias voltage (the second bias voltage is again just a statement of intended use but note that the second bias voltage is the bias voltage received at the gate terminals of transistor MP3 and/or MP4); and
an inductor (the left coil within dashed box 130) attached to the output node,
wherein the first voltage signal and the second voltage signal have the same frequency and phase and approximately the same amplitude (again, the claimed first and second voltage signals are just intended use recitations but note that VIN is applied to the gate terminals of both of Deng et al’s NCSA and PCSA).
Not disclosed by Deng et al are the limitations that the inductor features a center tap linked to a central node, and in a high-power mode, the central node has a high impedance, while in a low-power mode, the second bias voltage is set to a level that turns off the PCGA, and the central node has a low impedance and a DC voltage of a second power supply.
Rajendran et al discloses, in figures 5 and 6, an inductor (the bottom inductor within box 114) attached to an output node of a radio frequency power amplifier and featuring a center tap (the center tap of the above-noted inductor which is coupled to either VDD or GND via switch S1) linked to a central node (the claimed central node is the node at either VDD or GND), and in a high-power mode (the PA mode), the central node has a high impedance (in Rajendran et al’s PA mode, the above-noted central node is the VDD node and it will have a high impedance), while in a low-power mode (i.e., the LNA mode), the second bias voltage is set to a level that turns off the PCGA (in Rajensran et al’s LNA mode, the bias voltage applied to the gate terminals of cascode transistors 144 and 148 is GND), and the central node has a low impedance and a DC voltage of a second power supply (when the above-noted central node is the GND node, it will have a low impedance and a DC voltage of GND).
It would have been obvious to one of ordinary skill in the art before the effective filing date of applicant’s invention to have combined the above-noted teachings of Deng et al and Rajendran et al so that Deng et al’s inductor features a center tap linked to a central node wherein in a high-power mode, the central node has a high impedance, while in a low-power mode, the second bias voltage is set to a level that turns off the PCGA, and the central node has a low impedance and a DC voltage of a second power supply, the motivation for such a combination being to obtain the advantages taught by Rajendran et al, i.e., the ability to simplify the structure shown in Rajendran et al’s figure 1 by utilizing the same amplifier circuit for both the high-power (TX) and low-power (Rx) modes in Deng et al.
As to claim 2, again the recitation of the first and second voltage signals are just intended use recitations, i.e., they are not components of the claimed radio frequency power amplifier, and therefore the recitation that these two signals are coupled via a capacitor likewise cannot be relied upon to distinguish over Deng et al as modified above using the teachings of Rajendran et al.
As to claim 10, note that the DC level of the above-noted second power supply GND is not higher than half the DC level of the first power supply VDD.
6. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Deng et al (USP 12,580,541) in view of Rajendran et al (USP 8,483,627), as applied to claim 1 above, and further in view of Butler (USPAP 2009/0108906).
Deng et al as modified above using the teachings of Rajendran et al does not disclose that the above-noted first and second voltage signals are AC coupled from an input voltage signal using an AC coupling network.
Butler discloses, in figure 1, and amplifier circuit (150) which includes a differential pair structure (151), wherein the differential pair structure receives a pair of differential input signals (In1 and In2) which are AC coupled to the differential pair.
It would have been obvious to one of ordinary skill in the art before the effective filing date of applicant’s invention to have combined such a teaching by Butler with the radio frequency amplifier circuitry of Deng et al in order to obtain the well-known advantages associated with AC coupling a differential input signal to a pair of differentially connected transistors, i.e., to block DC voltage of the inputs while allowing the AC signals to pass through the AC coupling network, in order to prevent unwanted DC voltage from being passed between the input circuitry and the differential amplifier circuitry.
Allowable Subject Matter
7. Claims 4-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the prior art of record discloses or suggests the radio frequency amplifier of claim 3 with the further limitation that the AC coupling network comprises a trifilar transformer, nor does any of the prior art of record disclose or suggest the radio frequency amplifier of claim 1 with the further limitations of a bias network configured as recited in claim 6, nor does any of the prior art of record disclose or suggest the radio frequency amplifier of claim 1 with the further limitations of a current to voltage converter including first and second NMOS transistors configured as recited in claim 9. Claim 5 is allowable in view of its dependency on allowable claim 4, claims 7 and 8 are allowable in view of their dependencies on allowable claim 6.
Prior Art Not Relied Upon
8. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Figure 5 of Singhal et al (USPAP 2024/0063759) discloses another example of grounding the gate terminals of a pair of cascode transistors (transistors Mcas1 and Mcas2) in a radio frequency amplifier when the amplifier is in the low-power, i.e., Rx, mode.
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH B WELLS whose telephone number is (571)272-1757. The examiner can normally be reached Monday-Friday, 8:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, REGIS J BETSCH, can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH B WELLS/Primary Examiner, Art Unit 2836 August 17, 2026
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