DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Upon further consideration of previously objected claim 9, the objection is withdrawn and a rejection is made in view of U.S. Patent No. 11,233,966 ("Niclass").
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication No. 2019/0189827 ("Haraguchi") in view of U.S. Patent No. 11,233,966 ("Niclass").
Regarding claim 9, Haraguchi discloses a light detecting device, comprising:
a first pixel circuitry (203, Fig. 3) including a first avalanche photodiode (302, Fig. 3) and a first inverter (304, Fig. 3), the first pixel circuitry configured to output a first output signal (PLS, Fig. 3); and
a second pixel circuitry including a second avalanche photodiode and a second inverter (see Fig. 2, a plurality of pixels, each having the same circuitry illustrated in Fig. 3), the second pixel circuitry configured to output a second output signal (PLS, Fig. 3); and
control circuitry (205, Fig. 3, paragraph [0063]) configured to receive the second output signal (PLS, Fig. 3), wherein an output (PDEF, Fig. 3) of the control circuitry (205, Fig. 3) is coupled to an anode of the first avalanche photodiode (anode of 302, Fig. 3) and an anode of the second avalanche photodiode (anode of 302, Fig. 3, paragraphs [0051], [0053]).
Haraguchi does not disclose that the second pixel circuitry includes a sample and hold circuit.
However, Niclass discloses the second pixel circuitry (see 300, Fig. 3A) includes a sample and hold circuit (308, Figs. 3A-3B, col. 6, lines 15-24).
It would have been obvious to one of ordinary skill in the art before the effective filing date to include a sample and hold circuit as disclosed by Niclass in the device of Haraguchi in order to store a sample of the cathode voltage until it can be readout.
Regarding claim 10, Haraguchi in view of Niclass discloses the light detecting device according to claim 9, and Niclass further discloses that the sample and hold circuit (308, Figs. 3A-3B) is connected to a cathode of the second avalanche photodiode (see Fig. 3A).
It would have been obvious to one of ordinary skill in the art before the effective filing date to include a sample and hold circuit coupled to the cathode of the second avalanche photodiode as disclosed by Niclass in the device of Haraguchi in order to store a sample of the cathode voltage until the pixel can be readout.
Regarding claim 2, Haraguchi in view of Niclass discloses the light detecting device according to claim 9, and Haraguchi further discloses the control circuitry (205, Fig. 3) is configured to control a potential of the anode of the first avalanche photodiode (PDEF level controls linear or avalanche mode, paragraphs [0056], for example, first avalanche photodiode can be any of the normal pixels, see paragraph [0054]) and a potential of the anode of the second avalanche photodiode (paragraph [0056]) based on the output of the second pixel circuitry (paragraph [0056], PDEF control signal is sent to both first and second avalanche photodiodes based PLS exceeding a threshold value, those pixels exceeding the threshold are interpreted to be the second pixel circuitry, see paragraph [0054]).
Allowable Subject Matter
Claims 6, 15-19, 21-22 are allowed.
The following is an examiner’s statement of reasons for allowance: The invention as claimed, specifically in combination with: the control circuitry includes an inter-pixel averaging section, and wherein the control circuitry further includes time averaging circuit, are not taught or made obvious by the prior art of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 3-5, 7-8, 11-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The invention as claimed, specifically in combination with: the control circuitry includes an inter-pixel averaging section; or the sample and hold circuit is connected to the cathode of the second avalanche photodiode by the buffer amplifier, are not taught or made obvious by the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MONICA T. TABA whose telephone number is (571)272-1583. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
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/MONICA T TABA/Examiner, Art Unit 2878
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