DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statement submitted on 08/22/2024 has been considered by the Examiner and made of record in the application file.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pehlke (US 20200350866 A1).
Consider claim 9, Pehlke discloses a radio frequency module (read as power amplifier module 1191 implemented using packaged module 900 and provided by envelop tracking module 1192, which together corresponds to a packaged RF amplifier module, figures 16A-16C, par [0181], [0182] and [0189]-[0190]) comprising:
a power amplifier (read as power amplifier module 1191 and the supporting figure 12 amplifier stages, where carrier amplifier stage 1132 and peaking amplification stage 1133 use bipolar transistor 1129 and 1130 to amplify RF signal RFIN and produce amplified RF signals, figures 12 and 16C, par [0152]-[0156] and [0190]);
a variable delay circuit disposed on a power providing path for providing the power supply voltage from the external connection terminal to the power amplifier (read as contact pads 932 receiving module supply voltages, envelope tracking module 1192 provides VCC-_PA to power amplifier module 1191, delay circuit 66 with a controllable delay line for supply volage VCC-, and delay circuit 1139 on the VCC-_PA route to peaking amplification stage 1133, which corresponds to placing an adjustable/variable delay component one the power feed from the module voltage entry toward the amplifier, figures 4, 12, 16B and 16C, par [0045], [0095]-[0096], [0152]-[0153], [0186] and [0190]),
wherein the variable delay circuit is configured to adjust a delay time of the power supply voltage (read as delay circuit 66 controlling the timing of supply voltage VCC- to peaking amplification stage 52, and the controllable delay line matching the supply timing to the RF branch timing, which corresponds to the adjustable timing amount for the power amplifier supply voltage, figure 4, par [0095]-[0096]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pehlke (US 20200350866 A1) in view of Singh (US 20160079971 A1).
Consider claim 1, Pehlke discloses a radio frequency module (read as power amplifier module 1191 implemented using packaged module 900 and provided by envelop tracking module 1192, which together corresponds to a packaged RF amplifier module, figures 16A-16C, par [0181], [0182] and [0189]-[0190]) comprising:
a power amplifier (read as power amplifier module 1191 and the supporting figure 12 amplifier stages, where carrier amplifier stage 1132 and peaking amplification stage 1133 use bipolar transistor 1129 and 1130 to amplify RF signal RFIN and produce amplified RF signals, figures 12 and 16C, par [0152]-[0156] and [0190]);
an external connection terminal configured to receive a power supply voltage that is output from a tracker module (read as contact pads 932 on packaged module 900 for routing supply voltages through connections 933, and envelope tracking module 1192 providing VCC-_PA to power amplifier module 1191; the contact pad 932 receiving that VCC-_PA feed is the external module voltage entry, figures 16B and 16C, par [0186] and [0190]); and
a delay circuit configured to control a delay for coupling the external connection terminal to the power amplifier, the delay being controllable (read as contact pads 932 receiving module supply voltages, envelope tracking module 1192 providing VCC-_PA to power module 1191, and delay circuit 66 with a controllable delay line for controlling timing of supply voltage VCC to peaking amplification stage 52; delay circuit 1139 on the VCC-_PA feed to peaking amplification stage 1133, figures 4, 12, 16B and 16C, par [0095]-[0096], [0152]-[0153], [0186] and [0190]).
However, Pehlke discloses the claimed invention above and controllable PA supply delay path (figures 4 and 12, par [0095]-[0096] and [0152]-[0153]) but does not specifically disclose a switch configured to perform switching of a selected path among a plurality of paths, and the plurality of paths having different delay times.
Nonetheless, Singh discloses selected delay paths, comprising the fine delay circuit 210 in which a input signal at IN enters fast delay path 215 and slow delay path 218; switches 225(1) to 225(6) and multiplexer 250 operate under delay controller 260, multiplexer 250 selects which path output is coupled to OUT, and capacitor C1 to C6 make the slow path slower so the controller can set different timing amounts from fastest to slowest with multiple delay values, figures 2-4, par [0026]-[0033] and [0042]).
Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Singh into the teachings of Pehlke, to configure Pehlke’s controllable PA supply delay path using Singh’s different controller selected fast and slow delay paths, in order to allow the power amplifier module, during supply timing alignment, to select desired delay among discreate supply delay paths and maintain the supply timing match to the RF branch timing (see par [0032] and [0076] of Singh).
Claims 2 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pehlke (US 20200350866 A1) in view of Singh (US 20160079971 A1), and in further view of Gamal El Din et al. (US 20170230028 A1).
Consider claim 2, as applied to claim 1 above, Pehlke, as modified by Singh, discloses the claimed invention above with switch selected delay paths (figures 2-4 and par [0031]-[0033] and [0042]) but does not specifically disclose wherein the switch is configured to perform the switching of the selected path based on a temperature.
Nonetheless, Gamal discloses multi-state phase shifter circuit 200 in which switch pairs Sna-Snb are controlled by switch control data through a lookup table or other mapping circuit, and the switch state would be automatically set in response to detected parameter including IC device temperature, which discloses using a temperature condition to control which switch state and corresponding path are selected, in an RF circuit environment that includes power amplifiers, figure 2A, par [0024], [0026] and [0066]-[0072].
Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Gamal into the teachings of Pehlke, which modified by Singh, to configure the switch selected PA supply delay path using Gamal’s temperature based switch state control, in order to allow the selected supply delay state to follow thermal operating changes using switch control data tied to detected device temperature (see par [0069]-[0070] and [0072] of Gamal).
Consider claim 4, as applied to claim 1 above, Pehlke, as modified by Singh, discloses the claimed invention above with wherein at least one of the plurality of paths includes delay gates (read as fine delay circuit 210 with selectable timing paths, including fast delay path 215 and slow delay path 218, where multiplexer 250 selects which path output reaches OUT, figures 2 and 3, par [0026]-[0027] and [0031]-[0033] of Singh) but does not specifically disclose wherein at least one of the plurality of paths is formed solely from a wiring conductor.
Nonetheless, Gamal selectable parallel path containing THRU conductor 204, which is simple wire, IC trace or similar conductor; switch pairs Sna-Snb place that onductor path in circuit between RF1 and RF2, which corresponds to a selected path implemented only by conductor material, figures 2A and 3, par [0024]-[0026] and [0030].
Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Gamal into the teachings of Pehlke, which modified by Singh, to configure the plural selectable delay paths using Gamal’s selectable THRU conductor path, in order to provide a low complexity selected path using a simple wire or IC trace where a minimal delay path is desired (see par [0024]-[0026] of Gamal).
Claim 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pehlke (US 20200350866 A1) in view of Singh (US 20160079971 A1), and in further view of Jeon (US 20020097095 A1).
Consider claim 3, as applied to claim 1 above, Pehlke, as modified by Singh, discloses the claimed invention above with the switch is configured to perform the switching of the selected path (figures 2-4, par [0026]-[0033] and [0042] of Singh) but does not specifically disclose a temperature sensor, wherein the switch is configured to perform the switching of the selected path based on a temperature measured by the temperature sensor.
Nonetheless, Jeon discloses thermistor TH as temperature sensor in a temperature compensation circuit for power amplifier, with the thermistor responding to ambient temperature, which provides the temperature responsive sensing structure, figures 6 and 7, par [0031]-[0036].
Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Jeon into the teachings of Pehlke, which modified by Singh, to configure the delay paths switching for PA using Jeon’s thermistor temperature sensor for PA, in order to allow the power amplifier module to use temperature responsive resistance in the amplifier voltage path to maintain PA operating characteristics during temperature variation (see par [0035]-[0036] of Jeon).
Claims 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pehlke (US 20200350866 A1) in view of Singh (US 20160079971 A1), and in further view of Goetting et al. (US 6204710 A1).
Consider claim 5, as applied to claim 1 above, Pehlke, as modified by Singh, discloses the claimed invention above with delay path circuit but does not specifically disclose a delay circuit that is disposed on at least one of the plurality of paths, the delay circuit including an RC circuit having a resistor and a capacitor.
Nonetheless, Goetting discloses delay element 510-_0 formed as an RC circuit with resistor 611 and capacitor 618; the resistor and capacitor set charging and discharging time sued as the trim delay, which corresponds to resistor and capacitor delay structure, figure 6A, col. 5 with line 37 to col. 6 with line 14.
Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Goetting into the teachings of Pehlke, which modified by Singh, to configure the selected delay path circuit using Goetting’s RC delay element, in order to set path delay through a resistor-capacitor time constant to achieve simplicity and reduce cost.
Consider claim 6, as applied to claim 1 above, Pehlke, as modified by Singh, discloses the claimed invention above with multipole selectable delay paths (figure 2, par [0026], [0031] and [0032]) but does not specifically disclose further comprising a plurality of delay circuits that are respectively disposed on a corresponding one of the plurality of paths.
Nonetheless, Goetting discloses trim circuit 550a and trim circuit 550b, each using multiple delay elements 510-_0 to 510_N-1 that produce corresponding delayed outputs; each branch from T_IN through a corresponding delay element 510_X to multiplexer 550 is a corresponding delay path, and multiplexer 550 selects one delayed output as T_OUT, which corresponds to plural delay elements on corresponding selected branches, figures 5A and 5B, col. 3 with line 64 to col. 4 with line 24, col. 4 with lines 50-67.
Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Goetting into the teachings of Pehlke, which modified by Singh, to configure the multiple selectable delay paths using Goetting’s plural delay elements and multiplexer, in order to obtained desired delay by selecting from multiple discrete delayed outputs with defined timing values.
Consider claim 7, as applied to claim 6 above, Pehlke, as modified by Singh and Goetting, discloses the claimed invention above with delay path circuit but does not specifically disclose wherein each of the plurality of delay circuits includes an RC circuit having a resistor and a capacitor.
Nonetheless, Goetting discloses delay element 510-_0 formed as an RC circuit with resistor 611 and capacitor 618; the resistor and capacitor set charging and discharging time sued as the trim delay, which corresponds to resistor and capacitor delay structure, figure 6A, col. 5 with line 37 to col. 6 with line 14.
Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Goetting into the teachings of Pehlke, which modified by Singh and Goetting, to configure the selected delay path circuit using Goetting’s RC delay element, in order to set path delay through a resistor-capacitor time constant to achieve simplicity and reduce cost.
Claim 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pehlke (US 20200350866 A1) in view of Jeon (US 20020097095 A1).
Consider claim 8, Pehlke discloses a radio frequency module (read as power amplifier module 1191 implemented using packaged module 900 and provided by envelop tracking module 1192, which together corresponds to a packaged RF amplifier module, figures 16A-16C, par [0181], [0182] and [0189]-[0190]) comprising:
a power amplifier (read as power amplifier module 1191 and the supporting figure 12 amplifier stages, where carrier amplifier stage 1132 and peaking amplification stage 1133 use bipolar transistor 1129 and 1130 to amplify RF signal RFIN and produce amplified RF signals, figures 12 and 16C, par [0152]-[0156] and [0190]);
an external connection terminal configured to receive a power supply voltage that is output from a tracker module (read as contact pads 932 on packaged module 900 for routing supply voltages through connections 933, and envelope tracking module 1192 providing VCC-_PA to power amplifier module 1191; the contact pad 932 receiving that VCC-_PA feed is the external module voltage entry, figures 16B and 16C, par [0186] and [0190]); and
a delay circuit that is disposed on a path connecting the external connection terminal and the power amplifier (read as contact pads 932 routes supply voltages, envelope tracking module 1192 providing VCC-_PA to power amplifier circuit 1191, and delay circuit 1139 located on the VCC-_PA feed to peaking amplification stage 1133, which corresponds to a component on the voltage path from the module supply entry to the amplifier, figures 12, 16B and 16C, par [0152]-[0153], [0186] and [0190])
However, Pehlke discloses the claimed invention above and VCC-_PA voltage path but does not specifically disclose a thermistor that is disposed on a path connecting the external connection terminal and the power amplifier.
Nonetheless, Jeon discloses thermistor TH in a temperature compensated power amplifier, where thermistor TH is connected between supply voltage node Vt and bias voltage node Vref, and Vref provides voltage to the bias circuit of the power amplifier, which corresponds to the temperature responsive resistor on a voltage path leading to the amplifier, figures 6 and 7, par [0031]-[0036].
Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Jeon into the teachings of Pehlke, to configure VCC-_PA voltage path using Jeon’s thermistor TH voltage compensation, in order to allow the power amplifier module to use temperature responsive resistance in the amplifier voltage path to maintain PA operating characteristics during temperature variation (see par [0035]-[0036] of Jeon).
Claim 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pehlke (US 20200350866 A1) in view of Drogi (US 20140235185 A1).
Consider claim 10, as applied to claim 9 above, Pehlke discloses wherein the variable delay circuit is configured to adjust the delay time (read as delay circuit 66 with a controllable delay line for adjusting timing of supply voltage VCC, and delay circuit 1139 on the VCC_PA feed to peaking amplification stage 1133, figures 4 and 12, par [0095]-[0096] and [0152]-[0153]) but does not specifically disclose adjust the delay time based on a temperature.
Nonetheless, Drogi discloses an envelope tracking power amplifier, comprising delay determiner 144 using calibration control signal 145 carrying temperature information and using measured conditions including temperature to select stored delay values for calibrating delay blocks 122 and 134, which corresponds to temperature based adjustment of delay in an envelope tracking power amplifier system, figure 1, part [0029] and [0047].
Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Drogi into the teachings of Pehlke, to configure the controllable PA supply6 delay circuit using Drogi’s temperature based delay calibration, in order to compensate supply delay under temperature dependent operating conditions in an envelope tracking power amplifier (see par [0029] and [0047] of Drogi).
Claim 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pehlke (US 20200350866 A1) in view of Drogi (US 20140235185 A1), and in further view of Jeon (US 20020097095 A1).
Consider claim 11, as applied to claim 9 above, Pehlke discloses a temperature sensor, wherein the variable delay circuit is configured to adjust the delay time (read as delay circuit 66 with a controllable delay line for adjusting timing of supply voltage VCC, and delay circuit 1139 on the VCC_PA feed to peaking amplification stage 1133, figures 4 and 12, par [0095]-[0096] and [0152]-[0153]) but does not specifically disclose adjust the delay time based on a temperature.
Nonetheless, Drogi discloses an envelope tracking power amplifier, comprising delay determiner 144 using calibration control signal 145 carrying temperature information and using measured conditions including temperature to select stored delay values for calibrating delay blocks 122 and 134, which corresponds to temperature based adjustment of delay in an envelope tracking power amplifier system, figure 1, part [0029] and [0047].
Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Drogi into the teachings of Pehlke, to configure the controllable PA supply6 delay circuit using Drogi’s temperature based delay calibration, in order to compensate supply delay under temperature dependent operating conditions in an envelope tracking power amplifier (see par [0029] and [0047] of Drogi).
However, Pehlke, as modified by Drogi, discloses the claimed invention above with temperature controllable supply delay but does not specifically disclose temperature measured by the temperature sensor.
Nonetheless, Jeon discloses thermistor TH as temperature sensor in a temperature compensation circuit for power amplifier, with the thermistor responding to ambient temperature, which provides the temperature responsive sensing structure, figures 6 and 7, par [0031]-[0036].
Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Jeon into the teachings of Pehlke, which modified by Drogi, to configure the delay paths switching for PA using Jeon’s thermistor temperature sensor for PA, in order to allow the power amplifier module to use temperature responsive resistance in the amplifier voltage path to maintain PA operating characteristics during temperature variation (see par [0035]-[0036] of Jeon).
Claims 12, 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pehlke (US 20200350866 A1) in view of Goetting et al. (US 6204710 A1).
Consider claim 12, as applied to claim 9 above, Pehlke discloses wherein the variable delay circuit comprises delay circuit disposed on the power providing path for providing the power supply voltage from the external connection terminal to the power amplifier (read as contact pads 932 receiving supply voltage, envelope tracking module 1192 providing VCC_PA to power amplifier module 1191, and delay circuit 1139 on the VCC_PA route to peaking amplification stage 1133, while delay circuit 66 confirms a controllable delay line for the PA supply timing, figures 4, 12, 16B and 16C, par [0095]-[0096], [0152]-[0153] and [0186]) but does not specifically disclose that the variable delay circuit includes a switch configured to couple one of a plurality of delay circuits into the power providing path.
Nonetheless, Goetting discloses trim circuit 550a and trim circuit 550b, each using multiple delay elements 510-_0 to 510_N-1 that produce corresponding delayed outputs; each branch from T_IN through a corresponding delay element 510_X to multiplexer 550 is a corresponding delay path, and multiplexer 550 selects one delayed output as T_OUT, which corresponds to plural delay elements on corresponding selected branches, figures 5A and 5B, col. 3 with line 64 to col. 4 with line 24, col. 4 with lines 50-67.
Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Goetting into the teachings of Pehlke, to configure the multiple delay paths using Goetting’s plural delay elements and multiplexer, in order to obtained desired delay by selecting from multiple discrete delayed outputs with defined timing values.
Consider claim 14, as applied to claim 12 above, Pehlke, as modified by Goetting, discloses the claimed invention above with delay path circuit but does not specifically disclose wherein at least one of the plurality of delay circuits includes an RC circuit having a resistor and a capacitor.
Nonetheless, Goetting further discloses delay element 510-_0 formed as an RC circuit with resistor 611 and capacitor 618; the resistor and capacitor set charging and discharging time sued as the trim delay, which corresponds to resistor and capacitor delay structure, figure 6A, col. 5 with line 37 to col. 6 with line 14.
Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Goetting into the teachings of Pehlke, as modified by Goetting, to configure the selected delay path circuit using Goetting’s RC delay element, in order to set path delay through a resistor-capacitor time constant to achieve simplicity and reduce cost.
Consider claim 15, as applied to claim 12 above, Pehlke, as modified by Goetting, discloses the claimed invention above with delay path circuit but does not specifically disclose wherein at least one of the plurality of delay circuits includes an RC circuit having a resistor and a capacitor.
Nonetheless, Goetting discloses delay element 510-_0 formed as an RC circuit with resistor 611 and capacitor 618; the resistor and capacitor set charging and discharging time sued as the trim delay, which corresponds to resistor and capacitor delay structure, figure 6A, col. 5 with line 37 to col. 6 with line 14.
Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Goetting into the teachings of Pehlke, which modified by Goetting, to configure the selected delay path circuit using Goetting’s RC delay element, in order to set path delay through a resistor-capacitor time constant to achieve simplicity and reduce cost.
Claims 13, 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pehlke (US 20200350866 A1) in view of Goetting et al. (US 6204710 A1), and in further view of Gamal El Din et al. (US 20170230028 A1).
Consider claim 13, as applied to claim 12 above, Pehlke, as modified by Goetting, discloses wherein at least one of the plurality of delay circuits (read as trim circuit 550a and trim circuit 550b, each using multiple delay elements 510-_0 to 510_N-1 that produce corresponding delayed outputs; each branch from T_IN through a corresponding delay element 510_X to multiplexer 550 is a corresponding delay path, and multiplexer 550 selects one delayed output as T_OUT, which corresponds to plural delay elements on corresponding selected branches, figures 5A and 5B, col. 3 with line 64 to col. 4 with line 24, col. 4 with lines 50-67 of Goetting) but does not specifically disclose is formed solely from a wiring conductor.
Nonetheless, Gamal selectable parallel path containing THRU conductor 204, which is simple wire, IC trace or similar conductor; switch pairs Sna-Snb place that onductor path in circuit between RF1 and RF2, which corresponds to a selected path implemented only by conductor material, figures 2A and 3, par [0024]-[0026] and [0030].
Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Gamal into the teachings of Pehlke, which modified by Goeeting, to configure the plural selectable delay paths using Gamal’s selectable THRU conductor path, in order to provide a low complexity selected path using a simple wire or IC trace where a minimal delay path is desired (see par [0024]-[0026] of Gamal).
Consider claim 16, as applied to claim 12 above, Pehlke, as modified by Goetting, discloses wherein the plurality of delay circuits includes a first delay circuit (read as trim circuit 550a and trim circuit 550b, each using multiple delay elements 510-_0 to 510_N-1 that produce corresponding delayed outputs; each branch from T_IN through a corresponding delay element 510_X to multiplexer 550 is a corresponding delay path, and multiplexer 550 selects one delayed output as T_OUT, which corresponds to plural delay elements on corresponding selected branches, figures 5A and 5B, col. 3 with line 64 to col. 4 with line 24, col. 4 with lines 50-67 of Goetting) but does not specifically disclose the first delay circuit formed solely of a wiring conductor.
Nonetheless, Gamal selectable parallel path containing THRU conductor 204, which is simple wire, IC trace or similar conductor; switch pairs Sna-Snb place that onductor path in circuit between RF1 and RF2, which corresponds to a selected path implemented only by conductor material, figures 2A and 3, par [0024]-[0026] and [0030].
Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Gamal into the teachings of Pehlke, which modified by Goeeting, to configure the plural selectable delay paths using Gamal’s selectable THRU conductor path, in order to provide a low complexity selected path using a simple wire or IC trace where a minimal delay path is desired (see par [0024]-[0026] of Gamal).
Consider claim 17, as applied to claim 16 above, Pehlke, as modified by Goetting and Gamal, discloses wherein the plurality of delay circuits as above but does not specifically disclose includes at least a second delay circuit formed of a resistor and a capacitor
Nonetheless, Goetting further discloses delay element 510-_0 formed as an RC circuit with resistor 611 and capacitor 618; the resistor and capacitor set charging and discharging time sued as the trim delay, which corresponds to resistor and capacitor delay structure, figure 6A, col. 5 with line 37 to col. 6 with line 14.
Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Goetting into the teachings of Pehlke, which modified by Goetting and Gamal, to configure the selected delay path circuit using Goetting’s RC delay element, in order to set path delay through a resistor-capacitor time constant to achieve simplicity and reduce cost.
Claim 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pehlke (US 20200350866 A1) in view of Goetting et al. (US 6204710 A1), and in further view of Jeon (US 20020097095 A1).
Consider claim 18, as applied to claim 12 above, Pehlke, as modified by Goetting, discloses the claimed invention above but does not specifically disclose wherein the variable delay circuit comprises at least a thermistor configured to have a resistance changing with a temperature.
Nonetheless, Jeon discloses thermistor TH as temperature responsive resistance element, including NTC and PTC forms whose resistance changes with temperature, and further disclose the use of thermistor TH in a power amplifier voltage compensation circuit, figures 6 and 7, par [0031]-[0036].
Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Jeon into the teachings of Pehlke, which modified by Goetting, to configure the delay using Jeon’s thermistor with temperature responsive resistance, in order to allow the power amplifier module to use temperature responsive resistance in the amplifier voltage path to maintain PA operating characteristics during temperature variation (see par [0035]-[0036] of Jeon).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Junpeng Chen whose telephone number is (571) 270-1112. The examiner can normally be reached on Monday - Thursday, 8:00 a.m. - 5:00 p.m., EST.
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/Junpeng Chen/
Primary Examiner, Art Unit 2645
Prosecution Insights