DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 2, 3, 8-10, 15-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 13-18 and 24 of U.S. Patent No. 12,094,533. Although the conflicting claims are not identical, they are not patentably distinct from each other because claims 13-18 and 24 of U.S. Patent No. 12,094,533 are clearly anticipated or similar in scope to the rejected claims 2, 3, 8-10, 15-21 of the U. S. Pat. App (No. 18/812,133) with only obvious wording variations. For example below:
Instant application
Claim Number
U.S. Patent No. 12,094,533
Claim Number
2
13-17
3
17, 18
8
13-18
9
15-18
10
15-18
15
13-17
16
13-17
17
13-17
18
13-17
19
13-17
20
13-17
21
24
As shown in table above, the limitations in claims 2, 3, 8-10, 15-21 of pending Application can be found the limitations in claims 13-18 and 24 as indicated above of U.S. Patent No. 12,094,533. Thus, one of ordinary skill in the art before the effective filing date of the claimed invention would recognize that they are not patentably distinct from each other. Accordingly, claims 2, 3, 8-10, 15-21 of pending Application are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 13-18 and 24 of U.S. Patent No. 12,094,533 for the reasons as stated above.
Allowable Subject Matter
Claims 2-21 are allowed if they overcome the nonstatutory double patenting rejections above.
Claims 4-7 and 11-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, because the prior art of record fails to teach the limitation of claim 4 “further comprising: a sensing component; and a counter coupled with the sensing component and the first logic circuitry, the counter configured to: count, as part of the first phase of the read operation, a quantity of memory cells, from among the one or more arrays of memory cells, that is associated with a first logic state of a plurality of logic states as determined by the sensing component; and output an indication of the quantity to the first logic circuitry, wherein the first logic circuitry is configured to generate the first starting voltage based at least in part on the quantity.“; the limitation of claim 5 “further comprising: a sensing component configured to determine a plurality of logic states of memory cells in the one or more arrays of memory cells; and an error control component coupled with the sensing component, the error control component configured to: determine, as part of the first phase of the read operation, whether each logic state of the plurality of logic states as determined by the sensing component comprises an error; and increment a count in response to determining that a logic state of the plurality of logic states comprises the error, wherein the first logic circuitry is further configured to generate a first ending voltage of the first sequence of voltages based at least in part on the count. “; the limitation of claim 11 “further comprising: a sensing component configured to sense a plurality of logic states of memory cells included in the one or more arrays of memory cells; and a counter coupled with a sensing component and the first logic circuitry, the counter configured to: count, during the first phase of the read operation, a quantity of memory cells, from among the one or more arrays of memory cells, that is associated with a first logic state of the plurality of logic states as sensed by the sensing component; and output an indication of the quantity to the first logic circuitry, wherein the first logic circuitry is configured to generate the first starting voltage based at least in part on the quantity. “ and the limitation of claim 12 “further comprising: a sensing component configured to sense a plurality of logic states of memory cells included in the one or more arrays of memory cells; and an error control component coupled with the sensing component and configured to: determine, during the first phase of the read operation, whether each logic state of the plurality of logic states as sensed by the sensing component comprises an error; and increment a count in response to determining that a logic state of the plurality of logic states comprises the error, wherein the first logic circuitry is further configured to generate a first ending voltage of the first sequence of voltages based at least in part on the count.”. Therefore, the prior art teachings are neither anticipate nor render obvious the allowable subject matter in combination with the other claimed limitations.
Conclusion
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/TUAN D NGUYEN/Primary Examiner, Art Unit 2699
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