Response to Arguments
Applicant's arguments filed on 6/1/2026 have been fully considered but they are not persuasive.
First in regards to claims 1-11, Applicant argues Palaniappan (US Patent Pub. # 2020/0286945) in view of Ying (US Patent Pub. # 2004/0079977) references do not teach the limitation of “a first transistor connected in series to the FD and the reset transistor" (See Remarks, Pg 8 and 9). The Examiner respectfully disagrees. Specifically noting the Palaniappan reference teaches a first transistor (dual conversion gain transistor 120) connected in series to the FD (118) and the reset transistor (124) (Para 25 and 28). The floating diffusion region 118 is illustrated as a capacitor 118. The location 302 is the floating diffusion region in regards to ground. Therefore location 302 connects the three dual conversion gain transistor 120, reset transistor (124), and the FD (118) in series. Ying (Figs. 2B and 4) teaches a first transistor (variable capacitive load 202 (fig. 4 M9)) connected in series to the FD (node 103) and the reset transistor (transistor M1) (Para 5 and 24). Examiner analyzes the location 302 as the floating diffusion. For this reason, the Examiner believes that Kitazawa in view of Kingetsu does teach the limitation of claim 1 and the rejection to the claim will be set forth below.
In regards to claims 1-11, Applicant argues Palaniappan (US Patent Pub. # 2020/0286945) in view of Ying (US Patent Pub. # 2004/0079977) references do not teach the limitation of “transistor-controlled fourth capacity state" (See Remarks, Pg 9). The Examiner respectfully disagrees. Specifically noting the Ying teaches the variable capacitive load 202 can be increased by two discrete levels: capacitance C3 and capacitance C3+C5. If capacitor C3 is a different size from capacitor C5, the variable capacitive load 202 can be increased by three discrete levels: capacitance C3, capacitance C5, and capacitance C3+C5. This allows the conversion gain for the pixel to be changed in response to several different thresholds of light intensity. It is possible to have more than two legs in the variable capacitive load 202 (Para 26). Examiner analyzes the variable capacitive load 202 may have more than two legs so Ying can have “transistor-controlled fourth capacity state”. For this reason, the Examiner believes that Kitazawa in view of Kingetsu does teach the limitation of claim 1 and the rejection to the claim will be set forth below.
In regards to claims 1-11, Applicant argues Ying (US Patent Pub. # 2004/0079977) reference is directed to a variable capacitive load connected in parallel with a photodiode to vary conversion gain based on incident light intensity (See Remarks, Pg 9). The Examiner respectfully agrees. Palaniappan teaches a dual conversion gain transistor giving the floating diffusion a low and high gain (capacity) readout and Ying teaches a multiple conversion gain transistor. The claims as cited allow for a dual or multiple conversion gain transistor to be used. For this reason, the Examiner believes that Kitazawa in view of Kingetsu does teach the limitation of claim 1 and the rejection to the claim will be set forth below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over Palaniappan (US Patent Pub. # 2020/0286945) in view of Ying (US Patent Pub. # 2004/0079977).
As to claim 1, Palaniappan teaches an image sensor comprising:
a first photodiode (first photosensitive area 106 (PD_E1)) connected to a floating diffusion region (FD) (floating diffusion region 118) (Para 23);
a second photodiode (second photosensitive area 102 (PD_E2)) connected to the FD (118) (Para 23);
a reset transistor (reset transistor 124) connected to the FD (118) (Para 26);
a first transistor (dual conversion gain transistor 120) connected in series to the FD (118) and the reset transistor (124) (Para 25 and 28).
Palaniappan does not teach a second transistor connected in series to the FD and the reset transistor, a third transistor connected in series to the FD and the reset transistor, wherein the FD has a first capacity when the reset transistor, the first transistor, and the second transistor are off, wherein the FD has a second capacity when the first transistor is on, wherein the FD has a third capacity when the second transistor is on, wherein the FD has a fourth capacity when the third transistor is on, wherein the first capacity, the second capacity, the third capacity, and the fourth capacity are different from each other. Ying (Figs. 2B and 4) teaches a first transistor (transistor M7) connected in series to the FD (node 103) and the reset transistor (transistor M1) (Para 5 and 21); and a second transistor (variable capacitive load 202 (fig. 4 M9)) connected in series to the FD (103) and the reset transistor (M1) (Para 25 and 26), a third transistor (variable capacitive load 202 (fig. 4 M11)) connected in series to the FD (103) and the reset transistor (M1) (Para 25 and 26), wherein the FD (103) has a first capacity (node voltage) when the reset transistor (M1), the first transistor (M9), and the second transistor (M11) are off, wherein the FD (103) has a second capacity (C1) when the first transistor (M7) is on, wherein the FD (103) has a third capacity (C3) when the second transistor (M9) is on, wherein the FD (103) has a fourth capacity (C5) when the third transistor (M11) is on, wherein the first capacity (node voltage), the second capacity (C1), the third capacity (C3), and the fourth capacity (C5) are different (different size) from each other (Para 25 and 26). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have provided a variable capacitive load as taught by Ying to the dual conversion gain transistor of Palaniappan, to allows the conversion gain for the pixel to be changed in response to several different thresholds of light intensity (Para 26 of Ying).
As to claim 2, Ying teaches further comprising: a first capacitor (C3) connected to the first transistor (M9) and a second capacitor (C5) connected to the second transistor (M11) (Para 25 and 26).
As to claim 3, Ying teaches wherein: the reset transistor (transistor M1)is connected to a power supply voltage (supply voltage Vdd 107) (Para 6); the first capacitor (C1) is connected to a first terminal of the first transistor (M7) and a second terminal of the first transistor (M7) is connected to the FD (103); and the second capacitor (C3) is connected in series to the second transistor (M9) between the power supply voltage (107) and a ground voltage (ground) (Para 25 and 26).
As to claim 4, Ying teaches wherein: the FD (103) has the second capacity when the first transistor (M7) is on and the second (M9) and third transistors (M11) are off; the FD (103) has the third capacity when the first (M7) and second transistor (M9) are on and the third transistor (M11) is off; and the FD (103) has the fourth capacity when the first (M7), second (M9) and third transistors (M11) are on (Para 25 and 26).
As to claim 5, Ying teaches further comprising: a second capacitor (C3) connected to the second transistor (M9) (Para 25).
As to claim 6, Ying teaches wherein: the reset transistor (109) is connected to a power supply voltage (voltage supply Vdd 107); and a terminal of the second capacitor (C3) is connected to the power supply voltage (107) via the second transistor (M9) (Para 25 and 26).
As to claim 7, Ying teaches wherein: a first terminal of the reset transistor (109) is connected to a power supply voltage (107); and a terminal of the third capacitor (C5) is connected to a second terminal of the reset transistor (109) via the second transistor (M11) (Para 25 and 26).
As to claim 8, Palaniappan teaches further comprising: a first transfer transistor (transfer transistor 116) connected to the first photodiode (106) and the FD (118); and a second transfer transistor (transfer transistor 112) connected to the second photodiode (102) and the FD (118), wherein the first transfer transistor (116), the second transfer transistor (112), and the first transistor (120) are directly connected to the FD (118) (Para 23 and 25).
As to claim 9, Palaniappan teaches an image sensor comprising:
a first photodiode (first photosensitive area 106 (PD_E1)) connected to a floating diffusion region (FD) (floating diffusion region 118) via a first transfer transistor (transfer transistor 116) (Para 23);
a second photodiode (second photosensitive area 102 (PD_E2) connected to the FD (118) via a second transfer transistor (transfer transistor 112) (Para 25);
a reset transistor (reset transistor 124) connected to the FD (118) (Para 26);
a capacitor (dual conversion gain capacitor 122) connected to the FD (118) via a first transistor (transistor 120) (Para 25).
Palaniappan does not teach a second transistor connected in series to the FD and the reset transistor, a third transistor connected in series to the FD and the reset transistor, wherein the FD has a first capacity when the reset transistor, the first transistor, and the second transistor are off, wherein the FD has a second capacity when the first transistor is on, wherein the FD has a third capacity when the second transistor is on, wherein the FD has a fourth capacity when the third transistor is on, wherein the first capacity, the second capacity, the third capacity, and the fourth capacity are different from each other. Ying (Figs. 2B and 4) teaches a first transistor (transistor M7) connected in series to the FD (node 103) and the reset transistor (transistor M1) (Para 5 and 21); and a second transistor (variable capacitive load 202 (fig. 4 M9)) connected in series to the FD (103) and the reset transistor (M1) (Para 25 and 26), a third transistor (variable capacitive load 202 (fig. 4 M11)) connected in series to the FD (103) and the reset transistor (M1) (Para 25 and 26), wherein the FD (103) has a first capacity (node voltage) when the reset transistor (M1), the first transistor (M9), and the second transistor (M11) are off, wherein the FD (103) has a second capacity (C1) when the first transistor (M7) is on, wherein the FD (103) has a third capacity (C3) when the second transistor (M9) is on, wherein the FD (103) has a fourth capacity (C5) when the third transistor (M11) is on, wherein the first capacity (node voltage), the second capacity (C1), the third capacity (C3), and the fourth capacity (C5) are different (different size) from each other (Para 25 and 26). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have provided a variable capacitive load as taught by Ying to the dual conversion gain transistor of Palaniappan, to allows the conversion gain for the pixel to be changed in response to several different thresholds of light intensity (Para 26 of Ying).
As to claim 10, Palaniappan teaches wherein: the first transistor (120) is connected in series to the FD (118) and the reset transistor (124) (Para 25 and 28). The floating diffusion region 118 is illustrated as a capacitor 118. The location 302 is the floating diffusion region in regards to ground. Therefore location 302 connects the three dual conversion gain transistor 120, reset transistor (124), and the FD (118) in series.
As to claim 11, Ying teaches wherein: the second transistor (M9) is connected in series to the FD (103) and the reset transistor (109) (Para 24-26).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER K PETERSON whose telephone number is (571)270-1704. The examiner can normally be reached Monday-Friday 7AM-4PM.
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/CHRISTOPHER K PETERSON/
Primary Examiner, Art Unit 2637 6/13/2026
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