DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was filed with the application on 8/22/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 recites the limitation " a first transistor connected in series to the FD and the reset transistor" in line 7. This limitation is the same as the limitation in line 6. There is insufficient antecedent basis for this limitation in the claim.
Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted elements are: A capacitor connected to the first transistor. Claim omits the capacitor connected to the first transistor. Turning on and off a transistor does not add capacity to the floating diffusion region (FD). Examiner will reject claim 12 as analyzed in claims 1 and 9.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over Palaniappan (US Patent Pub. # 2020/0286945) in view of Ying (US Patent Pub. # 2004/0079977).
As to claim 1, Palaniappan teaches an image sensor comprising:
a first photodiode (first photosensitive area 106 (PD_E1)) connected to a floating diffusion region (FD) (floating diffusion region 118) (Para 23);
a second photodiode (second photosensitive area 102 (PD_E2)) connected to the FD (118) (Para 23);
a reset transistor (reset transistor 124) connected to the FD (118) (Para 26);
a first transistor (dual conversion gain transistor 120) connected in series to the FD (118) and the reset transistor (124) (Para 25 and 28).
Palaniappan does not teach a second transistor connected in series to the FD and the reset transistor, wherein the FD has a first capacity when the reset transistor, the first transistor, and the second transistor are off, wherein the FD has a second capacity when the reset transistor and the second transistor are off and the first transistor is on, wherein the FD has a third capacity when the reset transistor is off and the first transistor and the second transistor are on, wherein the second capacity is greater than the first capacity, and wherein the third capacity is greater than the second capacity. Ying (Figs. 2B and 4) teaches a first transistor (variable capacitive load 202 (fig. 4 M9)) connected in series to the FD (node 103) and the reset transistor (transistor M1) (Para 5 and 24); and a second transistor (variable capacitive load 202 (fig. 4 M11)) connected in series to the FD (103) and the reset transistor (M1), wherein the FD (103) has a first capacity (node voltage) when the reset transistor (M1), the first transistor (M9), and the second transistor (M11) are off, wherein the FD (103) has a second capacity (capacitance C3) when the reset transistor (M1)and the second transistor (M11) are off and the first transistor (M9) is on, wherein the FD (103) has a third capacity (capacitance C3+C5) when the reset transistor (M1) is off and the first transistor (M9) and the second transistor (M11) are on, wherein the second capacity (C3) is greater than the first capacity (node voltage), and wherein the third capacity (C3+C5) is greater than the second capacity (C3) (Para 25 and 26). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have provided a variable capacitive load as taught by Ying to the dual conversion gain transistor of Palaniappan, to allows the conversion gain for the pixel to be changed in response to several different thresholds of light intensity (Para 26 of Ying).
As to claim 2, Palaniappan teaches further comprising: a capacitor (dual conversion gain capacitor 122) connected to the first transistor (120) (Para 34).
As to claim 3, Palaniappan teaches wherein: the reset transistor (124) is connected to a power supply voltage (bias voltage supply terminal 134); and the capacitor (122) is connected in series to the first transistor (120) between the power supply voltage (134) and a ground voltage (ground).
As to claim 4, Palaniappan teaches wherein: the reset transistor (124) is connected to a power supply voltage (134); and a terminal of the capacitor (122) is connected to the power supply voltage (134) (Para 49). Palaniappan teaches the floating diffusion region is then reset at t.sub.7 by asserting reset transistor 124. This clears accumulated charge from floating diffusion region 118 and dual conversion gain capacitor 122 (Para 49). Vpix is applied to the dual conversion gain capacitor 122.
As to claim 5, Ying teaches further comprising: a capacitor (capacitor C5) connected to the second transistor (M11) (Para 25).
As to claim 6, Ying teaches wherein: the reset transistor (109) is connected to a power supply voltage (voltage supply Vdd 107); and a terminal of the capacitor (C5) is connected to the power supply voltage (107) via the second transistor (M11) (Para 25 and 26).
As to claim 7, Ying teaches wherein: a first terminal of the reset transistor (109) is connected to a power supply voltage (107); and a terminal of the capacitor (C5) is connected to a second terminal of the reset transistor (109) via the second transistor (M11) (Para 25 and 26).
As to claim 8, Palaniappan teaches further comprising: a first transfer transistor (transfer transistor 116) connected to the first photodiode (106) and the FD (118); and a second transfer transistor (transfer transistor 112) connected to the second photodiode (102) and the FD (118), wherein the first transfer transistor (116), the second transfer transistor (112), and the first transistor (120) are directly connected to the FD (118) (Para 23 and 25).
As to claim 9, Palaniappan teaches an image sensor comprising:
a first photodiode (first photosensitive area 106 (PD_E1)) connected to a floating diffusion region (FD) (floating diffusion region 118) via a first transfer transistor (transfer transistor 116) (Para 23);
a second photodiode (second photosensitive area 102 (PD_E2) connected to the FD (118) via a second transfer transistor (transfer transistor 112) (Para 25);
a reset transistor (reset transistor 124) connected to the FD (118) (Para 26);
a capacitor (dual conversion gain capacitor 122) connected to the FD (118) via a first transistor (transistor 120) (Para 25).
Palaniappan does not teach a second transistor connected to the FD and configured to receive a power supply voltage via the reset transistor, wherein the FD has a first capacity when the reset transistor, the first transistor, and the second transistor are off, wherein the FD has a second capacity when the reset transistor and the second transistor are off and the first transistor is on, wherein the FD has a third capacity when the reset transistor is off and the first transistor and the second transistor are on, wherein the second capacity is greater than the first capacity, and wherein the third capacity is greater than the second capacity. Ying (Figs. 2B and 4) teaches a first transistor (variable capacitive load 202 (fig. 4 M9)) connected in series to the FD (node 103) and the reset transistor (transistor M1) (Para 5 and 24); and a second transistor (variable capacitive load 202 (fig. 4 M11)) connected to the FD (103) and configured to receive a power supply voltage (voltage supply Vdd 107) via the reset transistor (109), wherein the FD (103) has a first capacity (node voltage) when the reset transistor (M1), the first transistor (M9), and the second transistor (M11) are off, wherein the FD (103) has a second capacity (capacitance C3) when the reset transistor (M1)and the second transistor (M11) are off and the first transistor (M9) is on, wherein the FD (103) has a third capacity (capacitance C3+C5) when the reset transistor (M1) is off and the first transistor (M9) and the second transistor (M11) are on, wherein the second capacity (C3) is greater than the first capacity (node voltage), and wherein the third capacity (C3+C5) is greater than the second capacity (C3) (Para 25 and 26). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have provided a variable capacitive load as taught by Ying to the dual conversion gain transistor of Palaniappan, to allows the conversion gain for the pixel to be changed in response to several different thresholds of light intensity (Para 26 of Ying).
As to claim 10, Palaniappan teaches wherein: the first transistor (120) is connected in series to the FD (118) and the reset transistor (124) (Para 25 and 26).
As to claim 11, Ying teaches wherein: the second transistor (M11) is connected in series to the FD (103) and the reset transistor (109) (Para 24-26).
As to claim 12, Palaniappan teaches an image sensor comprising:
a first photodiode (first photosensitive area 106 (PD_E1)) connected to a floating diffusion region (FD) (floating diffusion region 118) via a first transfer transistor (transfer transistor 116) (Para 23);
a second photodiode (second photosensitive area 102 (PD_E2) connected to the FD (118) via a second transfer transistor (transfer transistor 112) (Para 25);
a reset transistor (reset transistor 124) connected to the FD (118) (Para 26);
a first transistor (transistor 120) connected in series to the FD (118) and the reset transistor (124) (Para 25);
a first transistor (transistor 120) connected in series to the FD (118) and the reset transistor (124) (Para 25).
Palaniappan does not teach a capacitor connected to the FD via a second transistor, wherein the FD has a first capacity when the reset transistor, the first transistor, and the second transistor are off, wherein the FD has a second capacity when the reset transistor and the second transistor are off and the first transistor is on, wherein the FD has a third capacity when the reset transistor is off and the first transistor and the second transistor are on, wherein the second capacity is greater than the first capacity, and wherein the third capacity is greater than the second capacity. Ying (Figs. 2B and 4) teaches a first transistor (variable capacitive load 202 (fig. 4 M9)) connected in series to the FD (node 103) and the reset transistor (transistor M1) (Para 5 and 24); and a capacitor (capacitor C5) connected to the FD (103) via a second transistor (variable capacitive load 202 (fig. 4 M11)), wherein the FD (103) has a first capacity (node voltage) when the reset transistor (M1), the first transistor (M9), and the second transistor (M11) are off, wherein the FD (103) has a second capacity (capacitance C3) when the reset transistor (M1)and the second transistor (M11) are off and the first transistor (M9) is on, wherein the FD (103) has a third capacity (capacitance C3+C5) when the reset transistor (M1) is off and the first transistor (M9) and the second transistor (M11) are on, wherein the second capacity (C3) is greater than the first capacity (node voltage), and wherein the third capacity (C3+C5) is greater than the second capacity (C3) (Para 25 and 26). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have provided a variable capacitive load as taught by Ying to the dual conversion gain transistor of Palaniappan, to allows the conversion gain for the pixel to be changed in response to several different thresholds of light intensity (Para 26 of Ying).
As to claim 13, Ying teaches wherein: the reset transistor (109) is connected to a power supply voltage (voltage supply, Vdd 107); and the power supply voltage (107) is provided to a terminal of the capacitor (C5) via the reset transistor (109) and the second transistor (M11) (Para 25 and 26)
As to claim 14, Ying teaches wherein: a first terminal of the reset transistor (109) is connected to a power supply voltage (107); and a terminal of the capacitor (C5) is connected to a second terminal of the reset transistor (109) via the second transistor (M11) (Para 25 and 26).
Conclusion
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/CHRISTOPHER K PETERSON/Primary Examiner, Art Unit 2637 2/2/2026