Prosecution Insights
Last updated: July 17, 2026
Application No. 18/812,331

METHOD OF CONTROLLING FULL-BRIDGE RESONANT CONVERTER

Non-Final OA §102§103
Filed
Aug 22, 2024
Priority
Jun 21, 2024 — CN 2024108080277
Examiner
TRAN, NGUYEN
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Delta Electronics Inc.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
909 granted / 1088 resolved
+15.5% vs TC avg
Moderate +8% lift
Without
With
+7.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
35 currently pending
Career history
1126
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
84.6%
+44.6% vs TC avg
§102
11.1%
-28.9% vs TC avg
§112
1.9%
-38.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1088 resolved cases

Office Action

§102 §103
DETAILED ACTION 1. This action is in response to the application filed on 8/22/24. Notice of Pre-AIA or AIA Status 2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 4. Claims 1 and 6-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ye et al. (US 20160294294). Regarding claim 1: Ye et al. disclose (i.e. figures 2 and 7) a method of controlling a full-bridge resonant converter, the full-bridge resonant converter (i.e. figure 2) comprising a first bridge arm (i.e. Q1) (i.e. Q2) and a second bridge arm (i.e. Q3) (i.e. Q4) of an input side circuit (i.e. 102) of the full-bridge resonant converter (i.e. figure 2); the first bridge arm comprising a first upper switch (i.e. Q1) and a first lower switch (i.e. Q2), the second bridge arm comprising a second upper switch (i.e. Q3) and a second lower switch (i.e. Q4), the method comprising steps of: operating the first upper switch (i.e. Q1) in a first control action (i.e. on/off action) during a first time interval (i.e. figure 7: first interval from 767.4 to 771.0), wherein the first control action (i.e. on/off action) is an alternating action between a turned-off state (i.e. off) and a first period turned-on state (i.e. Q2 on first period), operating the first lower switch (i.e. Q2) in a second control action (i.e. on/off action) during the first time interval (i.e. figure 7: first interval from 767.4 to 771.0), wherein the second control action (i.e. on/off action) is an alternating action between the first period turned-on state (i.e. Q1 on) and the turned-off state (i.e. off), operating the second upper switch (i.e. Q3) in a third control action (i.e. on/off action) during the first time interval (i.e. figure 7: first interval from 767.4 to 771.0), wherein the third control action (i.e. on/off action) is an alternating action between a second period turned-on state (i.e. Q3 on) and the turned-off state (i.e. off), wherein a time length of the second period turned-on state (i.e. Q3 on second period) is greater than a time length of the first period turned-on state (i.e. Q2 on first period), operating the second lower switch (i.e. Q4) in a fourth control action (i.e. on/off action) during the first time interval (i.e. figure 7: first interval from 767.4 to 771.0), wherein the fourth control action (i.e. on/off action) is an alternating action between the turned-off state (i.e. off) and the second period turned-on state (i.e. Q3 on second period), operating the first upper switch (i.e. Q1) in the fourth control action (i.e. on/off action) during a second time interval (i.e. figure 7: second interval from 767.4 to 774.0) after the first time interval (i.e. figure 7: first interval from 767.4 to 771.0), operating the first lower switch (i.e. Q1) in the third control action (i.e. on/off action) during the second time interval (i.e. figure 7: second interval from 767.4 to 774.0), operating the second upper switch (i.e. Q2) in the second control action (i.e. on/off action) during the second time interval (i.e. figure 7: second interval from 767.4 to 774.0), and operating the second lower switch (i.e. Q2) in the first control action (i.e. 102) during the second time interval (i.e. figure 7: second interval from 767.4 to 774.0). Regarding claim 6: (i.e. figures 2 and 7) wherein in the first time interval (i.e. figure 7: first interval from 767.4 to 771.0), the first upper switch (i.e. Q1) and the first lower switch (i.e. Q2) operate in a hard switching (i.e. function of Q1, Q2). Regarding claim 7: (i.e. figures 2 and 7) wherein in the first time interval (i.e. figure 7: second interval from 767.4 to 774.0), the second upper switch (i.e. Q3) and the second lower switch (i.e. Q4) operate in a soft switching (i.e. function of Q3, Q4). Regarding claim 8: (i.e. figures 2 and 7) wherein in the second time interval (i.e. figure 7: second interval from 767.4 to 774.0), the first upper switch (i.e. Q1) and the first lower switch (i.e. Q2) operate in a soft switching (i.e. function of Q1, Q2). Regarding claim 9: (i.e. figures 2 and 7) wherein in the second time interval, the second upper switch (i.e. Q3) and the second lower switch (i.e. Q4) operate in a hard switching (i.e. function of Q3, Q4). Claim Rejections - 35 USC § 103 5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 6. Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over Ye et al. (US 20160294294) in view of Rehlaender et al. (US 20220399803). Regarding claim 2: Ye et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose in the first time interval, the first period turned-on state of the second control action of the first lower switch partially overlaps with the second period turned-on state of the third control action of the second upper switch. Rehlaender et al. disclose a power supply (i.e. figures 1-2) in the first time interval (i.e. interval of figure 2), the first period turned-on state of the second control action of the first lower switch (i.e. S3) partially overlaps (i.e. see on period of S3, S3) with the second period turned-on state of the third control action of the second upper switch (i.e. S2). Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Ye et al.’s invention with the power supply as disclose by Rehlaender et al. to balance the switching losses. Regarding claim 3: Ye et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose in the first time interval, the first period turned-on state of the first control action of the first upper switch partially overlaps with the second period turned-on state of the fourth control action of the second lower switch. Rehlaender et al. disclose a power supply (i.e. figures 1-2) in the first time interval (i.e. interval of figure 2), the first period turned-on state of the first control action of the first upper switch (i.e. S1) partially overlaps (i.e. see on period of S1, S4) with the second period turned-on state of the fourth control action of the second lower switch (i.e. S4). Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Ye et al.’s invention with the power supply as disclose by Rehlaender et al. to balance the switching losses. Regarding claim 4: Ye et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose in the second time interval, the first period turned-on state of the second control action of the second upper switch partially overlaps with the second period turned-on state of the third control action of the first lower switch. Rehlaender et al. disclose a power supply (i.e. figures 1-2) in the second time interval (i.e. interval of figure 2), the first period turned-on state of the second control action of the second upper switch (i.e. S2) partially overlaps (i.e. see signal of on period of S2, S3) with the second period turned-on state of the third control action of the first lower switch (i.e. S3). Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Ye et al.’s invention with the power supply as disclose by Rehlaender et al. to balance the switching losses. Regarding claim 5: Ye et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose in the second time interval, the first period turned-on state of the first control action of the second lower switch partially overlaps with the second period turned-on state of the fourth control action of the first upper switch. Rehlaender et al. disclose a power supply (i.e. figures 1-2) in the second time interval (i.e. interval of figure 2), the first period turned-on state of the first control action of the second lower switch (i.e. S3) partially overlaps (i.e. see on period of S2, S3) with the second period turned-on state of the fourth control action of the first upper switch (i.e. S2). Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Ye et al.’s invention with the power supply as disclose by Rehlaender et al. to balance the switching losses. Conclusion 7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN TRAN whose telephone number is (571)270-1269. The examiner can normally be reached Flex: M-F 8-7. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Nguyen Tran/Primary Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

Aug 22, 2024
Application Filed
Jun 03, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
91%
With Interview (+7.6%)
2y 5m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1088 resolved cases by this examiner. Grant probability derived from career allowance rate.

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