DETAILED ACTION
1. This action is in response to the amendment filed on 8/24/26.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
2. Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1 and 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Ye et al. (US 20160294294) in view of Rehlaender et al. (US 20230412086).
Regarding claim 1: Ye et al. disclose (i.e. figures 2 and 7) a method of controlling a full-bridge resonant converter, the full-bridge resonant converter (i.e. figure 2) comprising a first bridge arm (i.e. Q1) (i.e. Q2) and a second bridge arm (i.e. Q3) (i.e. Q4) of an input side circuit (i.e. 102) of the full-bridge resonant converter (i.e. figure 2);
the first bridge arm comprising a first upper switch (i.e. Q1) and a first lower switch (i.e. Q2), the second bridge arm comprising a second upper switch (i.e. Q3) and a second lower switch (i.e. Q4), the method comprising steps of:
operating the first upper switch (i.e. Q1) in a first control action (i.e. on/off action) during a first time interval (i.e. figure 7: first interval from 767.4 to 771.0), wherein the first control action (i.e. on/off action) is an alternating action between a turned-off state (i.e. off) and a first period turned-on state (i.e. Q2 on first period),
operating the first lower switch (i.e. Q2) in a second control action (i.e. on/off action) during the first time interval (i.e. figure 7: first interval from 767.4 to 771.0), wherein the second control action (i.e. on/off action) is an alternating action between the first period turned-on state (i.e. Q1 on) and the turned-off state (i.e. off),
operating the second upper switch (i.e. Q3) in a third control action (i.e. on/off action) during the first time interval (i.e. figure 7: first interval from 767.4 to 771.0), wherein the third control action (i.e. on/off action) is an alternating action between a second period turned-on state (i.e. Q3 on) and the turned-off state (i.e. off), wherein a time length of the second period turned-on state (i.e. Q3 on second period) is greater than a time length of the first period turned-on state (i.e. Q2 on first period),
operating the second lower switch (i.e. Q4) in a fourth control action (i.e. on/off action) during the first time interval (i.e. figure 7: first interval from 767.4 to 771.0), wherein the fourth control action (i.e. on/off action) is an alternating action between the turned-off state (i.e. off) and the second period turned-on state (i.e. Q3 on second period),
operating the first upper switch (i.e. Q1) in the fourth control action (i.e. on/off action) during a second time interval (i.e. figure 7: second interval from 767.4 to 774.0) after the first time interval (i.e. figure 7: first interval from 767.4 to 771.0),
operating the first lower switch (i.e. Q1) in the third control action (i.e. on/off action) during the second time interval (i.e. figure 7: second interval from 767.4 to 774.0), operating the second upper switch (i.e. Q2) in the second control action (i.e. on/off action) during the second time interval (i.e. figure 7: second interval from 767.4 to 774.0), and operating the second lower switch (i.e. Q2) in the first control action (i.e. 102) during the second time interval (i.e. figure 7: second interval from 767.4 to 774.0).
but does not specifically disclose the method further comprises: dynamically adjusting, in a mode-switching boundary region, a time length of the first period turned-on state and a time length of the second period turned-on state, so as to perform a seamless transition switching of the full-bridge resonant converter between the first time interval and the second time interval.
Rehlaender et al. disclose a converter (i.e. figures 1-2) having the method further comprises: dynamically adjusting, in a mode-switching boundary region (i.e. region of 11 to 14), a time length of the first period turned-on state (i.e. figure 2: mode 30, time length 15, S3 is reduce) and a time length of the second period turned-on state (i.e. figure 2: mode 30, time length 16, S2 is reduce), so as to perform a seamless transition (i.e. transistor of S3, S2) switching of the full-bridge resonant converter between the first time interval (i.e. interval from initial time 0t to end time t) and the second time interval (i.e. interval from initial time 0t to the end of 14).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Ye et al.’s invention with the converter as disclose by Rehlaender et al. to provide a modulation mode that is capable to improve a loss distribution.
Regarding claim 6: (i.e. figures 2 and 7) wherein in the first time interval (i.e. figure 7: first interval from 767.4 to 771.0), the first upper switch (i.e. Q1) and the first lower switch (i.e. Q2) operate in a hard switching (i.e. function of Q1, Q2).
Regarding claim 7: (i.e. figures 2 and 7) wherein in the first time interval (i.e. figure 7: second interval from 767.4 to 774.0), the second upper switch (i.e. Q3) and the second lower switch (i.e. Q4) operate in a soft switching (i.e. function of Q3, Q4).
Regarding claim 8: (i.e. figures 2 and 7) wherein in the second time interval (i.e. figure 7: second interval from 767.4 to 774.0), the first upper switch (i.e. Q1) and the first lower switch (i.e. Q2) operate in a soft switching (i.e. function of Q1, Q2).
Regarding claim 9: (i.e. figures 2 and 7) wherein in the second time interval, the second upper switch (i.e. Q3) and the second lower switch (i.e. Q4) operate in a hard switching (i.e. function of Q3, Q4).
5. Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over Ye et al. (US 20160294294) in view of Rehlaender et al. (US 20230412086) and further in view of Rehlaender et al. (US 20220399803, here after 803’).
Regarding claim 2: Ye et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose in the first time interval, the first period turned-on state of the second control action of the first lower switch partially overlaps with the second period turned-on state of the third control action of the second upper switch.
803’ disclose a power supply (i.e. figures 1-2) in the first time interval (i.e. interval of figure 2), the first period turned-on state of the second control action of the first lower switch (i.e. S3) partially overlaps (i.e. see on period of S3, S3) with the second period turned-on state of the third control action of the second upper switch (i.e. S2).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Ye et al.’s invention with the power supply as disclose by 803’ to balance the switching losses.
Regarding claim 3: Ye et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose in the first time interval, the first period turned-on state of the first control action of the first upper switch partially overlaps with the second period turned-on state of the fourth control action of the second lower switch. 803’ disclose a power supply (i.e. figures 1-2) in the first time interval (i.e. interval of figure 2), the first period turned-on state of the first control action of the first upper switch (i.e. S1) partially overlaps (i.e. see on period of S1, S4) with the second period turned-on state of the fourth control action of the second lower switch (i.e. S4).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Ye et al.’s invention with the power supply as disclose by 803’ to balance the switching losses.
Regarding claim 4: Ye et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose in the second time interval, the first period turned-on state of the second control action of the second upper switch partially overlaps with the second period turned-on state of the third control action of the first lower switch.
803’ disclose a power supply (i.e. figures 1-2) in the second time interval (i.e. interval of figure 2), the first period turned-on state of the second control action of the second upper switch (i.e. S2) partially overlaps (i.e. see signal of on period of S2, S3) with the second period turned-on state of the third control action of the first lower switch (i.e. S3).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Ye et al.’s invention with the power supply as disclose by 803’ to balance the switching losses.
Regarding claim 5: Ye et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose in the second time interval, the first period turned-on state of the first control action of the second lower switch partially overlaps with the second period turned-on state of the fourth control action of the first upper switch.
803’ disclose a power supply (i.e. figures 1-2) in the second time interval (i.e. interval of figure 2), the first period turned-on state of the first control action of the second lower switch (i.e. S3) partially overlaps (i.e. see on period of S2, S3) with the second period turned-on state of the fourth control action of the first upper switch (i.e. S2).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Ye et al.’s invention with the power supply as disclose by 803’to balance the switching losses.
Conclusion
6. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN TRAN whose telephone number is (571)270-1269. The examiner can normally be reached Flex: M-F 8-7.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nguyen Tran/Primary Examiner, Art Unit 2838
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